//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 core decoder ////
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//// 8051 core decoder ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/turb08051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Main 8051 core module. decodes instruction and creates ////
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//// Main 8051 core module. decodes instruction and creates ////
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//// control sigals. ////
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//// control sigals. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// optimize state machine, especially IDS ASS and AS3 ////
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//// optimize state machine, especially IDS ASS and AS3 ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.21 2003/06/03 17:09:57 simont
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// Revision 1.21 2003/06/03 17:09:57 simont
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// pipelined acces to axternal instruction interface added.
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// pipelined acces to axternal instruction interface added.
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//
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//
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// Revision 1.20 2003/05/06 11:10:38 simont
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// Revision 1.20 2003/05/06 11:10:38 simont
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// optimize state machine.
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// optimize state machine.
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//
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//
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// Revision 1.19 2003/05/06 09:41:35 simont
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// Revision 1.19 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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//
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//
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// Revision 1.18 2003/05/05 15:46:36 simont
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// Revision 1.18 2003/05/05 15:46:36 simont
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// add aditional alu destination to solve critical path.
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// add aditional alu destination to solve critical path.
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//
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//
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// Revision 1.17 2003/04/25 17:15:51 simont
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// Revision 1.17 2003/04/25 17:15:51 simont
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// change branch instruction execution (reduse needed clock periods).
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// change branch instruction execution (reduse needed clock periods).
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//
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//
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// Revision 1.16 2003/04/09 16:24:03 simont
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// Revision 1.16 2003/04/09 16:24:03 simont
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// change wr_sft to 2 bit wire.
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// change wr_sft to 2 bit wire.
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//
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//
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// Revision 1.15 2003/04/09 15:49:42 simont
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// Revision 1.15 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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//
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// Revision 1.14 2003/01/13 14:14:40 simont
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// Revision 1.14 2003/01/13 14:14:40 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.13 2002/10/23 16:53:39 simont
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// Revision 1.13 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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//
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//
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// Revision 1.12 2002/10/17 18:50:00 simont
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// Revision 1.12 2002/10/17 18:50:00 simont
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// cahnge interface to instruction rom
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// cahnge interface to instruction rom
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//
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//
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// Revision 1.11 2002/09/30 17:33:59 simont
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// Revision 1.11 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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`include "top_defines.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_decoder (clk, rst, op_in, op1_c,
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module oc8051_decoder (clk, rst, op_in, op1_c,
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ram_rd_sel_o, ram_wr_sel_o,
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ram_rd_sel_o, ram_wr_sel_o,
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bit_addr, wr_o, wr_sfr_o,
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bit_addr, wr_o, wr_sfr_o,
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src_sel1, src_sel2, src_sel3,
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src_sel1, src_sel2, src_sel3,
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alu_op_o, psw_set, eq, cy_sel, comp_sel,
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alu_op_o, psw_set, eq, cy_sel, comp_sel,
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pc_wr, pc_sel, rd, rmw, istb, mem_act, mem_wait,
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pc_wr, pc_sel, rd, rmw, istb, mem_act, mem_wait,
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wait_data);
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wait_data);
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//
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//
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// clk (in) clock
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// clk (in) clock
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// rst (in) reset
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// rst (in) reset
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// op_in (in) operation code [oc8051_op_select.op1]
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// op_in (in) operation code [oc8051_op_select.op1]
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// eq (in) compare result [oc8051_comp.eq]
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// eq (in) compare result [oc8051_comp.eq]
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// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
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// ram_rd_sel (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
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// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
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// ram_wr_sel (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
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// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
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// wr (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
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// src_sel1 (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
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// src_sel1 (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
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// src_sel2 (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
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// src_sel2 (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
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// src_sel3 (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
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// src_sel3 (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
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// alu_op (out) alu operation [oc8051_alu.op_code -r]
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// alu_op (out) alu operation [oc8051_alu.op_code -r]
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// psw_set (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
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// psw_set (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
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// cy_sel (out) carry in alu select [oc8051_cy_select.cy_sel -r]
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// cy_sel (out) carry in alu select [oc8051_cy_select.cy_sel -r]
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// comp_sel (out) compare source select [oc8051_comp.sel]
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// comp_sel (out) compare source select [oc8051_comp.sel]
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// bit_addr (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
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// bit_addr (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
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// pc_wr (out) pc write [oc8051_pc.wr]
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// pc_wr (out) pc write [oc8051_pc.wr]
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// pc_sel (out) pc select [oc8051_pc.pc_wr_sel]
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// pc_sel (out) pc select [oc8051_pc.pc_wr_sel]
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// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
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// rd (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
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// reti (out) return from interrupt [pin]
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// reti (out) return from interrupt [pin]
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// rmw (out) read modify write feature [oc8051_ports.rmw]
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// rmw (out) read modify write feature [oc8051_ports.rmw]
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// pc_wait (out)
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// pc_wait (out)
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//
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//
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input clk, rst, eq, mem_wait, wait_data;
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input clk, rst, eq, mem_wait, wait_data;
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input [7:0] op_in;
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input [7:0] op_in;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output [1:0] psw_set, cy_sel, wr_sfr_o, src_sel2, comp_sel;
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output [1:0] psw_set, cy_sel, wr_sfr_o, src_sel2, comp_sel;
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output [2:0] mem_act, src_sel1, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
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output [2:0] mem_act, src_sel1, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
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output [3:0] alu_op_o;
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output [3:0] alu_op_o;
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output rd;
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output rd;
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reg rmw;
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reg rmw;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg [3:0] alu_op;
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reg [3:0] alu_op;
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reg [1:0] src_sel2, comp_sel, psw_set, cy_sel, wr_sfr;
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reg [1:0] src_sel2, comp_sel, psw_set, cy_sel, wr_sfr;
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reg [2:0] mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel;
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reg [2:0] mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel;
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//
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//
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// op instruction buffer
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// op instruction buffer
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reg [1:0] state;
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reg [1:0] state;
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wire [1:0] state_dec;
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wire [1:0] state_dec;
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reg [7:0] op;
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reg [7:0] op;
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wire [7:0] op_cur;
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wire [7:0] op_cur;
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reg [2:0] ram_rd_sel_r;
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reg [2:0] ram_rd_sel_r;
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reg stb_i;
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reg stb_i;
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assign rd = !state[0] && !state[1] && !wait_data;// && !stb_o;
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assign rd = !state[0] && !state[1] && !wait_data;// && !stb_o;
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assign istb = (!state[1]) && stb_i;
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assign istb = (!state[1]) && stb_i;
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assign state_dec = wait_data ? 2'b00 : state;
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assign state_dec = wait_data ? 2'b00 : state;
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assign op_cur = mem_wait ? 8'h00
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assign op_cur = mem_wait ? 8'h00
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: (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
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: (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
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//assign op_cur = (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
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//assign op_cur = (state[0] || state[1] || mem_wait || wait_data) ? op : op_in;
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assign op1_c = op_cur[2:0];
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assign op1_c = op_cur[2:0];
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assign alu_op_o = wait_data ? `OC8051_ALU_NOP : alu_op;
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assign alu_op_o = wait_data ? `OC8051_ALU_NOP : alu_op;
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assign wr_sfr_o = wait_data ? `OC8051_WRS_N : wr_sfr;
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assign wr_sfr_o = wait_data ? `OC8051_WRS_N : wr_sfr;
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assign ram_rd_sel_o = wait_data ? ram_rd_sel_r : ram_rd_sel;
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assign ram_rd_sel_o = wait_data ? ram_rd_sel_r : ram_rd_sel;
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assign ram_wr_sel_o = wait_data ? `OC8051_RWS_DC : ram_wr_sel;
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assign ram_wr_sel_o = wait_data ? `OC8051_RWS_DC : ram_wr_sel;
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assign wr_o = wait_data ? 1'b0 : wr;
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assign wr_o = wait_data ? 1'b0 : wr;
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//
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//
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// main block
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// main block
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// unregisterd outputs
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// unregisterd outputs
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always @(op_cur or eq or state_dec or mem_wait)
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always @(op_cur or eq or state_dec or mem_wait)
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begin
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begin
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case (state_dec) /* synopsys full_case parallel_case */
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case (state_dec) /* synopsys full_case parallel_case */
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2'b01: begin
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2'b01: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : Div Instruction");
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$display("Executing : Div Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_B;
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ram_rd_sel = `OC8051_RRS_B;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : Mul Instruction");
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$display("Executing : Mul Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_B;
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ram_rd_sel = `OC8051_RRS_B;
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end
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end
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default begin
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default begin
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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end
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end
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endcase
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endcase
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stb_i = 1'b1;
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stb_i = 1'b1;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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pc_wr = `OC8051_PCW_N;
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pc_wr = `OC8051_PCW_N;
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pc_sel = `OC8051_PIS_DC;
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pc_sel = `OC8051_PIS_DC;
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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rmw = `OC8051_RMW_N;
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rmw = `OC8051_RMW_N;
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end
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end
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2'b10: begin
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2'b10: begin
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casex (op_cur) /* synopsys parallel_case */
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casex (op_cur) /* synopsys parallel_case */
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`OC8051_SJMP : begin
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`OC8051_SJMP : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : SJUMP Instruction");
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$display("Executing : SJUMP Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_DC;
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ram_rd_sel = `OC8051_RRS_DC;
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pc_wr = `OC8051_PCW_Y;
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pc_wr = `OC8051_PCW_Y;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_DC;
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comp_sel = `OC8051_CSS_DC;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_JC : begin
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`OC8051_JC : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : JC Instruction");
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$display("Executing : JC Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_PSW;
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ram_rd_sel = `OC8051_RRS_PSW;
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pc_wr = eq;
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pc_wr = eq;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_CY;
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comp_sel = `OC8051_CSS_CY;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_JNC : begin
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`OC8051_JNC : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : JNC Instruction");
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$display("Executing : JNC Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_PSW;
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ram_rd_sel = `OC8051_RRS_PSW;
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pc_wr = !eq;
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pc_wr = !eq;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_CY;
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comp_sel = `OC8051_CSS_CY;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_JNZ : begin
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`OC8051_JNZ : begin
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`ifdef OC8051_SIMULATION
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`ifdef OC8051_SIMULATION
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$display("Executing : JNZ Instruction");
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$display("Executing : JNZ Instruction");
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`endif
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`endif
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ram_rd_sel = `OC8051_RRS_ACC;
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ram_rd_sel = `OC8051_RRS_ACC;
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pc_wr = !eq;
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pc_wr = !eq;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_AZ;
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comp_sel = `OC8051_CSS_AZ;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
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end
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end
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`OC8051_JZ : begin
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`OC8051_JZ : begin
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`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
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$display("Executing : JZ Instruction");
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$display("Executing : JZ Instruction");
|
`endif
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`endif
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|
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ram_rd_sel = `OC8051_RRS_ACC;
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ram_rd_sel = `OC8051_RRS_ACC;
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pc_wr = eq;
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pc_wr = eq;
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pc_sel = `OC8051_PIS_SO1;
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pc_sel = `OC8051_PIS_SO1;
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comp_sel = `OC8051_CSS_AZ;
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comp_sel = `OC8051_CSS_AZ;
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bit_addr = 1'b0;
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bit_addr = 1'b0;
|
end
|
end
|
|
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : RET Instruction");
|
$display("Executing : RET Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_AL;
|
pc_sel = `OC8051_PIS_AL;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : RETI Instruction");
|
$display("Executing : RETI Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_AL;
|
pc_sel = `OC8051_PIS_AL;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_R Instruction");
|
$display("Executing : CJNE_R Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_I Instruction");
|
$display("Executing : CJNE_I Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_D Instruction");
|
$display("Executing : CJNE_D Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_C Instruction");
|
$display("Executing : CJNE_C Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DJNZ_R Instruction");
|
$display("Executing : DJNZ_R Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DJNZ_D Instruction");
|
$display("Executing : DJNZ_D Instruction");
|
`endif
|
`endif
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_DES;
|
comp_sel = `OC8051_CSS_DES;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : JB Instruction");
|
$display("Executing : JB Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : JBC Instruction");
|
$display("Executing : JBC Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : JMP_D Instruction");
|
$display("Executing : JMP_D Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_ALU;
|
pc_sel = `OC8051_PIS_ALU;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : JNB Instruction");
|
$display("Executing : JNB Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DIV Instruction");
|
$display("Executing : DIV Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : MUL Instruction");
|
$display("Executing : MUL Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
default begin
|
default begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
end
|
end
|
2'b11: begin
|
2'b11: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_R Instruction");
|
$display("Executing : CJNE_R Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_I Instruction");
|
$display("Executing : CJNE_I Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_D Instruction");
|
$display("Executing : CJNE_D Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : CJNE_C Instruction");
|
$display("Executing : CJNE_C Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DJNZ_R Instruction");
|
$display("Executing : DJNZ_R Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DJNZ_D Instruction");
|
$display("Executing : DJNZ_D Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : RET Instruction");
|
$display("Executing : RET Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_SP;
|
ram_rd_sel = `OC8051_RRS_SP;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_AH;
|
pc_sel = `OC8051_PIS_AH;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : RETI Instruction");
|
$display("Executing : RETI Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_SP;
|
ram_rd_sel = `OC8051_RRS_SP;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_AH;
|
pc_sel = `OC8051_PIS_AH;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : DIV Instruction");
|
$display("Executing : DIV Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : MUL Instruction");
|
$display("Executing : MUL Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
default begin
|
default begin
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
$display("Executing : RRS_DC Instruction");
|
$display("Executing : RRS_DC Instruction");
|
`endif
|
`endif
|
|
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
end
|
end
|
endcase
|
endcase
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
2'b00: begin
|
2'b00: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_ACALL :begin
|
`OC8051_ACALL :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_I11;
|
pc_sel = `OC8051_PIS_I11;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_AJMP : begin
|
`OC8051_AJMP : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_I11;
|
pc_sel = `OC8051_PIS_I11;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ADD_R : begin
|
`OC8051_ADD_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ADDC_R : begin
|
`OC8051_ADDC_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_R : begin
|
`OC8051_ANL_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DEC_R : begin
|
`OC8051_DEC_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_INC_R : begin
|
`OC8051_INC_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_R : begin
|
`OC8051_MOV_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_DR : begin
|
`OC8051_MOV_DR : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_RD : begin
|
`OC8051_MOV_RD : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_R : begin
|
`OC8051_ORL_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_SUBB_R : begin
|
`OC8051_SUBB_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XCH_R : begin
|
`OC8051_XCH_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XRL_R : begin
|
`OC8051_XRL_R : begin
|
ram_rd_sel = `OC8051_RRS_RN;
|
ram_rd_sel = `OC8051_RRS_RN;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
|
|
//op_code [7:1]
|
//op_code [7:1]
|
`OC8051_ADD_I : begin
|
`OC8051_ADD_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ADDC_I : begin
|
`OC8051_ADDC_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_I : begin
|
`OC8051_ANL_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DEC_I : begin
|
`OC8051_DEC_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_INC_I : begin
|
`OC8051_INC_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_I : begin
|
`OC8051_MOV_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_ID : begin
|
`OC8051_MOV_ID : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_DI : begin
|
`OC8051_MOV_DI : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOVX_IA : begin
|
`OC8051_MOVX_IA : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOVX_AI :begin
|
`OC8051_MOVX_AI :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_I : begin
|
`OC8051_ORL_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_SUBB_I : begin
|
`OC8051_SUBB_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XCH_I : begin
|
`OC8051_XCH_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XCHD :begin
|
`OC8051_XCHD :begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XRL_I : begin
|
`OC8051_XRL_I : begin
|
ram_rd_sel = `OC8051_RRS_I;
|
ram_rd_sel = `OC8051_RRS_I;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
|
|
//op_code [7:0]
|
//op_code [7:0]
|
`OC8051_ADD_D : begin
|
`OC8051_ADD_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ADDC_D : begin
|
`OC8051_ADDC_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_D : begin
|
`OC8051_ANL_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_C : begin
|
`OC8051_ANL_C : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_DD : begin
|
`OC8051_ANL_DD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_DC : begin
|
`OC8051_ANL_DC : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ANL_B : begin
|
`OC8051_ANL_B : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_ANL_NB : begin
|
`OC8051_ANL_NB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_CLR_B : begin
|
`OC8051_CLR_B : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_CPL_B : begin
|
`OC8051_CPL_B : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_DEC_D : begin
|
`OC8051_DEC_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_INC_D : begin
|
`OC8051_INC_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_INC_DP : begin
|
`OC8051_INC_DP : begin
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
/* `OC8051_JC : begin
|
/* `OC8051_JC : begin
|
ram_rd_sel = `OC8051_RRS_PSW;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end*/
|
end*/
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
|
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_SO2;
|
pc_sel = `OC8051_PIS_SO2;
|
comp_sel = `OC8051_CSS_BIT;
|
comp_sel = `OC8051_CSS_BIT;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
/* `OC8051_JNC : begin
|
/* `OC8051_JNC : begin
|
ram_rd_sel = `OC8051_RRS_PSW;
|
ram_rd_sel = `OC8051_RRS_PSW;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_CY;
|
comp_sel = `OC8051_CSS_CY;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JNZ : begin
|
`OC8051_JNZ : begin
|
ram_rd_sel = `OC8051_RRS_ACC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = !eq;
|
pc_wr = !eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_rd_sel = `OC8051_RRS_ACC;
|
ram_rd_sel = `OC8051_RRS_ACC;
|
pc_wr = eq;
|
pc_wr = eq;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_AZ;
|
comp_sel = `OC8051_CSS_AZ;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end*/
|
end*/
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_I16;
|
pc_sel = `OC8051_PIS_I16;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_LJMP : begin
|
`OC8051_LJMP : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_I16;
|
pc_sel = `OC8051_PIS_I16;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_D : begin
|
`OC8051_MOV_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_DD : begin
|
`OC8051_MOV_DD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOV_BC : begin
|
`OC8051_MOV_BC : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_MOV_CB : begin
|
`OC8051_MOV_CB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
ram_rd_sel = `OC8051_RRS_DPTR;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOVC_PC : begin
|
`OC8051_MOVC_PC : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOVX_PA : begin
|
`OC8051_MOVX_PA : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MOVX_AP : begin
|
`OC8051_MOVX_AP : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
ram_rd_sel = `OC8051_RRS_B;
|
ram_rd_sel = `OC8051_RRS_B;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_D : begin
|
`OC8051_ORL_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_AD : begin
|
`OC8051_ORL_AD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_CD : begin
|
`OC8051_ORL_CD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_ORL_B : begin
|
`OC8051_ORL_B : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_ORL_NB : begin
|
`OC8051_ORL_NB : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
`OC8051_POP : begin
|
`OC8051_POP : begin
|
ram_rd_sel = `OC8051_RRS_SP;
|
ram_rd_sel = `OC8051_RRS_SP;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_PUSH : begin
|
`OC8051_PUSH : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
ram_rd_sel = `OC8051_RRS_SP;
|
ram_rd_sel = `OC8051_RRS_SP;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
ram_rd_sel = `OC8051_RRS_SP;
|
ram_rd_sel = `OC8051_RRS_SP;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_SETB_B : begin
|
`OC8051_SETB_B : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b1;
|
bit_addr = 1'b1;
|
end
|
end
|
/* `OC8051_SJMP : begin
|
/* `OC8051_SJMP : begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_Y;
|
pc_wr = `OC8051_PCW_Y;
|
pc_sel = `OC8051_PIS_SO1;
|
pc_sel = `OC8051_PIS_SO1;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b0;
|
stb_i = 1'b0;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end*/
|
end*/
|
`OC8051_SUBB_D : begin
|
`OC8051_SUBB_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XCH_D : begin
|
`OC8051_XCH_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XRL_D : begin
|
`OC8051_XRL_D : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XRL_AD : begin
|
`OC8051_XRL_AD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
`OC8051_XRL_CD : begin
|
`OC8051_XRL_CD : begin
|
ram_rd_sel = `OC8051_RRS_D;
|
ram_rd_sel = `OC8051_RRS_D;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_Y;
|
rmw = `OC8051_RMW_Y;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
default: begin
|
default: begin
|
ram_rd_sel = `OC8051_RRS_DC;
|
ram_rd_sel = `OC8051_RRS_DC;
|
pc_wr = `OC8051_PCW_N;
|
pc_wr = `OC8051_PCW_N;
|
pc_sel = `OC8051_PIS_DC;
|
pc_sel = `OC8051_PIS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
comp_sel = `OC8051_CSS_DC;
|
rmw = `OC8051_RMW_N;
|
rmw = `OC8051_RMW_N;
|
stb_i = 1'b1;
|
stb_i = 1'b1;
|
bit_addr = 1'b0;
|
bit_addr = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
//
|
//
|
//
|
// registerd outputs
|
// registerd outputs
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end else if (!wait_data) begin
|
end else if (!wait_data) begin
|
case (state_dec) /* synopsys parallel_case */
|
case (state_dec) /* synopsys parallel_case */
|
2'b01: begin
|
2'b01: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOVC_PC :begin
|
`OC8051_MOVC_PC :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOVX_PA : begin
|
`OC8051_MOVX_PA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOVX_IA : begin
|
`OC8051_MOVX_IA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel1 <= #1 `OC8051_AS1_OP1;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
/* `OC8051_ACALL :begin
|
/* `OC8051_ACALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_AJMP : begin
|
`OC8051_AJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end*/
|
end*/
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_wr_sel <= #1 `OC8051_RWS_B;
|
ram_wr_sel <= #1 `OC8051_RWS_B;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_B;
|
ram_wr_sel <= #1 `OC8051_RWS_B;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
default begin
|
default begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
endcase
|
endcase
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
end
|
end
|
2'b10: begin
|
2'b10: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_ACALL :begin
|
`OC8051_ACALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel1 <= #1 `OC8051_AS1_PCH;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
`OC8051_JBC : begin
|
`OC8051_JBC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
end
|
end
|
default begin
|
default begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
endcase
|
endcase
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
|
|
2'b11: begin
|
2'b11: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
end
|
end
|
default begin
|
default begin
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
end
|
end
|
endcase
|
endcase
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
default: begin
|
default: begin
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_ACALL :begin
|
`OC8051_ACALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_AJMP : begin
|
`OC8051_AJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ADD_R : begin
|
`OC8051_ADD_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_R : begin
|
`OC8051_ADDC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_R : begin
|
`OC8051_ANL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CJNE_R : begin
|
`OC8051_CJNE_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DEC_R : begin
|
`OC8051_DEC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DJNZ_R : begin
|
`OC8051_DJNZ_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_R : begin
|
`OC8051_INC_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_R : begin
|
`OC8051_MOV_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_AR : begin
|
`OC8051_MOV_AR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DR : begin
|
`OC8051_MOV_DR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CR : begin
|
`OC8051_MOV_CR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_RD : begin
|
`OC8051_MOV_RD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_R : begin
|
`OC8051_ORL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_R : begin
|
`OC8051_SUBB_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XCH_R : begin
|
`OC8051_XCH_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
ram_wr_sel <= #1 `OC8051_RWS_RN;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_R : begin
|
`OC8051_XRL_R : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
|
|
//op_code [7:1]
|
//op_code [7:1]
|
`OC8051_ADD_I : begin
|
`OC8051_ADD_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_I : begin
|
`OC8051_ADDC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_I : begin
|
`OC8051_ANL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CJNE_I : begin
|
`OC8051_CJNE_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DEC_I : begin
|
`OC8051_DEC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_I : begin
|
`OC8051_INC_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_I : begin
|
`OC8051_MOV_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_ID : begin
|
`OC8051_MOV_ID : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_AI : begin
|
`OC8051_MOV_AI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DI : begin
|
`OC8051_MOV_DI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CI : begin
|
`OC8051_MOV_CI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_IA : begin
|
`OC8051_MOVX_IA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_AI :begin
|
`OC8051_MOVX_AI :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_I : begin
|
`OC8051_ORL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_I : begin
|
`OC8051_SUBB_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XCH_I : begin
|
`OC8051_XCH_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XCHD :begin
|
`OC8051_XCHD :begin
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
ram_wr_sel <= #1 `OC8051_RWS_I;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_I : begin
|
`OC8051_XRL_I : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
|
|
//op_code [7:0]
|
//op_code [7:0]
|
`OC8051_ADD_D : begin
|
`OC8051_ADD_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADD_C : begin
|
`OC8051_ADD_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_D : begin
|
`OC8051_ADDC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ADDC_C : begin
|
`OC8051_ADDC_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_D : begin
|
`OC8051_ANL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_C : begin
|
`OC8051_ANL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ANL_DD : begin
|
`OC8051_ANL_DD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_DC : begin
|
`OC8051_ANL_DC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_B : begin
|
`OC8051_ANL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_AND;
|
alu_op <= #1 `OC8051_ALU_AND;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ANL_NB : begin
|
`OC8051_ANL_NB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RR;
|
alu_op <= #1 `OC8051_ALU_RR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CJNE_D : begin
|
`OC8051_CJNE_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CJNE_C : begin
|
`OC8051_CJNE_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CLR_A : begin
|
`OC8051_CLR_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CLR_C : begin
|
`OC8051_CLR_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CLR_B : begin
|
`OC8051_CLR_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CPL_A : begin
|
`OC8051_CPL_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_CPL_C : begin
|
`OC8051_CPL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_CPL_B : begin
|
`OC8051_CPL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
alu_op <= #1 `OC8051_ALU_NOT;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DA : begin
|
`OC8051_DA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_DA;
|
alu_op <= #1 `OC8051_ALU_DA;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_DEC_A : begin
|
`OC8051_DEC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_DEC_D : begin
|
`OC8051_DEC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DIV : begin
|
`OC8051_DIV : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
alu_op <= #1 `OC8051_ALU_DIV;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_DJNZ_D : begin
|
`OC8051_DJNZ_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_A : begin
|
`OC8051_INC_A : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_INC_D : begin
|
`OC8051_INC_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_INC;
|
alu_op <= #1 `OC8051_ALU_INC;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_INC_DP : begin
|
`OC8051_INC_DP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
src_sel2 <= #1 `OC8051_AS2_ZERO;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
end
|
end
|
`OC8051_JB : begin
|
`OC8051_JB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JBC :begin
|
`OC8051_JBC :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JC : begin
|
`OC8051_JC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JMP_D : begin
|
`OC8051_JMP_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNB : begin
|
`OC8051_JNB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNC : begin
|
`OC8051_JNC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JNZ :begin
|
`OC8051_JNZ :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_JZ : begin
|
`OC8051_JZ : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_LCALL :begin
|
`OC8051_LCALL :begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_LJMP : begin
|
`OC8051_LJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_D : begin
|
`OC8051_MOV_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_C : begin
|
`OC8051_MOV_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_MOV_DA : begin
|
`OC8051_MOV_DA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DD : begin
|
`OC8051_MOV_DD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D3;
|
ram_wr_sel <= #1 `OC8051_RWS_D3;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CD : begin
|
`OC8051_MOV_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_BC : begin
|
`OC8051_MOV_BC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
cy_sel <= #1 `OC8051_CY_RAM;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_CB : begin
|
`OC8051_MOV_CB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOV_DP : begin
|
`OC8051_MOV_DP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
wr_sfr <= #1 `OC8051_WRS_DPTR;
|
end
|
end
|
`OC8051_MOVC_DP :begin
|
`OC8051_MOVC_DP :begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
src_sel3 <= #1 `OC8051_AS3_DP;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVC_PC : begin
|
`OC8051_MOVC_PC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel1 <= #1 `OC8051_AS1_PCL;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
alu_op <= #1 `OC8051_ALU_ADD;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_PA : begin
|
`OC8051_MOVX_PA : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MOVX_AP : begin
|
`OC8051_MOVX_AP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_MUL : begin
|
`OC8051_MUL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
alu_op <= #1 `OC8051_ALU_MUL;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_OV;
|
psw_set <= #1 `OC8051_PS_OV;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_D : begin
|
`OC8051_ORL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ORL_C : begin
|
`OC8051_ORL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_ORL_AD : begin
|
`OC8051_ORL_AD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_CD : begin
|
`OC8051_ORL_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_B : begin
|
`OC8051_ORL_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_OR;
|
alu_op <= #1 `OC8051_ALU_OR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_ORL_NB : begin
|
`OC8051_ORL_NB : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RL;
|
alu_op <= #1 `OC8051_ALU_RL;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_POP : begin
|
`OC8051_POP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_PUSH : begin
|
`OC8051_PUSH : begin
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
ram_wr_sel <= #1 `OC8051_RWS_SP;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_RET : begin
|
`OC8051_RET : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_RETI : begin
|
`OC8051_RETI : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_RL : begin
|
`OC8051_RL : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RL;
|
alu_op <= #1 `OC8051_ALU_RL;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RLC : begin
|
`OC8051_RLC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RR : begin
|
`OC8051_RR : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RR;
|
alu_op <= #1 `OC8051_ALU_RR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_RRC : begin
|
`OC8051_RRC : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RRC;
|
alu_op <= #1 `OC8051_ALU_RRC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SETB_C : begin
|
`OC8051_SETB_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_CY;
|
psw_set <= #1 `OC8051_PS_CY;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_SETB_B : begin
|
`OC8051_SETB_B : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_SJMP : begin
|
`OC8051_SJMP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
src_sel3 <= #1 `OC8051_AS3_PC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_SUBB_D : begin
|
`OC8051_SUBB_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SUBB_C : begin
|
`OC8051_SUBB_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
src_sel2 <= #1 `OC8051_AS2_OP2;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
alu_op <= #1 `OC8051_ALU_SUB;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_AC;
|
psw_set <= #1 `OC8051_PS_AC;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
cy_sel <= #1 `OC8051_CY_PSW;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_SWAP : begin
|
`OC8051_SWAP : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel1 <= #1 `OC8051_AS1_ACC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
alu_op <= #1 `OC8051_ALU_RLC;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XCH_D : begin
|
`OC8051_XCH_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
alu_op <= #1 `OC8051_ALU_XCH;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_1;
|
cy_sel <= #1 `OC8051_CY_1;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
wr_sfr <= #1 `OC8051_WRS_ACC2;
|
end
|
end
|
`OC8051_XRL_D : begin
|
`OC8051_XRL_D : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XRL_C : begin
|
`OC8051_XRL_C : begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel1 <= #1 `OC8051_AS1_OP2;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
wr_sfr <= #1 `OC8051_WRS_ACC1;
|
end
|
end
|
`OC8051_XRL_AD : begin
|
`OC8051_XRL_AD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel1 <= #1 `OC8051_AS1_RAM;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
src_sel2 <= #1 `OC8051_AS2_ACC;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
`OC8051_XRL_CD : begin
|
`OC8051_XRL_CD : begin
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
ram_wr_sel <= #1 `OC8051_RWS_D;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel1 <= #1 `OC8051_AS1_OP3;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
src_sel2 <= #1 `OC8051_AS2_RAM;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
alu_op <= #1 `OC8051_ALU_XOR;
|
wr <= #1 1'b1;
|
wr <= #1 1'b1;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
default: begin
|
default: begin
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
ram_wr_sel <= #1 `OC8051_RWS_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel1 <= #1 `OC8051_AS1_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
src_sel2 <= #1 `OC8051_AS2_DC;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
alu_op <= #1 `OC8051_ALU_NOP;
|
wr <= #1 1'b0;
|
wr <= #1 1'b0;
|
psw_set <= #1 `OC8051_PS_NOT;
|
psw_set <= #1 `OC8051_PS_NOT;
|
cy_sel <= #1 `OC8051_CY_0;
|
cy_sel <= #1 `OC8051_CY_0;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
src_sel3 <= #1 `OC8051_AS3_DC;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
wr_sfr <= #1 `OC8051_WRS_N;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
// remember current instruction
|
// remember current instruction
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst) op <= #1 2'b00;
|
if (rst) op <= #1 2'b00;
|
else if (state==2'b00) op <= #1 op_in;
|
else if (state==2'b00) op <= #1 op_in;
|
|
|
//
|
//
|
// in case of instructions that needs more than one clock set state
|
// in case of instructions that needs more than one clock set state
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst)
|
if (rst)
|
state <= #1 2'b11;
|
state <= #1 2'b11;
|
else if (!mem_wait & !wait_data) begin
|
else if (!mem_wait & !wait_data) begin
|
case (state) /* synopsys parallel_case */
|
case (state) /* synopsys parallel_case */
|
2'b10: state <= #1 2'b01;
|
2'b10: state <= #1 2'b01;
|
2'b11: state <= #1 2'b10;
|
2'b11: state <= #1 2'b10;
|
2'b00:
|
2'b00:
|
casex (op_in) /* synopsys full_case parallel_case */
|
casex (op_in) /* synopsys full_case parallel_case */
|
`OC8051_ACALL : state <= #1 2'b10;
|
`OC8051_ACALL : state <= #1 2'b10;
|
`OC8051_AJMP : state <= #1 2'b10;
|
`OC8051_AJMP : state <= #1 2'b10;
|
`OC8051_CJNE_R : state <= #1 2'b10;
|
`OC8051_CJNE_R : state <= #1 2'b10;
|
`OC8051_CJNE_I : state <= #1 2'b10;
|
`OC8051_CJNE_I : state <= #1 2'b10;
|
`OC8051_CJNE_D : state <= #1 2'b10;
|
`OC8051_CJNE_D : state <= #1 2'b10;
|
`OC8051_CJNE_C : state <= #1 2'b10;
|
`OC8051_CJNE_C : state <= #1 2'b10;
|
`OC8051_LJMP : state <= #1 2'b10;
|
`OC8051_LJMP : state <= #1 2'b10;
|
`OC8051_DJNZ_R : state <= #1 2'b10;
|
`OC8051_DJNZ_R : state <= #1 2'b10;
|
`OC8051_DJNZ_D : state <= #1 2'b10;
|
`OC8051_DJNZ_D : state <= #1 2'b10;
|
`OC8051_LCALL : state <= #1 2'b10;
|
`OC8051_LCALL : state <= #1 2'b10;
|
`OC8051_MOVC_DP : state <= #1 2'b11;
|
`OC8051_MOVC_DP : state <= #1 2'b11;
|
`OC8051_MOVC_PC : state <= #1 2'b11;
|
`OC8051_MOVC_PC : state <= #1 2'b11;
|
`OC8051_MOVX_IA : state <= #1 2'b10;
|
`OC8051_MOVX_IA : state <= #1 2'b10;
|
`OC8051_MOVX_AI : state <= #1 2'b10;
|
`OC8051_MOVX_AI : state <= #1 2'b10;
|
`OC8051_MOVX_PA : state <= #1 2'b10;
|
`OC8051_MOVX_PA : state <= #1 2'b10;
|
`OC8051_MOVX_AP : state <= #1 2'b10;
|
`OC8051_MOVX_AP : state <= #1 2'b10;
|
`OC8051_RET : state <= #1 2'b11;
|
`OC8051_RET : state <= #1 2'b11;
|
`OC8051_RETI : state <= #1 2'b11;
|
`OC8051_RETI : state <= #1 2'b11;
|
`OC8051_SJMP : state <= #1 2'b10;
|
`OC8051_SJMP : state <= #1 2'b10;
|
`OC8051_JB : state <= #1 2'b10;
|
`OC8051_JB : state <= #1 2'b10;
|
`OC8051_JBC : state <= #1 2'b10;
|
`OC8051_JBC : state <= #1 2'b10;
|
`OC8051_JC : state <= #1 2'b10;
|
`OC8051_JC : state <= #1 2'b10;
|
`OC8051_JMP_D : state <= #1 2'b10;
|
`OC8051_JMP_D : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNC : state <= #1 2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNB : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JNZ : state <= #1 2'b10;
|
`OC8051_JZ : state <= #1 2'b10;
|
`OC8051_JZ : state <= #1 2'b10;
|
`OC8051_DIV : state <= #1 2'b11;
|
`OC8051_DIV : state <= #1 2'b11;
|
`OC8051_MUL : state <= #1 2'b11;
|
`OC8051_MUL : state <= #1 2'b11;
|
// default : state <= #1 2'b00;
|
// default : state <= #1 2'b00;
|
endcase
|
endcase
|
default: state <= #1 2'b00;
|
default: state <= #1 2'b00;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
|
|
//
|
//
|
//in case of writing to external ram
|
//in case of writing to external ram
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <= #1 `OC8051_MAS_NO;
|
end else if (!rd) begin
|
end else if (!rd) begin
|
mem_act <= #1 `OC8051_MAS_NO;
|
mem_act <= #1 `OC8051_MAS_NO;
|
end else
|
end else
|
casex (op_cur) /* synopsys parallel_case */
|
casex (op_cur) /* synopsys parallel_case */
|
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
|
`OC8051_MOVX_AI : mem_act <= #1 `OC8051_MAS_RI_W;
|
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
|
`OC8051_MOVX_AP : mem_act <= #1 `OC8051_MAS_DPTR_W;
|
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
|
`OC8051_MOVX_IA : mem_act <= #1 `OC8051_MAS_RI_R;
|
`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
|
`OC8051_MOVX_PA : mem_act <= #1 `OC8051_MAS_DPTR_R;
|
`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_DP : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
|
`OC8051_MOVC_PC : mem_act <= #1 `OC8051_MAS_CODE;
|
default : mem_act <= #1 `OC8051_MAS_NO;
|
default : mem_act <= #1 `OC8051_MAS_NO;
|
endcase
|
endcase
|
end
|
end
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
begin
|
begin
|
if (rst) begin
|
if (rst) begin
|
ram_rd_sel_r <= #1 3'h0;
|
ram_rd_sel_r <= #1 3'h0;
|
end else begin
|
end else begin
|
ram_rd_sel_r <= #1 ram_rd_sel;
|
ram_rd_sel_r <= #1 ram_rd_sel;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
`ifdef OC8051_SIMULATION
|
`ifdef OC8051_SIMULATION
|
always @(op_cur)
|
always @(op_cur)
|
if (op_cur===8'hxx) begin
|
if (op_cur===8'hxx) begin
|
$display("%m:%0tns faulire: invalid instruction (oc8051_decoder)",$time);
|
$display("%m:%0tns faulire: invalid instruction (oc8051_decoder)",$time);
|
#22
|
#22
|
$finish;
|
$finish;
|
|
|
end
|
end
|
|
|
`endif
|
`endif
|
|
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|