//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/***************************************************************
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/***************************************************************
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Description:
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Description:
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Synchronizes the pulse from one clock to another
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Synchronizes the pulse from one clock to another
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* clock domain
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* clock domain
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***********************************************************************/
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***********************************************************************/
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//`timescale 1ns/100ps
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module half_dup_dble_reg (
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module half_dup_dble_reg (
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//outputs
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//outputs
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sync_out_pulse,
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sync_out_pulse,
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//inputs
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//inputs
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in_pulse,
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in_pulse,
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dest_clk,
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dest_clk,
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reset_n);
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reset_n);
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output sync_out_pulse; //output synchronised to slow clock
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output sync_out_pulse; //output synchronised to slow clock
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input in_pulse; //input based on fast clock, pulse
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input in_pulse; //input based on fast clock, pulse
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input dest_clk; //slow clock
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input dest_clk; //slow clock
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input reset_n;
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input reset_n;
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reg s1_sync_out,d_sync_out,s2_sync_out;
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reg s1_sync_out,d_sync_out,s2_sync_out;
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//double register the data in the slow clock domain
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//double register the data in the slow clock domain
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always @(posedge dest_clk or negedge reset_n)
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always @(posedge dest_clk or negedge reset_n)
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begin
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begin
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if (!reset_n)
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if (!reset_n)
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begin
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begin
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s1_sync_out <= 0;
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s1_sync_out <= 0;
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s2_sync_out <= 0;
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s2_sync_out <= 0;
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d_sync_out <= 0;
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d_sync_out <= 0;
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end // if (reset_n)
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end // if (reset_n)
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else
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else
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begin
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begin
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s1_sync_out <= in_pulse;
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s1_sync_out <= in_pulse;
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s2_sync_out <= s1_sync_out;
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s2_sync_out <= s1_sync_out;
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d_sync_out <= s2_sync_out;
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d_sync_out <= s2_sync_out;
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end // else: !if(reset_n)
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end // else: !if(reset_n)
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end // always @ (posedge dest_clk or negedge reset_n)
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end // always @ (posedge dest_clk or negedge reset_n)
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assign sync_out_pulse = d_sync_out;
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assign sync_out_pulse = d_sync_out;
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endmodule // dble_reg
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endmodule // dble_reg
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