//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//`timescale 1ns/100ps
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|
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/***************************************************************
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/***************************************************************
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Description:
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Description:
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|
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md_intf.v: This verilog file is for the mdio interface of the mac
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md_intf.v: This verilog file is for the mdio interface of the mac
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This block enables the station to communicate with the
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This block enables the station to communicate with the
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PHYs. This interface is kicked of by a go command from
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PHYs. This interface is kicked of by a go command from
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the application. This intiates the read and write operation
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the application. This intiates the read and write operation
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to the PHY. Upon completion of the operation it returns
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to the PHY. Upon completion of the operation it returns
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a indication called command done with the status of such
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a indication called command done with the status of such
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operation.
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operation.
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|
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***************************************************************/
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***************************************************************/
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/************** MODULE DECLARATION ****************************/
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/************** MODULE DECLARATION ****************************/
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module g_md_intf(
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module g_md_intf(
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scan_mode,
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scan_mode,
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reset_n,
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reset_n,
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mdio_clk,
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mdio_clk,
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mdio_in,
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mdio_in,
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mdio_outen_reg,
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mdio_outen_reg,
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mdio_out_reg,
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mdio_out_reg,
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mdio_regad,
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mdio_regad,
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mdio_phyad,
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mdio_phyad,
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mdio_op,
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mdio_op,
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go_mdio,
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go_mdio,
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mdio_datain,
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mdio_datain,
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mdio_dataout,
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mdio_dataout,
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mdio_cmd_done,
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mdio_cmd_done,
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mdio_stat,
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mdio_stat,
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mdc
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mdc
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);
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);
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parameter FIVE = 5'h5;
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parameter FIVE = 5'h5;
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parameter SIXTEEN = 5'd16;
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parameter SIXTEEN = 5'd16;
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parameter THIRTY_TWO = 5'd31;
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parameter THIRTY_TWO = 5'd31;
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parameter WRITE = 1;
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parameter WRITE = 1;
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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input scan_mode ; // scan_mode = 1
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input scan_mode ; // scan_mode = 1
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input reset_n; // reset from mac application interface
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input reset_n; // reset from mac application interface
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input mdio_in; // Input signal used to read data from PHY
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input mdio_in; // Input signal used to read data from PHY
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input mdio_clk; // Input signal used to read data from PHY
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input mdio_clk; // Input signal used to read data from PHY
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input[4:0] mdio_regad; // register address for the current PHY operation
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input[4:0] mdio_regad; // register address for the current PHY operation
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input[4:0] mdio_phyad; // Phy address to which the current operation is intended
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input[4:0] mdio_phyad; // Phy address to which the current operation is intended
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input mdio_op; // 1 = READ 0 = WRITE
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input mdio_op; // 1 = READ 0 = WRITE
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input go_mdio; // This is go command from the application for a MDIO
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input go_mdio; // This is go command from the application for a MDIO
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// transfer
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// transfer
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input[15:0] mdio_datain; // 16 bit Write value from application to MDIO block
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input[15:0] mdio_datain; // 16 bit Write value from application to MDIO block
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output[15:0] mdio_dataout; // 16 bit Read value for a MDIO transfer
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output[15:0] mdio_dataout; // 16 bit Read value for a MDIO transfer
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output mdio_cmd_done; // This is from MDIO to indicate mdio command completion
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output mdio_cmd_done; // This is from MDIO to indicate mdio command completion
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output mdio_stat; // Status of completion. 0 = No error 1= Error
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output mdio_stat; // Status of completion. 0 = No error 1= Error
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output mdio_out_reg; // Output signal used to write data to PHY
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output mdio_out_reg; // Output signal used to write data to PHY
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output mdio_outen_reg; // Enable signal 1= Output mode on 0 = Input mode
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output mdio_outen_reg; // Enable signal 1= Output mode on 0 = Input mode
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output mdc; // This is the MDIO clock
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output mdc; // This is the MDIO clock
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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wire mdc;
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wire mdc;
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wire [15:0] mdio_dataout;
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wire [15:0] mdio_dataout;
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wire go_mdio_sync;
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wire go_mdio_sync;
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reg mdio_stat;
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reg mdio_stat;
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reg mdio_cmd_done;
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reg mdio_cmd_done;
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reg mdio_out_en;
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reg mdio_out_en;
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reg mdio_out;
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reg mdio_out;
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half_dup_dble_reg U_dble_reg1 (
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half_dup_dble_reg U_dble_reg1 (
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//outputs
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//outputs
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.sync_out_pulse(go_mdio_sync),
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.sync_out_pulse(go_mdio_sync),
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//inputs
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//inputs
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.in_pulse(go_mdio),
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.in_pulse(go_mdio),
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.dest_clk(mdio_clk),
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.dest_clk(mdio_clk),
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.reset_n(reset_n)
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.reset_n(reset_n)
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);
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);
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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reg[3:0] mdio_cur_st;
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reg[3:0] mdio_cur_st;
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reg[3:0] mdio_nxt_st;
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reg[3:0] mdio_nxt_st;
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parameter mdio_idle_st= 4'd0,
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parameter mdio_idle_st= 4'd0,
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mdio_idle1_st = 4'd1,
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mdio_idle1_st = 4'd1,
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mdio_sfd1_st= 4'd2,
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mdio_sfd1_st= 4'd2,
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mdio_sfd2_st= 4'd3,
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mdio_sfd2_st= 4'd3,
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mdio_op1_st= 4'd4,
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mdio_op1_st= 4'd4,
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mdio_op2_st= 4'd5,
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mdio_op2_st= 4'd5,
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mdio_phyaddr_st= 4'd6,
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mdio_phyaddr_st= 4'd6,
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mdio_regaddr_st= 4'd7,
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mdio_regaddr_st= 4'd7,
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mdio_turnar_st= 4'd8,
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mdio_turnar_st= 4'd8,
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mdio_wrturn_st= 4'd9,
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mdio_wrturn_st= 4'd9,
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mdio_rdturn_st= 4'd10,
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mdio_rdturn_st= 4'd10,
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mdio_read_st= 4'd11,
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mdio_read_st= 4'd11,
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mdio_write_st= 4'd12,
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mdio_write_st= 4'd12,
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mdio_complete_st= 4'd13,
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mdio_complete_st= 4'd13,
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mdio_preamble_st= 4'd14;
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mdio_preamble_st= 4'd14;
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reg operation;
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reg operation;
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reg phyaddr_mux_sel;
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reg phyaddr_mux_sel;
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reg regaddr_mux_sel;
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reg regaddr_mux_sel;
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reg write_data_mux_sel;
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reg write_data_mux_sel;
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reg read_data_mux_sel;
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reg read_data_mux_sel;
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wire[4:0] inc_temp_count;
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wire[4:0] inc_temp_count;
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reg[4:0] temp_count;
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reg[4:0] temp_count;
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reg reset_temp_count;
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reg reset_temp_count;
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reg inc_count;
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reg inc_count;
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reg[4:0] phy_addr;
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reg[4:0] phy_addr;
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reg[4:0] reg_addr;
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reg[4:0] reg_addr;
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reg[15:0] transmit_data;
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reg[15:0] transmit_data;
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reg[15:0] receive_data;
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reg[15:0] receive_data;
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reg set_mdio_stat,clr_mdio_stat;
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reg set_mdio_stat,clr_mdio_stat;
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/***************** WIRE ASSIGNMENTS *************************/
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/***************** WIRE ASSIGNMENTS *************************/
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assign mdc = mdio_clk;
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assign mdc = mdio_clk;
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assign mdio_dataout = receive_data;
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assign mdio_dataout = receive_data;
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/******** SEQUENTIAL LOGIC **********************************/
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/******** SEQUENTIAL LOGIC **********************************/
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always @(mdio_cur_st or go_mdio_sync or inc_temp_count or
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always @(mdio_cur_st or go_mdio_sync or inc_temp_count or
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transmit_data or operation or phy_addr or reg_addr or temp_count or mdio_in)
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transmit_data or operation or phy_addr or reg_addr or temp_count or mdio_in)
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begin
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begin
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mdio_nxt_st = mdio_cur_st;
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mdio_nxt_st = mdio_cur_st;
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inc_count = 1'b0;
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inc_count = 1'b0;
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//mdio_cmd_done = 1'b0;
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//mdio_cmd_done = 1'b0;
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mdio_out = 1'b0;
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mdio_out = 1'b0;
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mdio_out_en = 1'b0;
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mdio_out_en = 1'b0;
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set_mdio_stat = 1'b0;
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set_mdio_stat = 1'b0;
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clr_mdio_stat = 1'b0;
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clr_mdio_stat = 1'b0;
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phyaddr_mux_sel = 1'b0;
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phyaddr_mux_sel = 1'b0;
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read_data_mux_sel = 1'b0;
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read_data_mux_sel = 1'b0;
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regaddr_mux_sel = 1'b0;
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regaddr_mux_sel = 1'b0;
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reset_temp_count = 1'b0;
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reset_temp_count = 1'b0;
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write_data_mux_sel = 1'b0;
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write_data_mux_sel = 1'b0;
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casex(mdio_cur_st ) // synopsys parallel_case full_case
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casex(mdio_cur_st ) // synopsys parallel_case full_case
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mdio_idle_st:
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mdio_idle_st:
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// This state waits for signal go_mdio
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// This state waits for signal go_mdio
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// upon this command from config block
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// upon this command from config block
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// mdio state machine starts to send
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// mdio state machine starts to send
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// SOF delimter
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// SOF delimter
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begin
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begin
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if(~go_mdio_sync)
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if(~go_mdio_sync)
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mdio_nxt_st = mdio_idle1_st; //mdio_sfd1_st;
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mdio_nxt_st = mdio_idle1_st; //mdio_sfd1_st;
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else
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else
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mdio_nxt_st = mdio_idle_st;
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mdio_nxt_st = mdio_idle_st;
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end
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end
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mdio_idle1_st:
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mdio_idle1_st:
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begin
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begin
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if (go_mdio_sync)
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if (go_mdio_sync)
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mdio_nxt_st = mdio_preamble_st;
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mdio_nxt_st = mdio_preamble_st;
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else
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else
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mdio_nxt_st = mdio_idle1_st;
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mdio_nxt_st = mdio_idle1_st;
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end
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end
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mdio_preamble_st:
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mdio_preamble_st:
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begin
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begin
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clr_mdio_stat = 1'b1;
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clr_mdio_stat = 1'b1;
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mdio_out_en = 1'b1;
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mdio_out_en = 1'b1;
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mdio_out = 1'b1;
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mdio_out = 1'b1;
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if (temp_count == THIRTY_TWO)
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if (temp_count == THIRTY_TWO)
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begin
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begin
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mdio_nxt_st = mdio_sfd1_st;
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mdio_nxt_st = mdio_sfd1_st;
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reset_temp_count = 1'b1;
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reset_temp_count = 1'b1;
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end
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end
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else
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else
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begin
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begin
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inc_count = 1'b1;
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inc_count = 1'b1;
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mdio_nxt_st = mdio_preamble_st;
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mdio_nxt_st = mdio_preamble_st;
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end
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end
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end
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end
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mdio_sfd1_st:
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mdio_sfd1_st:
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// This state shifts the first bit
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// This state shifts the first bit
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// of Start of Frame De-limiter
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// of Start of Frame De-limiter
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begin
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begin
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mdio_out_en = 1'b1;
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mdio_out_en = 1'b1;
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mdio_out = 1'b0;
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mdio_out = 1'b0;
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mdio_nxt_st = mdio_sfd2_st;
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mdio_nxt_st = mdio_sfd2_st;
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end
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end
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mdio_sfd2_st:
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mdio_sfd2_st:
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// This state shifts the second bit
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// This state shifts the second bit
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// of Start of Frame De-limiter
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// of Start of Frame De-limiter
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begin
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begin
|
mdio_out_en = 1'b1;
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mdio_out_en = 1'b1;
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mdio_out = 1'b1;
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mdio_out = 1'b1;
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mdio_nxt_st = mdio_op1_st;
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mdio_nxt_st = mdio_op1_st;
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end
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end
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mdio_op1_st:
|
mdio_op1_st:
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// This state shifts the first bit
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// This state shifts the first bit
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// of type of operation read/write
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// of type of operation read/write
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
if(operation)
|
if(operation)
|
mdio_out = 1'b0;
|
mdio_out = 1'b0;
|
else
|
else
|
mdio_out = 1'b1;
|
mdio_out = 1'b1;
|
//mdio_out = 1'b0; naveen 120199
|
//mdio_out = 1'b0; naveen 120199
|
mdio_nxt_st = mdio_op2_st;
|
mdio_nxt_st = mdio_op2_st;
|
end
|
end
|
|
|
mdio_op2_st:
|
mdio_op2_st:
|
// This state shifts the second bit
|
// This state shifts the second bit
|
// of type of operation read/write and
|
// of type of operation read/write and
|
// determines the appropriate next state
|
// determines the appropriate next state
|
// needed for such operation
|
// needed for such operation
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
mdio_nxt_st = mdio_phyaddr_st;
|
mdio_nxt_st = mdio_phyaddr_st;
|
if(operation)
|
if(operation)
|
mdio_out = 1'b1;
|
mdio_out = 1'b1;
|
else
|
else
|
mdio_out = 1'b0;
|
mdio_out = 1'b0;
|
end
|
end
|
|
|
mdio_phyaddr_st:
|
mdio_phyaddr_st:
|
// This state shifts the phy-address on the mdio
|
// This state shifts the phy-address on the mdio
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
phyaddr_mux_sel = 1'b1;
|
phyaddr_mux_sel = 1'b1;
|
if(inc_temp_count == FIVE)
|
if(inc_temp_count == FIVE)
|
begin
|
begin
|
reset_temp_count = 1'b1;
|
reset_temp_count = 1'b1;
|
mdio_out = phy_addr[4];
|
mdio_out = phy_addr[4];
|
mdio_nxt_st = mdio_regaddr_st;
|
mdio_nxt_st = mdio_regaddr_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
inc_count = 1'b1;
|
inc_count = 1'b1;
|
mdio_out = phy_addr[4];
|
mdio_out = phy_addr[4];
|
mdio_nxt_st = mdio_phyaddr_st;
|
mdio_nxt_st = mdio_phyaddr_st;
|
end
|
end
|
end
|
end
|
|
|
mdio_regaddr_st:
|
mdio_regaddr_st:
|
// This state shifts the register in the phy to which
|
// This state shifts the register in the phy to which
|
// this operation is intended
|
// this operation is intended
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
regaddr_mux_sel = 1'b1;
|
regaddr_mux_sel = 1'b1;
|
if(inc_temp_count == FIVE)
|
if(inc_temp_count == FIVE)
|
begin
|
begin
|
reset_temp_count = 1'b1;
|
reset_temp_count = 1'b1;
|
mdio_out = reg_addr[4];
|
mdio_out = reg_addr[4];
|
mdio_nxt_st = mdio_turnar_st;
|
mdio_nxt_st = mdio_turnar_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
inc_count = 1'b1;
|
inc_count = 1'b1;
|
mdio_out = reg_addr[4];
|
mdio_out = reg_addr[4];
|
mdio_nxt_st = mdio_regaddr_st;
|
mdio_nxt_st = mdio_regaddr_st;
|
end
|
end
|
end
|
end
|
|
|
mdio_turnar_st:
|
mdio_turnar_st:
|
// This state determines whether the output enable
|
// This state determines whether the output enable
|
// needs to on or of based on the type of command
|
// needs to on or of based on the type of command
|
begin
|
begin
|
//mdio_out_en = 1'b1;naveen 011299
|
//mdio_out_en = 1'b1;naveen 011299
|
mdio_out = 1'b1;
|
mdio_out = 1'b1;
|
if(operation)
|
if(operation)
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
mdio_nxt_st = mdio_wrturn_st;
|
mdio_nxt_st = mdio_wrturn_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mdio_out_en = 1'b0;
|
mdio_out_en = 1'b0;
|
mdio_nxt_st = mdio_rdturn_st;
|
mdio_nxt_st = mdio_rdturn_st;
|
end
|
end
|
end
|
end
|
|
|
mdio_wrturn_st:
|
mdio_wrturn_st:
|
// This state is used for write turn around
|
// This state is used for write turn around
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
mdio_out = 1'b0;
|
mdio_out = 1'b0;
|
mdio_nxt_st = mdio_write_st;
|
mdio_nxt_st = mdio_write_st;
|
end
|
end
|
|
|
mdio_rdturn_st:
|
mdio_rdturn_st:
|
// This state is used to read turn around state
|
// This state is used to read turn around state
|
// the output enable is switched off
|
// the output enable is switched off
|
begin
|
begin
|
if (mdio_in)
|
if (mdio_in)
|
set_mdio_stat = 1'b1;
|
set_mdio_stat = 1'b1;
|
mdio_out_en = 1'b0;
|
mdio_out_en = 1'b0;
|
mdio_nxt_st = mdio_read_st;
|
mdio_nxt_st = mdio_read_st;
|
end
|
end
|
|
|
mdio_write_st:
|
mdio_write_st:
|
// This state transfers the 16 bits of data to the
|
// This state transfers the 16 bits of data to the
|
// PHY
|
// PHY
|
begin
|
begin
|
mdio_out_en = 1'b1;
|
mdio_out_en = 1'b1;
|
write_data_mux_sel = 1'b1;
|
write_data_mux_sel = 1'b1;
|
if(inc_temp_count == SIXTEEN)
|
if(inc_temp_count == SIXTEEN)
|
begin
|
begin
|
reset_temp_count = 1'b1;
|
reset_temp_count = 1'b1;
|
mdio_out = transmit_data[15];
|
mdio_out = transmit_data[15];
|
mdio_nxt_st = mdio_complete_st;
|
mdio_nxt_st = mdio_complete_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
inc_count = 1'b1;
|
inc_count = 1'b1;
|
mdio_out = transmit_data[15];
|
mdio_out = transmit_data[15];
|
mdio_nxt_st = mdio_write_st;
|
mdio_nxt_st = mdio_write_st;
|
end
|
end
|
end
|
end
|
|
|
mdio_read_st:
|
mdio_read_st:
|
// This state receives the 16 bits of data from the
|
// This state receives the 16 bits of data from the
|
// PHY
|
// PHY
|
begin
|
begin
|
mdio_out_en = 1'b0;
|
mdio_out_en = 1'b0;
|
read_data_mux_sel = 1'b1;
|
read_data_mux_sel = 1'b1;
|
if(inc_temp_count == SIXTEEN)
|
if(inc_temp_count == SIXTEEN)
|
begin
|
begin
|
reset_temp_count = 1'b1;
|
reset_temp_count = 1'b1;
|
mdio_nxt_st = mdio_complete_st;
|
mdio_nxt_st = mdio_complete_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
inc_count = 1'b1;
|
inc_count = 1'b1;
|
mdio_nxt_st = mdio_read_st;
|
mdio_nxt_st = mdio_read_st;
|
end
|
end
|
end
|
end
|
|
|
mdio_complete_st:
|
mdio_complete_st:
|
// This completes the mdio transfers indicates to the
|
// This completes the mdio transfers indicates to the
|
// application of such complete
|
// application of such complete
|
begin
|
begin
|
mdio_nxt_st = mdio_idle_st;
|
mdio_nxt_st = mdio_idle_st;
|
mdio_out_en = 1'b0;
|
mdio_out_en = 1'b0;
|
read_data_mux_sel = 1'b0;
|
read_data_mux_sel = 1'b0;
|
//mdio_cmd_done = 1'b1;
|
//mdio_cmd_done = 1'b1;
|
// mdio_stat = 1'b0;
|
// mdio_stat = 1'b0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
always @(mdio_cur_st)
|
always @(mdio_cur_st)
|
mdio_cmd_done = (mdio_cur_st == 4'd13);
|
mdio_cmd_done = (mdio_cur_st == 4'd13);
|
|
|
|
|
always @(posedge mdio_clk or negedge reset_n)
|
always @(posedge mdio_clk or negedge reset_n)
|
begin
|
begin
|
if (!reset_n)
|
if (!reset_n)
|
mdio_stat <= 1'b0;
|
mdio_stat <= 1'b0;
|
else if (set_mdio_stat)
|
else if (set_mdio_stat)
|
mdio_stat <= 1'b1;
|
mdio_stat <= 1'b1;
|
else if (clr_mdio_stat)
|
else if (clr_mdio_stat)
|
mdio_stat <= 1'b0;
|
mdio_stat <= 1'b0;
|
end
|
end
|
|
|
|
|
// This latches the PHY address, Register address and the
|
// This latches the PHY address, Register address and the
|
// Transmit data and the type of operation
|
// Transmit data and the type of operation
|
//
|
//
|
always @(posedge mdio_clk or negedge reset_n)
|
always @(posedge mdio_clk or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
phy_addr <= 5'd0;
|
phy_addr <= 5'd0;
|
reg_addr <= 5'd0;
|
reg_addr <= 5'd0;
|
transmit_data <= 16'd0;
|
transmit_data <= 16'd0;
|
operation <= 1'b0;
|
operation <= 1'b0;
|
receive_data <= 16'd0;
|
receive_data <= 16'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(go_mdio_sync)
|
if(go_mdio_sync)
|
begin
|
begin
|
phy_addr <= mdio_phyad;
|
phy_addr <= mdio_phyad;
|
reg_addr <= mdio_regad;
|
reg_addr <= mdio_regad;
|
if(mdio_op == WRITE)
|
if(mdio_op == WRITE)
|
begin
|
begin
|
operation <= 1'b1;
|
operation <= 1'b1;
|
transmit_data <= mdio_datain;
|
transmit_data <= mdio_datain;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
operation <= 1'b0;
|
operation <= 1'b0;
|
phy_addr <= phy_addr;
|
phy_addr <= phy_addr;
|
transmit_data <= transmit_data;
|
transmit_data <= transmit_data;
|
reg_addr <= reg_addr;
|
reg_addr <= reg_addr;
|
// receive_data <= receive_data; naveen 011299
|
// receive_data <= receive_data; naveen 011299
|
end // else: !if(go_mdio)
|
end // else: !if(go_mdio)
|
|
|
if(phyaddr_mux_sel)
|
if(phyaddr_mux_sel)
|
begin
|
begin
|
/*
|
/*
|
phy_addr[0] <= phy_addr[1];
|
phy_addr[0] <= phy_addr[1];
|
phy_addr[1] <= phy_addr[2];
|
phy_addr[1] <= phy_addr[2];
|
phy_addr[2] <= phy_addr[3];
|
phy_addr[2] <= phy_addr[3];
|
phy_addr[3] <= phy_addr[4];
|
phy_addr[3] <= phy_addr[4];
|
*/
|
*/
|
phy_addr[4] <= phy_addr[3];
|
phy_addr[4] <= phy_addr[3];
|
phy_addr[3] <= phy_addr[2];
|
phy_addr[3] <= phy_addr[2];
|
phy_addr[2] <= phy_addr[1];
|
phy_addr[2] <= phy_addr[1];
|
phy_addr[1] <= phy_addr[0];
|
phy_addr[1] <= phy_addr[0];
|
end
|
end
|
if(regaddr_mux_sel)
|
if(regaddr_mux_sel)
|
begin
|
begin
|
reg_addr[4] <= reg_addr[3];
|
reg_addr[4] <= reg_addr[3];
|
reg_addr[3] <= reg_addr[2];
|
reg_addr[3] <= reg_addr[2];
|
reg_addr[2] <= reg_addr[1];
|
reg_addr[2] <= reg_addr[1];
|
reg_addr[1] <= reg_addr[0];
|
reg_addr[1] <= reg_addr[0];
|
end
|
end
|
if(write_data_mux_sel)
|
if(write_data_mux_sel)
|
begin
|
begin
|
transmit_data[15] <= transmit_data[14];
|
transmit_data[15] <= transmit_data[14];
|
transmit_data[14] <= transmit_data[13];
|
transmit_data[14] <= transmit_data[13];
|
transmit_data[13] <= transmit_data[12];
|
transmit_data[13] <= transmit_data[12];
|
transmit_data[12] <= transmit_data[11];
|
transmit_data[12] <= transmit_data[11];
|
transmit_data[11] <= transmit_data[10];
|
transmit_data[11] <= transmit_data[10];
|
transmit_data[10] <= transmit_data[9];
|
transmit_data[10] <= transmit_data[9];
|
transmit_data[9] <= transmit_data[8];
|
transmit_data[9] <= transmit_data[8];
|
transmit_data[8] <= transmit_data[7];
|
transmit_data[8] <= transmit_data[7];
|
transmit_data[7] <= transmit_data[6];
|
transmit_data[7] <= transmit_data[6];
|
transmit_data[6] <= transmit_data[5];
|
transmit_data[6] <= transmit_data[5];
|
transmit_data[5] <= transmit_data[4];
|
transmit_data[5] <= transmit_data[4];
|
transmit_data[4] <= transmit_data[3];
|
transmit_data[4] <= transmit_data[3];
|
transmit_data[3] <= transmit_data[2];
|
transmit_data[3] <= transmit_data[2];
|
transmit_data[2] <= transmit_data[1];
|
transmit_data[2] <= transmit_data[1];
|
transmit_data[1] <= transmit_data[0];
|
transmit_data[1] <= transmit_data[0];
|
end
|
end
|
if(read_data_mux_sel)
|
if(read_data_mux_sel)
|
begin
|
begin
|
receive_data[0] <= mdio_in;
|
receive_data[0] <= mdio_in;
|
receive_data[1] <= receive_data[0];
|
receive_data[1] <= receive_data[0];
|
receive_data[2] <= receive_data[1];
|
receive_data[2] <= receive_data[1];
|
receive_data[3] <= receive_data[2];
|
receive_data[3] <= receive_data[2];
|
receive_data[4] <= receive_data[3];
|
receive_data[4] <= receive_data[3];
|
receive_data[5] <= receive_data[4];
|
receive_data[5] <= receive_data[4];
|
receive_data[6] <= receive_data[5];
|
receive_data[6] <= receive_data[5];
|
receive_data[7] <= receive_data[6];
|
receive_data[7] <= receive_data[6];
|
receive_data[8] <= receive_data[7];
|
receive_data[8] <= receive_data[7];
|
receive_data[9] <= receive_data[8];
|
receive_data[9] <= receive_data[8];
|
receive_data[10] <= receive_data[9];
|
receive_data[10] <= receive_data[9];
|
receive_data[11] <= receive_data[10];
|
receive_data[11] <= receive_data[10];
|
receive_data[12] <= receive_data[11];
|
receive_data[12] <= receive_data[11];
|
receive_data[13] <= receive_data[12];
|
receive_data[13] <= receive_data[12];
|
receive_data[14] <= receive_data[13];
|
receive_data[14] <= receive_data[13];
|
receive_data[15] <= receive_data[14];
|
receive_data[15] <= receive_data[14];
|
end
|
end
|
// end // else: !if(go_mdio) naveen 011298
|
// end // else: !if(go_mdio) naveen 011298
|
end // else: !if(!reset_n)
|
end // else: !if(!reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
|
|
// Temporary counter used to shift the data on the mdio line
|
// Temporary counter used to shift the data on the mdio line
|
// This is also used to receive data on the line
|
// This is also used to receive data on the line
|
assign inc_temp_count = temp_count + 5'h1;
|
assign inc_temp_count = temp_count + 5'h1;
|
|
|
always @(posedge mdio_clk or negedge reset_n)
|
always @(posedge mdio_clk or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
mdio_cur_st <= mdio_idle_st;
|
mdio_cur_st <= mdio_idle_st;
|
else
|
else
|
mdio_cur_st <= mdio_nxt_st;
|
mdio_cur_st <= mdio_nxt_st;
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
|
|
reg mdio_outen_reg, mdio_out_reg;
|
reg mdio_outen_reg, mdio_out_reg;
|
|
|
//----------------------------------------------
|
//----------------------------------------------
|
// Scan fix done for negedge FF-Dinesh-A for A200
|
// Scan fix done for negedge FF-Dinesh-A for A200
|
// Note: Druring Scan Mode inverted mdio_clk used for
|
// Note: Druring Scan Mode inverted mdio_clk used for
|
// mdio_outen_reg & mdio_out_reg
|
// mdio_outen_reg & mdio_out_reg
|
//-----------------------------------------------
|
//-----------------------------------------------
|
wire mdio_clk_scan = (scan_mode) ? !mdio_clk : mdio_clk;
|
wire mdio_clk_scan = (scan_mode) ? !mdio_clk : mdio_clk;
|
|
|
always @(negedge mdio_clk_scan or negedge reset_n)
|
always @(negedge mdio_clk_scan or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
mdio_outen_reg <= 1'b0;
|
mdio_outen_reg <= 1'b0;
|
mdio_out_reg <= 1'b0;
|
mdio_out_reg <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mdio_outen_reg <= mdio_out_en;
|
mdio_outen_reg <= mdio_out_en;
|
mdio_out_reg <= mdio_out;
|
mdio_out_reg <= mdio_out;
|
end
|
end
|
|
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
|
|
always @(posedge mdio_clk or negedge reset_n)
|
always @(posedge mdio_clk or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
temp_count <= 5'b0;
|
temp_count <= 5'b0;
|
else
|
else
|
begin
|
begin
|
if(reset_temp_count)
|
if(reset_temp_count)
|
temp_count <= 5'b0;
|
temp_count <= 5'b0;
|
else if(inc_count)
|
else if(inc_count)
|
temp_count <= inc_temp_count;
|
temp_count <= inc_temp_count;
|
end // else: !if(reset_n)
|
end // else: !if(reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
end // always @ (posedge mdio_clk or negedge reset_n)
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
