//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//`timescale 1ns/100ps
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/***************************************************************
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/***************************************************************
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Description:
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Description:
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mii_intf.v: This verilog file is reduced mii interface for ethenet
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mii_intf.v: This verilog file is reduced mii interface for ethenet
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The transmit state machine generates a condition to indicate
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The transmit state machine generates a condition to indicate
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start transmit. This is done using strt_preamble. The transmit
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start transmit. This is done using strt_preamble. The transmit
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state machine upon detecting strt_preamble generates pre-amble
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state machine upon detecting strt_preamble generates pre-amble
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and start of frame de-limiter and then starts accepting the data
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and start of frame de-limiter and then starts accepting the data
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from the transmit block by asserting the transmit nibble ack.
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from the transmit block by asserting the transmit nibble ack.
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***************************************************************/
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***************************************************************/
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/************** MODULE DECLARATION ****************************/
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/************** MODULE DECLARATION ****************************/
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module g_mii_intf(
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module g_mii_intf(
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// Data and Control Signals to tx_fsm and rx_fsm
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// Data and Control Signals to tx_fsm and rx_fsm
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mi2rx_strt_rcv,
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mi2rx_strt_rcv,
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mi2rx_rcv_vld,
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mi2rx_rcv_vld,
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mi2rx_rx_byte,
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mi2rx_rx_byte,
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mi2rx_end_rcv,
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mi2rx_end_rcv,
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mi2rx_extend,
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mi2rx_extend,
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mi2rx_frame_err,
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mi2rx_frame_err,
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mi2rx_end_frame,
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mi2rx_end_frame,
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mi2rx_crs,
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mi2rx_crs,
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mi2tx_byte_ack,
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mi2tx_byte_ack,
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mi2tx_slot_vld,
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mi2tx_slot_vld,
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cfg_uni_mac_mode_change,
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cfg_uni_mac_mode_change,
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// Phy Signals
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// Phy Signals
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phy_tx_en,
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phy_tx_en,
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phy_tx_er,
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phy_tx_er,
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phy_txd,
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phy_txd,
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phy_tx_clk,
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phy_tx_clk,
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phy_rx_clk,
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phy_rx_clk,
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tx_reset_n,
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tx_reset_n,
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rx_reset_n,
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rx_reset_n,
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phy_rx_er,
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phy_rx_er,
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phy_rx_dv,
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phy_rx_dv,
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phy_rxd,
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phy_rxd,
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phy_crs,
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phy_crs,
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// rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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// rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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rx_sts_rx_er_reg,
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rx_sts_rx_er_reg,
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// Reset signal
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// Reset signal
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app_reset_n,
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app_reset_n,
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// Signals from Config Management
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// Signals from Config Management
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cf2mi_loopback_en,
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cf2mi_loopback_en,
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cf2mi_rmii_en,
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cf2mi_rmii_en,
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cf_mac_mode,
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cf_mac_mode,
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cf_chk_rx_dfl,
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cf_chk_rx_dfl,
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cf_silent_mode,
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cf_silent_mode,
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// Signal from Application to transmit JAM
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// Signal from Application to transmit JAM
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df2rx_dfl_dn,
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df2rx_dfl_dn,
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// Inputs from Transmit FSM
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// Inputs from Transmit FSM
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tx2mi_strt_preamble,
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tx2mi_strt_preamble,
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tx2mi_end_transmit,
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tx2mi_end_transmit,
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tx2mi_tx_byte,
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tx2mi_tx_byte,
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tx_ch_en
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tx_ch_en
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);
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);
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parameter NO_GMII_PREAMBLE = 5'b00111;
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parameter NO_GMII_PREAMBLE = 5'b00111;
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parameter NO_MII_PREAMBLE = 5'b01111;
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parameter NO_MII_PREAMBLE = 5'b01111;
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parameter NO_RMII_PREAMBLE = 5'b11111;
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parameter NO_RMII_PREAMBLE = 5'b11111;
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parameter GMII_JAM_COUNT = 5'b0011;
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parameter GMII_JAM_COUNT = 5'b0011;
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parameter MII_JAM_COUNT = 5'b0111;
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parameter MII_JAM_COUNT = 5'b0111;
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parameter RMII_JAM_COUNT = 5'b1111;
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parameter RMII_JAM_COUNT = 5'b1111;
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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output mi2rx_strt_rcv; // This is generated by the MII block to indicate start
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output mi2rx_strt_rcv; // This is generated by the MII block to indicate start
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// of receive data.
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// of receive data.
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output mi2rx_rcv_vld; // This signal is asserted by MII on reception of valid
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output mi2rx_rcv_vld; // This signal is asserted by MII on reception of valid
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// bytes to indicate to the RX block to accept data from PHY
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// bytes to indicate to the RX block to accept data from PHY
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output[7:0] mi2rx_rx_byte; // This the receive data from the PHY gathered as bytes
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output[7:0] mi2rx_rx_byte; // This the receive data from the PHY gathered as bytes
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output mi2rx_end_rcv; // This signal is asserted with the last data assembled
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output mi2rx_end_rcv; // This signal is asserted with the last data assembled
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output mi2rx_extend; // This signal is asserted during carrier extension (Receive)
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output mi2rx_extend; // This signal is asserted during carrier extension (Receive)
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output mi2rx_frame_err; // This signal is asserted during Dibit Error (In RMII Mode)
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output mi2rx_frame_err; // This signal is asserted during Dibit Error (In RMII Mode)
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// or Nibble Error in (MII Mode)
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// or Nibble Error in (MII Mode)
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output mi2rx_end_frame; // End of Frame
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output mi2rx_end_frame; // End of Frame
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output mi2rx_crs; // CRS signal in rx_clk domain
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output mi2rx_crs; // CRS signal in rx_clk domain
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output mi2tx_byte_ack; // MII block acknowledges a byte during transmit
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output mi2tx_byte_ack; // MII block acknowledges a byte during transmit
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output mi2tx_slot_vld; // MII block acknowledges valid slot during transmit // mfilardo
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output mi2tx_slot_vld; // MII block acknowledges valid slot during transmit // mfilardo
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output phy_tx_en; // Enable data on TX
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output phy_tx_en; // Enable data on TX
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output phy_tx_er; // Transmit Error (Used in Carrier Extension in 1000 Mode)
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output phy_tx_er; // Transmit Error (Used in Carrier Extension in 1000 Mode)
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output[7:0] phy_txd; // Transmit data on the line
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output[7:0] phy_txd; // Transmit data on the line
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input phy_tx_clk; // Transmit Clock in 10/100 Mb/s
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input phy_tx_clk; // Transmit Clock in 10/100 Mb/s
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output rx_sts_rx_er_reg; // rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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output rx_sts_rx_er_reg; // rx_er fix. need to fwd to mac wrapper, to drop rx_er pkts. mfilardo.
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input app_reset_n; // reset from the application interface
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input app_reset_n; // reset from the application interface
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input phy_rx_clk; // Receive Clock in 10/100/1000 Mb/s
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input phy_rx_clk; // Receive Clock in 10/100/1000 Mb/s
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input phy_rx_er; // Receive Error. Used in Carrier Extension in 1000 Mode
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input phy_rx_er; // Receive Error. Used in Carrier Extension in 1000 Mode
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input phy_rx_dv; // Receive Data Valid from the PHY
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input phy_rx_dv; // Receive Data Valid from the PHY
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input[7:0] phy_rxd; // Receive Data
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input[7:0] phy_rxd; // Receive Data
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input phy_crs; // Carrier Sense from the line
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input phy_crs; // Carrier Sense from the line
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input tx_reset_n;
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input tx_reset_n;
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input rx_reset_n;
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input rx_reset_n;
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input cf2mi_loopback_en; // loop back enable
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input cf2mi_loopback_en; // loop back enable
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input cf2mi_rmii_en; // RMII Mode
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input cf2mi_rmii_en; // RMII Mode
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input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
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input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
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input cf_chk_rx_dfl; // Check for Deferal
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input cf_chk_rx_dfl; // Check for Deferal
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input cf_silent_mode; // PHY Inactive
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input cf_silent_mode; // PHY Inactive
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input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
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input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
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input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
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input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
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// preamble on the line
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// preamble on the line
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input tx2mi_end_transmit; // This is provided by the TX block to
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input tx2mi_end_transmit; // This is provided by the TX block to
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// indicate end of transmit
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// indicate end of transmit
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input[7:0] tx2mi_tx_byte; // 8 bits of data from Tx block
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input[7:0] tx2mi_tx_byte; // 8 bits of data from Tx block
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input tx_ch_en; // Transmitt Enable
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input tx_ch_en; // Transmitt Enable
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input cfg_uni_mac_mode_change;
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input cfg_uni_mac_mode_change;
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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reg phy_tx_en;
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reg phy_tx_en;
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reg mi2tx_byte_ack;
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reg mi2tx_byte_ack;
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reg mi2tx_slot_vld;
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reg mi2tx_slot_vld;
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reg [7:0] phy_txd;
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reg [7:0] phy_txd;
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wire [7:0] mi2rx_rx_byte;
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wire [7:0] mi2rx_rx_byte;
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reg [7:0] mi2rx_rx_byte_in;
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reg [7:0] mi2rx_rx_byte_in;
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reg mi2rx_extend;
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reg mi2rx_extend;
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reg mi2rx_extend_err;
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reg mi2rx_extend_err;
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reg mi2rx_strt_rcv;
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reg mi2rx_strt_rcv;
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reg mi2rx_end_rcv;
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reg mi2rx_end_rcv;
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reg mi2rx_rcv_vld;
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reg mi2rx_rcv_vld;
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reg mi2rx_frame_err;
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reg mi2rx_frame_err;
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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reg [4:0] tx_preamble_cnt_val;
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reg [4:0] tx_preamble_cnt_val;
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reg strt_rcv_in;
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reg strt_rcv_in;
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reg end_rcv_in;
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reg end_rcv_in;
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reg rx_dv_in;
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reg rx_dv_in;
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reg rx_er_in;
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reg rx_er_in;
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reg rcv_valid_in;
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reg rcv_valid_in;
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reg [7:0] rxd_in;
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reg [7:0] rxd_in;
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parameter mii_rx_idle_st = 3'd0, mii_rx_pre_st = 3'd1,
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parameter mii_rx_idle_st = 3'd0, mii_rx_pre_st = 3'd1,
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mii_rx_byte_st = 3'd2, mii_rx_end_st = 3'd3,
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mii_rx_byte_st = 3'd2, mii_rx_end_st = 3'd3,
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mii_rx_dibit_st = 3'd4, mii_rx_nibble_st = 3'd5;
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mii_rx_dibit_st = 3'd4, mii_rx_nibble_st = 3'd5;
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reg [2:0] mii_rx_nxt_st;
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reg [2:0] mii_rx_nxt_st;
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reg [2:0] mii_rx_cur_st;
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reg [2:0] mii_rx_cur_st;
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parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
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parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
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mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
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mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
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mii_tx_nibble_st = 4'd5,
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mii_tx_nibble_st = 4'd5,
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mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
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mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
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mii_tx_dibit_end_st = 4'd8;
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mii_tx_dibit_end_st = 4'd8;
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reg [3:0] mii_tx_cur_st;
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reg [3:0] mii_tx_cur_st;
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reg [3:0] mii_tx_nxt_st;
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reg [3:0] mii_tx_nxt_st;
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wire receive_detect;
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wire receive_detect;
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wire pre_condition;
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wire pre_condition;
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wire sfd_condition;
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wire sfd_condition;
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wire tx_en;
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wire tx_en;
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wire tx_er;
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wire tx_er;
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wire [7:0] txd;
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wire [7:0] txd;
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wire byte_boundary_rx, byte_boundary_tx;
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wire byte_boundary_rx, byte_boundary_tx;
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reg tx_en_in;
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reg tx_en_in;
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reg tx_err_in;
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reg tx_err_in;
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reg tx_ext_in;
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reg tx_ext_in;
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reg tx_pre_in;
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reg tx_pre_in;
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reg tx_sfd_in;
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reg tx_sfd_in;
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reg tx_xfr_ack_in;
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reg tx_xfr_ack_in;
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reg inc_preamble_cntr;
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reg inc_preamble_cntr;
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reg rst_preamble_cntr;
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reg rst_preamble_cntr;
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reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
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reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
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reg rx_dv;
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reg rx_dv;
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reg rx_er;
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reg rx_er;
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reg rcv_err_in;
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reg rcv_err_in;
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reg mi2rx_end_frame_in;
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reg mi2rx_end_frame_in;
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reg [1:0] tx_dibit_in;
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reg [1:0] tx_dibit_in;
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reg mi2rx_extend_in, mi2rx_extend_err_in, mi2rx_end_frame;
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reg mi2rx_extend_in, mi2rx_extend_err_in, mi2rx_end_frame;
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reg crs_in;
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reg crs_in;
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reg phy_tx_er;
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reg phy_tx_er;
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|
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wire dibit_check_rx, dibit_check_tx;
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wire dibit_check_rx, dibit_check_tx;
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wire nibble_check_rx, nibble_check_tx;
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wire nibble_check_rx, nibble_check_tx;
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wire pre_condition_gmii, pre_condition_mii, pre_condition_rmii;
|
wire pre_condition_gmii, pre_condition_mii, pre_condition_rmii;
|
wire sfd_condition_gmii, sfd_condition_mii, sfd_condition_rmii;
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wire sfd_condition_gmii, sfd_condition_mii, sfd_condition_rmii;
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wire [3:0] tx_nibble_in;
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wire [3:0] tx_nibble_in;
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reg [7:0] rxd;
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reg [7:0] rxd;
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wire receive_detect_pulse;
|
wire receive_detect_pulse;
|
reg d_receive_detect;
|
reg d_receive_detect;
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|
|
|
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reg lb_tx_en, lb_tx_er;
|
reg lb_tx_en, lb_tx_er;
|
reg rx_dv_del;
|
reg rx_dv_del;
|
reg [1:0] rxd_del;
|
reg [1:0] rxd_del;
|
reg rx_dfl_dn;
|
reg rx_dfl_dn;
|
reg rx_dfl_dn_reg;
|
reg rx_dfl_dn_reg;
|
|
|
|
|
/******** SEQUENTIAL LOGIC **********************************/
|
/******** SEQUENTIAL LOGIC **********************************/
|
|
|
// This logic generates appropriate receive data valid
|
// This logic generates appropriate receive data valid
|
// in case of loop back
|
// in case of loop back
|
always @(tx_en or phy_rxd or txd or phy_rx_dv or tx_er or phy_crs
|
always @(tx_en or phy_rxd or txd or phy_rx_dv or tx_er or phy_crs
|
or cf2mi_loopback_en or phy_tx_en or phy_rx_er or
|
or cf2mi_loopback_en or phy_tx_en or phy_rx_er or
|
cf2mi_rmii_en or cf_mac_mode)
|
cf2mi_rmii_en or cf_mac_mode)
|
begin
|
begin
|
if(cf2mi_loopback_en)
|
if(cf2mi_loopback_en)
|
begin
|
begin
|
rx_dv_in = tx_en;
|
rx_dv_in = tx_en;
|
rx_er_in = tx_er;
|
rx_er_in = tx_er;
|
rxd_in = txd;
|
rxd_in = txd;
|
crs_in = (tx_en | tx_er) && cf_mac_mode;
|
crs_in = (tx_en | tx_er) && cf_mac_mode;
|
end // if (mii_loopback_en)
|
end // if (mii_loopback_en)
|
else
|
else
|
begin
|
begin
|
rx_dv_in = phy_rx_dv ;
|
rx_dv_in = phy_rx_dv ;
|
rx_er_in = phy_rx_er;
|
rx_er_in = phy_rx_er;
|
rxd_in = phy_rxd;
|
rxd_in = phy_rxd;
|
// *** NOTE ****
|
// *** NOTE ****
|
// phy_crs should be a combination of crs and tx_en
|
// phy_crs should be a combination of crs and tx_en
|
// In Full Duplex tx_en determines deferral in half duplex
|
// In Full Duplex tx_en determines deferral in half duplex
|
// crs determines deferral
|
// crs determines deferral
|
crs_in = (tx_en | tx_er);
|
crs_in = (tx_en | tx_er);
|
end // else: !if(mii_loopback_en)
|
end // else: !if(mii_loopback_en)
|
end
|
end
|
|
|
|
|
// Following state machine is to detect start preamble and
|
// Following state machine is to detect start preamble and
|
// transmit preamble and sfd and then the data.
|
// transmit preamble and sfd and then the data.
|
// This state machine also generates acknowledge to TX block
|
// This state machine also generates acknowledge to TX block
|
// to allow the TX block to update its byte pointers
|
// to allow the TX block to update its byte pointers
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
begin
|
begin
|
mii_tx_cur_st <= mii_tx_idle_st;
|
mii_tx_cur_st <= mii_tx_idle_st;
|
end
|
end
|
else if (tx_ch_en)
|
else if (tx_ch_en)
|
begin
|
begin
|
mii_tx_cur_st <= mii_tx_nxt_st;
|
mii_tx_cur_st <= mii_tx_nxt_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mii_tx_cur_st <= mii_tx_idle_st;
|
mii_tx_cur_st <= mii_tx_idle_st;
|
end
|
end
|
end
|
end
|
|
|
always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
|
always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
|
or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
|
or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
|
or tx_xfr_cnt or receive_detect
|
or tx_xfr_cnt or receive_detect
|
or receive_detect_pulse or cfg_uni_mac_mode_change)
|
or receive_detect_pulse or cfg_uni_mac_mode_change)
|
begin
|
begin
|
|
|
mii_tx_nxt_st = mii_tx_cur_st;
|
mii_tx_nxt_st = mii_tx_cur_st;
|
tx_en_in = 1'b0;
|
tx_en_in = 1'b0;
|
tx_pre_in = 1'b0;
|
tx_pre_in = 1'b0;
|
tx_sfd_in = 1'b0;
|
tx_sfd_in = 1'b0;
|
tx_err_in = 1'b0;
|
tx_err_in = 1'b0;
|
tx_ext_in = 1'b0;
|
tx_ext_in = 1'b0;
|
inc_preamble_cntr = 1'b0;
|
inc_preamble_cntr = 1'b0;
|
rst_preamble_cntr = 1'b0;
|
rst_preamble_cntr = 1'b0;
|
tx_xfr_ack_in = 1'b0;
|
tx_xfr_ack_in = 1'b0;
|
|
|
casex(mii_tx_cur_st) // synopsys parallel_case full_case
|
casex(mii_tx_cur_st) // synopsys parallel_case full_case
|
|
|
mii_tx_idle_st:
|
mii_tx_idle_st:
|
// wait from start from transmit state machine
|
// wait from start from transmit state machine
|
begin
|
begin
|
if(tx2mi_strt_preamble)
|
if(tx2mi_strt_preamble)
|
begin
|
begin
|
inc_preamble_cntr = 1'b1;
|
inc_preamble_cntr = 1'b1;
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_pre_in = 1'b1;
|
tx_pre_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
end
|
end
|
else
|
else
|
mii_tx_nxt_st = mii_tx_idle_st;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
end
|
end
|
|
|
mii_tx_pre_st:
|
mii_tx_pre_st:
|
// This state generates the preamble to be transmitted and
|
// This state generates the preamble to be transmitted and
|
// generates SFD before transitioning the data state
|
// generates SFD before transitioning the data state
|
begin
|
begin
|
if((tx_preamble_cnt_val == NO_GMII_PREAMBLE) && cf_mac_mode)
|
if((tx_preamble_cnt_val == NO_GMII_PREAMBLE) && cf_mac_mode)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
end
|
end
|
else if((tx_preamble_cnt_val == NO_MII_PREAMBLE) && !cf_mac_mode &&
|
else if((tx_preamble_cnt_val == NO_MII_PREAMBLE) && !cf_mac_mode &&
|
!cf2mi_rmii_en)
|
!cf2mi_rmii_en)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
end
|
end
|
else if((tx_preamble_cnt_val == NO_RMII_PREAMBLE) && !cf_mac_mode &&
|
else if((tx_preamble_cnt_val == NO_RMII_PREAMBLE) && !cf_mac_mode &&
|
cf2mi_rmii_en)
|
cf2mi_rmii_en)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_sfd_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
rst_preamble_cntr = 1'b1;
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
inc_preamble_cntr = 1'b1;
|
inc_preamble_cntr = 1'b1;
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_pre_in = 1'b1;
|
tx_pre_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
end
|
end
|
end
|
end
|
|
|
mii_tx_byte_st:
|
mii_tx_byte_st:
|
// This state picks up a byte from the transmit block
|
// This state picks up a byte from the transmit block
|
// before transmitting on the line
|
// before transmitting on the line
|
begin
|
begin
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b0;
|
tx_xfr_ack_in = 1'b0;
|
mii_tx_nxt_st = mii_tx_end_st;
|
mii_tx_nxt_st = mii_tx_end_st;
|
end
|
end
|
else if (!cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
else if (!cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
end
|
end
|
end
|
end
|
|
|
/*mii_tx_byte_st:
|
/*mii_tx_byte_st:
|
// This state picks up a byte from the transmit block
|
// This state picks up a byte from the transmit block
|
// before transmitting on the line
|
// before transmitting on the line
|
begin
|
begin
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
if(tx2mi_end_transmit && byte_boundary_tx )
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b0;
|
tx_xfr_ack_in = 1'b0;
|
mii_tx_nxt_st = mii_tx_end_st;
|
mii_tx_nxt_st = mii_tx_end_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
end
|
end
|
end*/
|
end*/
|
|
|
mii_tx_end_st:
|
mii_tx_end_st:
|
// This state checks for the end of transfer
|
// This state checks for the end of transfer
|
// and extend for carrier extension
|
// and extend for carrier extension
|
begin
|
begin
|
if(tx2mi_strt_preamble)
|
if(tx2mi_strt_preamble)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_pre_in = 1'b1;
|
tx_pre_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b0;
|
tx_en_in = 1'b0;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
end
|
end
|
end
|
end
|
|
|
/*mii_tx_nibble_st:
|
/*mii_tx_nibble_st:
|
// This state picks up a byte from the transmit block
|
// This state picks up a byte from the transmit block
|
// before transmitting on the line
|
// before transmitting on the line
|
begin
|
begin
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
end
|
end
|
end*/
|
end*/
|
|
|
mii_tx_nibble_st: // Mandar
|
mii_tx_nibble_st: // Mandar
|
// This state picks up a byte from the transmit block
|
// This state picks up a byte from the transmit block
|
// before transmitting on the line
|
// before transmitting on the line
|
begin
|
begin
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
if(tx2mi_end_transmit && !byte_boundary_tx )
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
mii_tx_nxt_st = mii_tx_nibble_end_st;
|
end
|
end
|
else if (cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
else if (cf_mac_mode & cfg_uni_mac_mode_change) // Mandar
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
mii_tx_nxt_st = mii_tx_nibble_st;
|
end
|
end
|
end
|
end
|
|
|
mii_tx_nibble_end_st:
|
mii_tx_nibble_end_st:
|
// This state checks for the end of transfer
|
// This state checks for the end of transfer
|
// and extend for carrier extension
|
// and extend for carrier extension
|
begin
|
begin
|
if(tx2mi_strt_preamble)
|
if(tx2mi_strt_preamble)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_pre_in = 1'b1;
|
tx_pre_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b0;
|
tx_en_in = 1'b0;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
end
|
end
|
end
|
end
|
|
|
mii_tx_dibit_st:
|
mii_tx_dibit_st:
|
// This state picks up a byte from the transmit block
|
// This state picks up a byte from the transmit block
|
// before transmitting on the line
|
// before transmitting on the line
|
begin
|
begin
|
if(tx2mi_end_transmit && (tx_xfr_cnt[0]) && (tx_xfr_cnt[1]) )
|
if(tx2mi_end_transmit && (tx_xfr_cnt[0]) && (tx_xfr_cnt[1]) )
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_dibit_end_st;
|
mii_tx_nxt_st = mii_tx_dibit_end_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
mii_tx_nxt_st = mii_tx_dibit_st;
|
end
|
end
|
end
|
end
|
|
|
mii_tx_dibit_end_st:
|
mii_tx_dibit_end_st:
|
// This state checks for the end of transfer
|
// This state checks for the end of transfer
|
// and extend for carrier extension
|
// and extend for carrier extension
|
begin
|
begin
|
if(tx2mi_strt_preamble)
|
if(tx2mi_strt_preamble)
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
tx_pre_in = 1'b1;
|
tx_pre_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
mii_tx_nxt_st = mii_tx_pre_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
tx_en_in = 1'b1;
|
tx_en_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
mii_tx_nxt_st = mii_tx_idle_st;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end // end always
|
end // end always
|
|
|
// All the data, enable and ack signals leaving this blocks are
|
// All the data, enable and ack signals leaving this blocks are
|
// registered tx_data and tx_en are outputs going to PHY tx_nibble_ack
|
// registered tx_data and tx_en are outputs going to PHY tx_nibble_ack
|
// is indicating to the TX block of acceptance of data nibble
|
// is indicating to the TX block of acceptance of data nibble
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
begin
|
begin
|
lb_tx_en <= 1'b0;
|
lb_tx_en <= 1'b0;
|
lb_tx_er <= 1'b0;
|
lb_tx_er <= 1'b0;
|
phy_tx_en <= 1'b0;
|
phy_tx_en <= 1'b0;
|
phy_tx_er <= 1'b0;
|
phy_tx_er <= 1'b0;
|
mi2tx_byte_ack <= 1'b0;
|
mi2tx_byte_ack <= 1'b0;
|
mi2tx_slot_vld <= 1'b0;
|
mi2tx_slot_vld <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
lb_tx_en <= tx_en_in;
|
lb_tx_en <= tx_en_in;
|
lb_tx_er <= tx_err_in;
|
lb_tx_er <= tx_err_in;
|
phy_tx_en <= (cf_silent_mode) ? 1'b0 : tx_en_in;
|
phy_tx_en <= (cf_silent_mode) ? 1'b0 : tx_en_in;
|
phy_tx_er <= (cf_silent_mode) ? 1'b0 : tx_err_in;
|
phy_tx_er <= (cf_silent_mode) ? 1'b0 : tx_err_in;
|
mi2tx_byte_ack <= (cf_mac_mode || (cf2mi_rmii_en && tx_xfr_cnt[1] && !tx_xfr_cnt[0]) ||
|
mi2tx_byte_ack <= (cf_mac_mode || (cf2mi_rmii_en && tx_xfr_cnt[1] && !tx_xfr_cnt[0]) ||
|
(!cf2mi_rmii_en && nibble_check_tx)) ? tx_xfr_ack_in : 1'b0;
|
(!cf2mi_rmii_en && nibble_check_tx)) ? tx_xfr_ack_in : 1'b0;
|
mi2tx_slot_vld <= (cf_mac_mode || (cf2mi_rmii_en && tx_slot_xfr_cnt[1] && !tx_slot_xfr_cnt[0]) ||
|
mi2tx_slot_vld <= (cf_mac_mode || (cf2mi_rmii_en && tx_slot_xfr_cnt[1] && !tx_slot_xfr_cnt[0]) ||
|
(!cf2mi_rmii_en && tx_slot_xfr_cnt[0] )) ? (tx_xfr_ack_in || inc_preamble_cntr) : 1'b0;
|
(!cf2mi_rmii_en && tx_slot_xfr_cnt[0] )) ? (tx_xfr_ack_in || inc_preamble_cntr) : 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
begin
|
begin
|
phy_txd[7:0] <= 8'b00000000;
|
phy_txd[7:0] <= 8'b00000000;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (cf_mac_mode)
|
if (cf_mac_mode)
|
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
|
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
|
8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
|
8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
|
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
|
4'b1101 : tx_nibble_in) ;
|
4'b1101 : tx_nibble_in) ;
|
else if (!cf_mac_mode && cf2mi_rmii_en)
|
else if (!cf_mac_mode && cf2mi_rmii_en)
|
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
|
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
|
2'b11 : tx_dibit_in) ;
|
2'b11 : tx_dibit_in) ;
|
end
|
end
|
end
|
end
|
assign receive_detect_pulse = receive_detect && !d_receive_detect;
|
assign receive_detect_pulse = receive_detect && !d_receive_detect;
|
|
|
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
d_receive_detect <= 0;
|
d_receive_detect <= 0;
|
else
|
else
|
d_receive_detect <= receive_detect;
|
d_receive_detect <= receive_detect;
|
end
|
end
|
// counter for the number transfers
|
// counter for the number transfers
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
tx_xfr_cnt <= 2'd0;
|
tx_xfr_cnt <= 2'd0;
|
else if(tx2mi_strt_preamble)
|
else if(tx2mi_strt_preamble)
|
tx_xfr_cnt <= 2'd0;
|
tx_xfr_cnt <= 2'd0;
|
else if(tx_xfr_ack_in)
|
else if(tx_xfr_ack_in)
|
tx_xfr_cnt <= tx_xfr_cnt + 1;
|
tx_xfr_cnt <= tx_xfr_cnt + 1;
|
end
|
end
|
|
|
// phy_tx_en_dly
|
// phy_tx_en_dly
|
reg phy_tx_en_dly;
|
reg phy_tx_en_dly;
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
phy_tx_en_dly <= 1'd0;
|
phy_tx_en_dly <= 1'd0;
|
else
|
else
|
phy_tx_en_dly <= phy_tx_en;
|
phy_tx_en_dly <= phy_tx_en;
|
end
|
end
|
|
|
wire phy_tx_en_fall;
|
wire phy_tx_en_fall;
|
assign phy_tx_en_fall = phy_tx_en_dly && !phy_tx_en;
|
assign phy_tx_en_fall = phy_tx_en_dly && !phy_tx_en;
|
|
|
// counter for the number transfers ...
|
// counter for the number transfers ...
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
tx_slot_xfr_cnt <= 2'd0;
|
tx_slot_xfr_cnt <= 2'd0;
|
else if(phy_tx_en_fall)
|
else if(phy_tx_en_fall)
|
tx_slot_xfr_cnt <= 2'd0;
|
tx_slot_xfr_cnt <= 2'd0;
|
else if(inc_preamble_cntr || tx_xfr_ack_in)
|
else if(inc_preamble_cntr || tx_xfr_ack_in)
|
tx_slot_xfr_cnt <= tx_slot_xfr_cnt + 1;
|
tx_slot_xfr_cnt <= tx_slot_xfr_cnt + 1;
|
end
|
end
|
|
|
assign nibble_check_tx = tx_xfr_cnt[0];
|
assign nibble_check_tx = tx_xfr_cnt[0];
|
assign dibit_check_tx= tx_xfr_cnt[0] && tx_xfr_cnt[1];
|
assign dibit_check_tx= tx_xfr_cnt[0] && tx_xfr_cnt[1];
|
assign byte_boundary_tx = (cf_mac_mode) ? 1'b1:
|
assign byte_boundary_tx = (cf_mac_mode) ? 1'b1:
|
((!cf_mac_mode && !cf2mi_rmii_en) ? nibble_check_tx : dibit_check_tx);
|
((!cf_mac_mode && !cf2mi_rmii_en) ? nibble_check_tx : dibit_check_tx);
|
|
|
assign tx_nibble_in = (tx_xfr_cnt[0]) ? tx2mi_tx_byte[3:0] : tx2mi_tx_byte[7:4];
|
assign tx_nibble_in = (tx_xfr_cnt[0]) ? tx2mi_tx_byte[3:0] : tx2mi_tx_byte[7:4];
|
|
|
/* always @(tx_xfr_cnt or tx2mi_tx_byte or phy_tx_clk)
|
/* always @(tx_xfr_cnt or tx2mi_tx_byte or phy_tx_clk)
|
begin
|
begin
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
else
|
else
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
end
|
end
|
*/
|
*/
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
tx_dibit_in <= 2'b0;
|
tx_dibit_in <= 2'b0;
|
else if(tx2mi_strt_preamble)
|
else if(tx2mi_strt_preamble)
|
tx_dibit_in <= 2'b0;
|
tx_dibit_in <= 2'b0;
|
else
|
else
|
begin
|
begin
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
if (!tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
tx_dibit_in <= tx2mi_tx_byte[1:0];
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
else if (!tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
tx_dibit_in <= tx2mi_tx_byte[3:2];
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
else if (tx_xfr_cnt[1] && !tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
tx_dibit_in <= tx2mi_tx_byte[5:4];
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
else if (tx_xfr_cnt[1] && tx_xfr_cnt[0])
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
tx_dibit_in <= tx2mi_tx_byte[7:6];
|
end
|
end
|
end
|
end
|
|
|
// counter for the number of preamble to be sent
|
// counter for the number of preamble to be sent
|
// before transmitting the sfd
|
// before transmitting the sfd
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
tx_preamble_cnt_val <= 5'd0;
|
tx_preamble_cnt_val <= 5'd0;
|
else if(rst_preamble_cntr)
|
else if(rst_preamble_cntr)
|
tx_preamble_cnt_val <= 5'd0;
|
tx_preamble_cnt_val <= 5'd0;
|
else if(inc_preamble_cntr)
|
else if(inc_preamble_cntr)
|
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
|
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
|
end
|
end
|
|
|
|
|
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
rx_dfl_dn_reg <= 1'b0;
|
rx_dfl_dn_reg <= 1'b0;
|
else if (df2rx_dfl_dn)
|
else if (df2rx_dfl_dn)
|
rx_dfl_dn_reg <= 1'b1;
|
rx_dfl_dn_reg <= 1'b1;
|
else
|
else
|
begin
|
begin
|
if (!phy_rx_dv && !phy_rx_er)
|
if (!phy_rx_dv && !phy_rx_er)
|
rx_dfl_dn_reg <= 1'b0;
|
rx_dfl_dn_reg <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
assign mi2rx_rx_byte = mi2rx_rx_byte_in;
|
assign mi2rx_rx_byte = mi2rx_rx_byte_in;
|
//assign rxd = (!cf_mac_mode && cf2mi_rmii_en)? mi2rx_rx_byte : mi2rx_rx_byte_in;
|
//assign rxd = (!cf_mac_mode && cf2mi_rmii_en)? mi2rx_rx_byte : mi2rx_rx_byte_in;
|
|
|
assign pre_condition_gmii = (!rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
assign pre_condition_gmii = (!rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
assign pre_condition_mii = (!rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
assign pre_condition_mii = (!rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
assign pre_condition_rmii = (!rxd[1] && rxd[0] && rx_dv
|
assign pre_condition_rmii = (!rxd[1] && rxd[0] && rx_dv
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
assign sfd_condition_gmii = (rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
assign sfd_condition_gmii = (rxd[7] && rxd[6] && !rxd[5] && rxd[4]
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
assign sfd_condition_mii = (rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
assign sfd_condition_mii = (rxd[3] && rxd[2] && !rxd[1] && rxd[0] && rx_dv
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
assign sfd_condition_rmii = (rxd[1] && rxd[0] && rx_dv
|
assign sfd_condition_rmii = (rxd[1] && rxd[0] && rx_dv
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
&& !rxd_del[1] && rxd_del[0] && rx_dv_del
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
&& !(!rx_dfl_dn_reg && cf_chk_rx_dfl));
|
|
|
|
|
|
|
assign pre_condition = (cf_mac_mode) ? pre_condition_gmii :
|
assign pre_condition = (cf_mac_mode) ? pre_condition_gmii :
|
((cf2mi_rmii_en) ? pre_condition_rmii : pre_condition_mii);
|
((cf2mi_rmii_en) ? pre_condition_rmii : pre_condition_mii);
|
|
|
assign sfd_condition = (cf_mac_mode) ? sfd_condition_gmii :
|
assign sfd_condition = (cf_mac_mode) ? sfd_condition_gmii :
|
((cf2mi_rmii_en) ? sfd_condition_rmii : sfd_condition_mii);
|
((cf2mi_rmii_en) ? sfd_condition_rmii : sfd_condition_mii);
|
|
|
// Following state machine is to detect strt preamble and
|
// Following state machine is to detect strt preamble and
|
// receive preamble and sfd and then the data.
|
// receive preamble and sfd and then the data.
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
begin
|
begin
|
mii_rx_cur_st <= mii_rx_idle_st;
|
mii_rx_cur_st <= mii_rx_idle_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mii_rx_cur_st <= mii_rx_nxt_st;
|
mii_rx_cur_st <= mii_rx_nxt_st;
|
end
|
end
|
end
|
end
|
|
|
always @(mii_rx_cur_st or rx_dv or rx_er or pre_condition or sfd_condition
|
always @(mii_rx_cur_st or rx_dv or rx_er or pre_condition or sfd_condition
|
or byte_boundary_rx or rxd or rx_xfr_cnt or cf2mi_rmii_en or cf_mac_mode)
|
or byte_boundary_rx or rxd or rx_xfr_cnt or cf2mi_rmii_en or cf_mac_mode)
|
begin
|
begin
|
mii_rx_nxt_st = mii_rx_cur_st;
|
mii_rx_nxt_st = mii_rx_cur_st;
|
strt_rcv_in = 1'b0;
|
strt_rcv_in = 1'b0;
|
end_rcv_in = 1'b0;
|
end_rcv_in = 1'b0;
|
rcv_valid_in = 1'b0;
|
rcv_valid_in = 1'b0;
|
rcv_err_in = 1'b0;
|
rcv_err_in = 1'b0;
|
mi2rx_extend_in = 1'b0;
|
mi2rx_extend_in = 1'b0;
|
mi2rx_extend_err_in = 1'b0;
|
mi2rx_extend_err_in = 1'b0;
|
mi2rx_end_frame_in = 1'b0;
|
mi2rx_end_frame_in = 1'b0;
|
|
|
casex(mii_rx_cur_st) // synopsys parallel_case full_case
|
casex(mii_rx_cur_st) // synopsys parallel_case full_case
|
|
|
mii_rx_idle_st:
|
mii_rx_idle_st:
|
// This state is waiting for pre-amble to
|
// This state is waiting for pre-amble to
|
// appear on the line in Receive mode
|
// appear on the line in Receive mode
|
begin
|
begin
|
if(pre_condition)
|
if(pre_condition)
|
mii_rx_nxt_st = mii_rx_pre_st;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
else
|
else
|
mii_rx_nxt_st = mii_rx_idle_st;
|
mii_rx_nxt_st = mii_rx_idle_st;
|
end
|
end
|
|
|
mii_rx_pre_st:
|
mii_rx_pre_st:
|
// This state checks the pre-amble and Waits for SFD on the line
|
// This state checks the pre-amble and Waits for SFD on the line
|
begin
|
begin
|
if(sfd_condition)
|
if(sfd_condition)
|
begin
|
begin
|
strt_rcv_in = 1'b1;
|
strt_rcv_in = 1'b1;
|
if(cf_mac_mode)
|
if(cf_mac_mode)
|
mii_rx_nxt_st = mii_rx_byte_st;
|
mii_rx_nxt_st = mii_rx_byte_st;
|
else if(!cf_mac_mode && !cf2mi_rmii_en)
|
else if(!cf_mac_mode && !cf2mi_rmii_en)
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
end
|
end
|
else if(pre_condition)
|
else if(pre_condition)
|
begin
|
begin
|
mii_rx_nxt_st = mii_rx_pre_st;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
end
|
end
|
else if(!rx_dv && rx_er && cf_mac_mode)
|
else if(!rx_dv && rx_er && cf_mac_mode)
|
begin
|
begin
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mi2rx_end_frame_in = 1'b1;
|
mi2rx_end_frame_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_idle_st;
|
mii_rx_nxt_st = mii_rx_idle_st;
|
end
|
end
|
end
|
end
|
|
|
mii_rx_byte_st:
|
mii_rx_byte_st:
|
// This state looks for data validity and latches di-bit2 and
|
// This state looks for data validity and latches di-bit2 and
|
// sends it to the receiver
|
// sends it to the receiver
|
begin
|
begin
|
if(rx_dv)
|
if(rx_dv)
|
begin
|
begin
|
rcv_valid_in = 1'b1;
|
rcv_valid_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_byte_st;
|
mii_rx_nxt_st = mii_rx_byte_st;
|
end
|
end
|
else if (!rx_dv && rx_er && cf_mac_mode)
|
else if (!rx_dv && rx_er && cf_mac_mode)
|
begin
|
begin
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
mi2rx_extend_in = (rxd == 8'h0F) ? 1'b1: 1'b0;
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
mi2rx_extend_err_in = (rxd == 8'h1F) ? 1'b1: 1'b0;
|
end_rcv_in = 1'b1;
|
end_rcv_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
mii_rx_nxt_st = mii_rx_pre_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
end_rcv_in = 1'b1;
|
end_rcv_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_end_st;
|
mii_rx_nxt_st = mii_rx_end_st;
|
end
|
end
|
end
|
end
|
|
|
mii_rx_end_st:
|
mii_rx_end_st:
|
// This state looks for data validity and latches di-bit2 and
|
// This state looks for data validity and latches di-bit2 and
|
// sends it to the receiver
|
// sends it to the receiver
|
mii_rx_nxt_st = mii_rx_idle_st;
|
mii_rx_nxt_st = mii_rx_idle_st;
|
|
|
mii_rx_nibble_st:
|
mii_rx_nibble_st:
|
begin
|
begin
|
if(rx_dv)
|
if(rx_dv)
|
begin
|
begin
|
rcv_valid_in = 1'b1;
|
rcv_valid_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
mii_rx_nxt_st = mii_rx_nibble_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
end_rcv_in = 1'b1;
|
end_rcv_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_end_st;
|
mii_rx_nxt_st = mii_rx_end_st;
|
if(rx_xfr_cnt[0])
|
if(rx_xfr_cnt[0])
|
rcv_err_in = 1'b1;
|
rcv_err_in = 1'b1;
|
end
|
end
|
end
|
end
|
|
|
mii_rx_dibit_st:
|
mii_rx_dibit_st:
|
begin
|
begin
|
if(rx_dv)
|
if(rx_dv)
|
begin
|
begin
|
rcv_valid_in = 1'b1;
|
rcv_valid_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
mii_rx_nxt_st = mii_rx_dibit_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
end_rcv_in = 1'b1;
|
end_rcv_in = 1'b1;
|
mii_rx_nxt_st = mii_rx_end_st;
|
mii_rx_nxt_st = mii_rx_end_st;
|
if(!(!rx_xfr_cnt[0] && !rx_xfr_cnt[1]))
|
if(!(!rx_xfr_cnt[0] && !rx_xfr_cnt[1]))
|
rcv_err_in = 1'b1;
|
rcv_err_in = 1'b1;
|
end
|
end
|
end
|
end
|
|
|
endcase
|
endcase
|
end // always @ (mii_rx_cur_st...
|
end // always @ (mii_rx_cur_st...
|
|
|
// counter for the number receives
|
// counter for the number receives
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
rx_xfr_cnt <= 2'd0;
|
rx_xfr_cnt <= 2'd0;
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
rx_xfr_cnt <= 2'd0;
|
rx_xfr_cnt <= 2'd0;
|
else if(rcv_valid_in)
|
else if(rcv_valid_in)
|
rx_xfr_cnt <= rx_xfr_cnt + 1;
|
rx_xfr_cnt <= rx_xfr_cnt + 1;
|
end
|
end
|
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
begin
|
begin
|
mi2rx_rx_byte_in <= 8'b0;
|
mi2rx_rx_byte_in <= 8'b0;
|
rxd <= 8'b0;
|
rxd <= 8'b0;
|
rxd_del <= 2'b0;
|
rxd_del <= 2'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rxd <= rxd_in;
|
rxd <= rxd_in;
|
// rxd_del <= rxd_in[1:0];
|
// rxd_del <= rxd_in[1:0];
|
rxd_del <= rxd[1:0];
|
rxd_del <= rxd[1:0];
|
|
|
if (cf_mac_mode)
|
if (cf_mac_mode)
|
mi2rx_rx_byte_in <= rxd;
|
mi2rx_rx_byte_in <= rxd;
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
begin
|
begin
|
if(!rx_xfr_cnt[0])
|
if(!rx_xfr_cnt[0])
|
mi2rx_rx_byte_in[3:0] <= rxd[3:0];
|
mi2rx_rx_byte_in[3:0] <= rxd[3:0];
|
else
|
else
|
mi2rx_rx_byte_in[7:4] <= rxd[3:0];
|
mi2rx_rx_byte_in[7:4] <= rxd[3:0];
|
end
|
end
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
else if(!cf_mac_mode && cf2mi_rmii_en)
|
begin
|
begin
|
if(!rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
if(!rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
mi2rx_rx_byte_in[1:0] <= rxd[1:0];
|
mi2rx_rx_byte_in[1:0] <= rxd[1:0];
|
else if(!rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
else if(!rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
mi2rx_rx_byte_in[3:2] <= rxd[1:0];
|
mi2rx_rx_byte_in[3:2] <= rxd[1:0];
|
else if(rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
else if(rx_xfr_cnt[1] && !rx_xfr_cnt[0])
|
mi2rx_rx_byte_in[5:4] <= rxd[1:0];
|
mi2rx_rx_byte_in[5:4] <= rxd[1:0];
|
else if(rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
else if(rx_xfr_cnt[1] && rx_xfr_cnt[0])
|
mi2rx_rx_byte_in[7:6] <= rxd[1:0];
|
mi2rx_rx_byte_in[7:6] <= rxd[1:0];
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
reg rx_sts_rx_er_reg;
|
reg rx_sts_rx_er_reg;
|
always @(posedge phy_rx_clk or negedge rx_reset_n) begin
|
always @(posedge phy_rx_clk or negedge rx_reset_n) begin
|
if(!rx_reset_n) begin
|
if(!rx_reset_n) begin
|
rx_sts_rx_er_reg <= 1'b0;
|
rx_sts_rx_er_reg <= 1'b0;
|
end
|
end
|
else if (mi2rx_strt_rcv) begin
|
else if (mi2rx_strt_rcv) begin
|
rx_sts_rx_er_reg <= 1'b0;
|
rx_sts_rx_er_reg <= 1'b0;
|
end
|
end
|
else if(phy_rx_dv && phy_rx_er) begin
|
else if(phy_rx_dv && phy_rx_er) begin
|
rx_sts_rx_er_reg <= 1'b1;
|
rx_sts_rx_er_reg <= 1'b1;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge rx_reset_n)
|
or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
begin
|
begin
|
mi2rx_rcv_vld <= 1'b0;
|
mi2rx_rcv_vld <= 1'b0;
|
end
|
end
|
else if(cf_mac_mode)
|
else if(cf_mac_mode)
|
mi2rx_rcv_vld <= rcv_valid_in;
|
mi2rx_rcv_vld <= rcv_valid_in;
|
else if(!cf_mac_mode && cf2mi_rmii_en && rx_xfr_cnt[0] && rx_xfr_cnt[1])
|
else if(!cf_mac_mode && cf2mi_rmii_en && rx_xfr_cnt[0] && rx_xfr_cnt[1])
|
mi2rx_rcv_vld <= rcv_valid_in;
|
mi2rx_rcv_vld <= rcv_valid_in;
|
else if(!cf_mac_mode && !cf2mi_rmii_en && rx_xfr_cnt[0])
|
else if(!cf_mac_mode && !cf2mi_rmii_en && rx_xfr_cnt[0])
|
mi2rx_rcv_vld <= rcv_valid_in;
|
mi2rx_rcv_vld <= rcv_valid_in;
|
else
|
else
|
mi2rx_rcv_vld <= 1'b0;
|
mi2rx_rcv_vld <= 1'b0;
|
end
|
end
|
// All the data, enable and ack signals out of RX block are
|
// All the data, enable and ack signals out of RX block are
|
// registered
|
// registered
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
begin
|
begin
|
mi2rx_strt_rcv <= 1'b0;
|
mi2rx_strt_rcv <= 1'b0;
|
mi2rx_end_rcv <= 1'b0;
|
mi2rx_end_rcv <= 1'b0;
|
//mi2rx_rcv_vld <= 1'b0;
|
//mi2rx_rcv_vld <= 1'b0;
|
mi2rx_frame_err <= 1'b0;
|
mi2rx_frame_err <= 1'b0;
|
mi2rx_extend <= 1'b0;
|
mi2rx_extend <= 1'b0;
|
mi2rx_extend_err <= 1'b0;
|
mi2rx_extend_err <= 1'b0;
|
mi2rx_end_frame <= 1'b0;
|
mi2rx_end_frame <= 1'b0;
|
rx_dv <= 1'b0;
|
rx_dv <= 1'b0;
|
rx_er <= 1'b0;
|
rx_er <= 1'b0;
|
rx_dv_del <= 1'b0;
|
rx_dv_del <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
mi2rx_strt_rcv <= strt_rcv_in;
|
mi2rx_strt_rcv <= strt_rcv_in;
|
mi2rx_end_rcv <= end_rcv_in;
|
mi2rx_end_rcv <= end_rcv_in;
|
//mi2rx_rcv_vld <= rcv_valid_in;
|
//mi2rx_rcv_vld <= rcv_valid_in;
|
mi2rx_frame_err <= rcv_err_in;
|
mi2rx_frame_err <= rcv_err_in;
|
mi2rx_extend <= mi2rx_extend_in;
|
mi2rx_extend <= mi2rx_extend_in;
|
mi2rx_extend_err <= mi2rx_extend_err_in;
|
mi2rx_extend_err <= mi2rx_extend_err_in;
|
mi2rx_end_frame <= mi2rx_end_frame_in;
|
mi2rx_end_frame <= mi2rx_end_frame_in;
|
rx_dv <= rx_dv_in;
|
rx_dv <= rx_dv_in;
|
rx_er <= rx_er_in;
|
rx_er <= rx_er_in;
|
rx_dv_del <= rx_dv;
|
rx_dv_del <= rx_dv;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
half_dup_dble_reg U_dble_reg1 (
|
half_dup_dble_reg U_dble_reg1 (
|
//outputs
|
//outputs
|
.sync_out_pulse(receive_detect),
|
.sync_out_pulse(receive_detect),
|
//inputs
|
//inputs
|
.in_pulse(rx_dv_in),
|
.in_pulse(rx_dv_in),
|
.dest_clk(phy_tx_clk),
|
.dest_clk(phy_tx_clk),
|
.reset_n(tx_reset_n)
|
.reset_n(tx_reset_n)
|
);
|
);
|
|
|
|
|
wire test;
|
wire test;
|
|
|
half_dup_dble_reg U_dble_reg5 (
|
half_dup_dble_reg U_dble_reg5 (
|
//outputs
|
//outputs
|
.sync_out_pulse(tx_en),
|
.sync_out_pulse(tx_en),
|
//inputs
|
//inputs
|
.in_pulse(lb_tx_en),
|
.in_pulse(lb_tx_en),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
half_dup_dble_reg U_dble_reg6 (
|
half_dup_dble_reg U_dble_reg6 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[0]),
|
.sync_out_pulse(txd[0]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[0]),
|
.in_pulse(phy_txd[0]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
half_dup_dble_reg U_dble_reg7 (
|
half_dup_dble_reg U_dble_reg7 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[1]),
|
.sync_out_pulse(txd[1]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[1]),
|
.in_pulse(phy_txd[1]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
half_dup_dble_reg U_dble_reg8 (
|
half_dup_dble_reg U_dble_reg8 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[2]),
|
.sync_out_pulse(txd[2]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[2]),
|
.in_pulse(phy_txd[2]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
half_dup_dble_reg U_dble_reg9 (
|
half_dup_dble_reg U_dble_reg9 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[3]),
|
.sync_out_pulse(txd[3]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[3]),
|
.in_pulse(phy_txd[3]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
half_dup_dble_reg U_dble_reg10 (
|
half_dup_dble_reg U_dble_reg10 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[4]),
|
.sync_out_pulse(txd[4]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[4]),
|
.in_pulse(phy_txd[4]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
|
|
half_dup_dble_reg U_dble_reg11 (
|
half_dup_dble_reg U_dble_reg11 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[5]),
|
.sync_out_pulse(txd[5]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[5]),
|
.in_pulse(phy_txd[5]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
|
|
half_dup_dble_reg U_dble_reg12 (
|
half_dup_dble_reg U_dble_reg12 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[6]),
|
.sync_out_pulse(txd[6]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[6]),
|
.in_pulse(phy_txd[6]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
|
|
half_dup_dble_reg U_dble_reg13 (
|
half_dup_dble_reg U_dble_reg13 (
|
//outputs
|
//outputs
|
.sync_out_pulse(txd[7]),
|
.sync_out_pulse(txd[7]),
|
//inputs
|
//inputs
|
.in_pulse(phy_txd[7]),
|
.in_pulse(phy_txd[7]),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
|
|
half_dup_dble_reg U_dble_reg14 (
|
half_dup_dble_reg U_dble_reg14 (
|
//outputs
|
//outputs
|
.sync_out_pulse(tx_er),
|
.sync_out_pulse(tx_er),
|
//inputs
|
//inputs
|
.in_pulse(lb_tx_er),
|
.in_pulse(lb_tx_er),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
|
|
half_dup_dble_reg U_dble_reg15 (
|
half_dup_dble_reg U_dble_reg15 (
|
//outputs
|
//outputs
|
.sync_out_pulse(mi2rx_crs),
|
.sync_out_pulse(mi2rx_crs),
|
//inputs
|
//inputs
|
.in_pulse(crs_in),
|
.in_pulse(crs_in),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(rx_reset_n)
|
.reset_n(rx_reset_n)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
|
|
