//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/***************************************************************
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/***************************************************************
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Description:
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Description:
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rx_fsm.v: This verilog file is the receive state machine for the MAC
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rx_fsm.v: This verilog file is the receive state machine for the MAC
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block. It receives nibbles from rmii block. It assembles
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block. It receives nibbles from rmii block. It assembles
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double words from bytes. Generates writes to Receive FIFO
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double words from bytes. Generates writes to Receive FIFO
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Removes padding and generates appropriate signals to the
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Removes padding and generates appropriate signals to the
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CRC and Address Filtering block. It also generates the necessary
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CRC and Address Filtering block. It also generates the necessary
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signals to generate status for every frame.
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signals to generate status for every frame.
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***************************************************************/
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***************************************************************/
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/************** MODULE DECLARATION ****************************/
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/************** MODULE DECLARATION ****************************/
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//`timescale 1ns/100ps
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//`timescale 1ns/100ps
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module g_rx_fsm(
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module g_rx_fsm(
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// Status information to Applications
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// Status information to Applications
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rx_sts_vld,
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rx_sts_vld,
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rx_sts_bytes_rcvd,
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rx_sts_bytes_rcvd,
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rx_sts_large_pkt,
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rx_sts_large_pkt,
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rx_sts_lengthfield_err,
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rx_sts_lengthfield_err,
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rx_sts_crc_err,
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rx_sts_crc_err,
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rx_sts_runt_pkt_rcvd,
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rx_sts_runt_pkt_rcvd,
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rx_sts_rx_overrun,
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rx_sts_rx_overrun,
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rx_sts_frm_length_err,
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rx_sts_frm_length_err,
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rx_sts_len_mismatch,
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rx_sts_len_mismatch,
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// Data Signals to Fifo Management Block
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// Data Signals to Fifo Management Block
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clr_rx_error_from_rx_fsm,
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clr_rx_error_from_rx_fsm,
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rx2ap_rx_fsm_wrt,
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rx2ap_rx_fsm_wrt,
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rx2ap_rx_fsm_dt,
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rx2ap_rx_fsm_dt,
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// Fifo Control Signal to Fifo Management Block
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// Fifo Control Signal to Fifo Management Block
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rx2ap_commit_write,
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rx2ap_commit_write,
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rx2ap_rewind_write,
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rx2ap_rewind_write,
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// To address filtering block
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// To address filtering block
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//commit
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//commit
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commit_write_done,
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commit_write_done,
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// Global Signals
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// Global Signals
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reset_n,
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reset_n,
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phy_rx_clk,
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phy_rx_clk,
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// Signals from Mii/Rmii block for Receive data
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// Signals from Mii/Rmii block for Receive data
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mi2rx_strt_rcv,
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mi2rx_strt_rcv,
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mi2rx_rcv_vld,
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mi2rx_rcv_vld,
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mi2rx_rx_byte,
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mi2rx_rx_byte,
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mi2rx_end_rcv,
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mi2rx_end_rcv,
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mi2rx_extend,
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mi2rx_extend,
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mi2rx_frame_err,
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mi2rx_frame_err,
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mi2rx_end_frame,
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mi2rx_end_frame,
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// Rx fifo management signal to indicate overrun
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// Rx fifo management signal to indicate overrun
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rx_fifo_full,
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rx_fifo_full,
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ap2rx_rx_fifo_err,
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ap2rx_rx_fifo_err,
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// Signal from CRC check block
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// Signal from CRC check block
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rc2rx_crc_ok,
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rc2rx_crc_ok,
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// Signals from Config Management Block
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// Signals from Config Management Block
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cf2rx_max_pkt_sz,
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cf2rx_max_pkt_sz,
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cf2rx_rx_ch_en,
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cf2rx_rx_ch_en,
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cf2rx_strp_pad_en,
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cf2rx_strp_pad_en,
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cf2rx_snd_crc,
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cf2rx_snd_crc,
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cf2rx_rcv_runt_pkt_en,
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cf2rx_rcv_runt_pkt_en,
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cf2rx_gigabit_xfr,
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cf2rx_gigabit_xfr,
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//A200 change Port added for crs based flow control
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//A200 change Port added for crs based flow control
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phy_crs
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phy_crs
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);
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);
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parameter MIN_FRM_SIZE = 6'h2e ;
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parameter MIN_FRM_SIZE = 6'h2e ;
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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/******* INPUT & OUTPUT DECLARATIONS *************************/
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output rx_sts_vld; // Receive status is available for the application
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output rx_sts_vld; // Receive status is available for the application
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output [15:0] rx_sts_bytes_rcvd;
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output [15:0] rx_sts_bytes_rcvd;
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output rx_sts_large_pkt;
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output rx_sts_large_pkt;
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output rx_sts_lengthfield_err;
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output rx_sts_lengthfield_err;
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output rx_sts_crc_err;
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output rx_sts_crc_err;
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output rx_sts_runt_pkt_rcvd;
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output rx_sts_runt_pkt_rcvd;
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output rx_sts_rx_overrun;
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output rx_sts_rx_overrun;
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output rx_sts_frm_length_err;
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output rx_sts_frm_length_err;
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output rx_sts_len_mismatch;
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output rx_sts_len_mismatch;
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output rx2ap_rx_fsm_wrt; // Receive Fifo Write
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output rx2ap_rx_fsm_wrt; // Receive Fifo Write
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output [8:0] rx2ap_rx_fsm_dt; // This is 32 bit assembled receive data
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output [8:0] rx2ap_rx_fsm_dt; // This is 32 bit assembled receive data
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// with EOP and valid bytes information in it.
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// with EOP and valid bytes information in it.
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output rx2ap_commit_write; // This is to RX fifo MGMT to indicate
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output rx2ap_commit_write; // This is to RX fifo MGMT to indicate
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// that the current packet
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// that the current packet
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// has to be sent to application
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// has to be sent to application
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output rx2ap_rewind_write; // This indicates the previous packet
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output rx2ap_rewind_write; // This indicates the previous packet
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// in the FIFO has a error
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// in the FIFO has a error
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// Ignore the packet and restart from the
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// Ignore the packet and restart from the
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// end of previous packet
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// end of previous packet
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output clr_rx_error_from_rx_fsm;
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output clr_rx_error_from_rx_fsm;
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output commit_write_done;
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output commit_write_done;
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input reset_n; // reset from mac application interface
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input reset_n; // reset from mac application interface
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input phy_rx_clk; // Reference clock used for RX
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input phy_rx_clk; // Reference clock used for RX
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input mi2rx_strt_rcv; // Receive data from the PHY
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input mi2rx_strt_rcv; // Receive data from the PHY
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input mi2rx_rcv_vld; // Received nibble is valid
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input mi2rx_rcv_vld; // Received nibble is valid
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input [7:0] mi2rx_rx_byte; // Rx nibble from the RMII/MII block
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input [7:0] mi2rx_rx_byte; // Rx nibble from the RMII/MII block
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input mi2rx_end_rcv; // This is provided by the RMII/MII
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input mi2rx_end_rcv; // This is provided by the RMII/MII
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// block to indicate
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// block to indicate
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// end of receieve
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// end of receieve
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input mi2rx_frame_err;
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input mi2rx_frame_err;
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input mi2rx_end_frame;
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input mi2rx_end_frame;
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input rx_fifo_full;
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input rx_fifo_full;
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input ap2rx_rx_fifo_err; // Receive error generated by the
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input ap2rx_rx_fifo_err; // Receive error generated by the
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// RX FIFO MGMT block
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// RX FIFO MGMT block
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input rc2rx_crc_ok; // CRC of the receiving packet is OK.
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input rc2rx_crc_ok; // CRC of the receiving packet is OK.
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// Generated by CRC block
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// Generated by CRC block
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input [15:0] cf2rx_max_pkt_sz; // max packet size
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input [15:0] cf2rx_max_pkt_sz; // max packet size
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input cf2rx_rx_ch_en; // Receive Enabled
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input cf2rx_rx_ch_en; // Receive Enabled
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input cf2rx_strp_pad_en; // Do not Append padding after the data
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input cf2rx_strp_pad_en; // Do not Append padding after the data
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input cf2rx_snd_crc; // Append CRC to the data
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input cf2rx_snd_crc; // Append CRC to the data
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// ( This automatically means padding
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// ( This automatically means padding
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// will be enabled)
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// will be enabled)
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input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
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input cf2rx_rcv_runt_pkt_en; // Receive needs to receive
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input cf2rx_gigabit_xfr;
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input cf2rx_gigabit_xfr;
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input mi2rx_extend;
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input mi2rx_extend;
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//A200 change Port added for crs based flow control
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//A200 change Port added for crs based flow control
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input phy_crs;
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input phy_crs;
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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/******* WIRE & REG DECLARATION FOR INPUT AND OUTPUTS ********/
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reg rx2ap_commit_write;
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reg rx2ap_commit_write;
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reg rx2ap_rewind_write;
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reg rx2ap_rewind_write;
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reg [8:0] rx2ap_rx_fsm_dt;
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reg [8:0] rx2ap_rx_fsm_dt;
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reg rx2ap_rx_fsm_wrt;
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reg rx2ap_rx_fsm_wrt;
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wire [31:0] rx_sts_dt;
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wire [31:0] rx_sts_dt;
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reg [31:0] rx_sts;
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reg [31:0] rx_sts;
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
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reg commit_write;
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reg commit_write;
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reg rewind_write;
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reg rewind_write;
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wire look_at_length_field;
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wire look_at_length_field;
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reg send_crc;
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reg send_crc;
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reg rcv_pad_data;
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reg rcv_pad_data;
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reg first_dword;
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reg first_dword;
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wire [15:0] inc_rcv_byte_count;
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wire [15:0] inc_rcv_byte_count;
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reg [15:0] rcv_byte_count;
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reg [15:0] rcv_byte_count;
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reg reset_tmp_count;
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reg reset_tmp_count;
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reg ld_length_byte_1,ld_length_byte_2;
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reg ld_length_byte_1,ld_length_byte_2;
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reg set_crc_error;
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reg set_crc_error;
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reg set_byte_allgn_error;
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reg set_byte_allgn_error;
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reg rx_sts_vld,e_rx_sts_vld;
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reg rx_sts_vld,e_rx_sts_vld;
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reg padding_needed;
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reg padding_needed;
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reg dec_data_len;
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reg dec_data_len;
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reg dec_pad_len;
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reg dec_pad_len;
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reg gen_eop;
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reg gen_eop;
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reg set_frm_lngth_error;
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reg set_frm_lngth_error;
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reg set_incomplete_frm;
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reg set_incomplete_frm;
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reg byte_boundary;
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reg byte_boundary;
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reg error;
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reg error;
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reg error_seen;
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reg error_seen;
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reg commit_write_done;
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reg commit_write_done;
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reg check_padding;
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reg check_padding;
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reg check_padding_in;
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reg check_padding_in;
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reg [2:0] padding_len_reg;
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reg [2:0] padding_len_reg;
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reg [15:0] rcv_length_reg;
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reg [15:0] rcv_length_reg;
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reg [15:0] length_counter;
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reg [15:0] length_counter;
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reg [18:0] rx_fsm_cur_st;
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reg [18:0] rx_fsm_cur_st;
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reg [18:0] rx_fsm_nxt_st;
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reg [18:0] rx_fsm_nxt_st;
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reg crc_stat_reg;
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reg crc_stat_reg;
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reg rx_runt_pkt_reg;
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reg rx_runt_pkt_reg;
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reg large_pkt_reg;
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reg large_pkt_reg;
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reg rx_fifo_overrun_reg;
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reg rx_fifo_overrun_reg;
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reg frm_length_err_reg;
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reg frm_length_err_reg;
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reg [2:0] crc_count;
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reg [2:0] crc_count;
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reg inc_shift_counter;
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reg inc_shift_counter;
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reg send_data_to_fifo;
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reg send_data_to_fifo;
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wire send_runt_packet;
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wire send_runt_packet;
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reg [2:0] shift_counter;
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reg [2:0] shift_counter;
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reg [2:0] bytes_to_fifo;
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reg [2:0] bytes_to_fifo;
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reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
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reg [7:0] buf_latch4,buf_latch3,buf_latch2,buf_latch1,buf_latch0;
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wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
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wire ld_buf,ld_buf1,ld_buf2,ld_buf3,ld_buf4;
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reg lengthfield_error;
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reg lengthfield_error;
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reg lengthfield_err_reg;
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reg lengthfield_err_reg;
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reg addr_stat_chk;
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reg addr_stat_chk;
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reg clr_rx_error_from_rx_fsm;
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reg clr_rx_error_from_rx_fsm;
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wire [15:0] adj_rcv_length_reg;
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wire [15:0] adj_rcv_length_reg;
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wire [15:0] adj_rcv_byte_count;
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wire [15:0] adj_rcv_byte_count;
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wire [15:0] adj_cf2rx_max_pkt_sz;
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wire [15:0] adj_cf2rx_max_pkt_sz;
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reg set_tag1_flag, set_tag2_flag;
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reg set_tag1_flag, set_tag2_flag;
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|
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parameter rx_fsm_idle_st= 19'b0000000000000000000,
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parameter rx_fsm_idle_st= 19'b0000000000000000000,
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rx_fsm_chkdestad_nib1_st = 19'b0000000000000000001,
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rx_fsm_chkdestad_nib1_st = 19'b0000000000000000001,
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rx_fsm_lk4srcad_nib1_st = 19'b0000000000000000010,
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rx_fsm_lk4srcad_nib1_st = 19'b0000000000000000010,
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rx_fsm_lk4len_byte1_st = 19'b0000000000000000100,
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rx_fsm_lk4len_byte1_st = 19'b0000000000000000100,
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rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
|
rx_fsm_lk4len_byte2_st = 19'b0000000000000001000,
|
rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
|
rx_fsm_getdt_nib1_st = 19'b0000000000000010000,
|
rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
|
rx_fsm_getpaddt_nib1_st = 19'b0000000000000100000,
|
rx_fsm_updstat_st = 19'b0000000000001000000,
|
rx_fsm_updstat_st = 19'b0000000000001000000,
|
rx_fsm_chkval_st = 19'b0000000000010000000,
|
rx_fsm_chkval_st = 19'b0000000000010000000,
|
rx_fsm_extend_st = 19'b0000000100000000000;
|
rx_fsm_extend_st = 19'b0000000100000000000;
|
|
|
/***************** WIRE ASSIGNMENTS *************************/
|
/***************** WIRE ASSIGNMENTS *************************/
|
wire [6:0] dec_pad_length;
|
wire [6:0] dec_pad_length;
|
wire [15:0] inc_length_counter;
|
wire [15:0] inc_length_counter;
|
wire rx_overrun_error;
|
wire rx_overrun_error;
|
wire commit_condition;
|
wire commit_condition;
|
|
|
//COMMIT_WRITE CONDITION
|
//COMMIT_WRITE CONDITION
|
assign commit_condition = ((inc_rcv_byte_count[14:0] == 15'd65)&& !commit_write_done );
|
assign commit_condition = ((inc_rcv_byte_count[14:0] == 15'd65)&& !commit_write_done );
|
|
|
|
|
|
|
/******** SEQUENTIAL LOGIC **********************************/
|
/******** SEQUENTIAL LOGIC **********************************/
|
half_dup_dble_reg U_dble_reg1 (
|
half_dup_dble_reg U_dble_reg1 (
|
//outputs
|
//outputs
|
.sync_out_pulse(rx_ch_en),
|
.sync_out_pulse(rx_ch_en),
|
//inputs
|
//inputs
|
.in_pulse(cf2rx_rx_ch_en),
|
.in_pulse(cf2rx_rx_ch_en),
|
.dest_clk(phy_rx_clk),
|
.dest_clk(phy_rx_clk),
|
.reset_n(reset_n)
|
.reset_n(reset_n)
|
);
|
);
|
|
|
// ap2rx_rx_fifo_err signal is generated in rx_clk domain
|
// ap2rx_rx_fifo_err signal is generated in rx_clk domain
|
assign rx_overrun_error = ap2rx_rx_fifo_err;
|
assign rx_overrun_error = ap2rx_rx_fifo_err;
|
|
|
reg rx_sts_vld_delayed;
|
reg rx_sts_vld_delayed;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rx_sts <= 32'b0;
|
rx_sts <= 32'b0;
|
rx_sts_vld <= 1'b0;
|
rx_sts_vld <= 1'b0;
|
rx_sts_vld_delayed <= 1'b0;
|
rx_sts_vld_delayed <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_sts_vld <= rx_sts_vld_delayed;
|
rx_sts_vld <= rx_sts_vld_delayed;
|
rx_sts_vld_delayed <= e_rx_sts_vld;
|
rx_sts_vld_delayed <= e_rx_sts_vld;
|
if (e_rx_sts_vld)
|
if (e_rx_sts_vld)
|
rx_sts <= rx_sts_dt;
|
rx_sts <= rx_sts_dt;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rx_fsm_cur_st <= rx_fsm_idle_st;
|
rx_fsm_cur_st <= rx_fsm_idle_st;
|
check_padding <= 1'b0;
|
check_padding <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_cur_st <= rx_fsm_nxt_st;
|
rx_fsm_cur_st <= rx_fsm_nxt_st;
|
check_padding <= check_padding_in;
|
check_padding <= check_padding_in;
|
end
|
end
|
end
|
end
|
reg first_byte_seen;
|
reg first_byte_seen;
|
|
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
if(!reset_n)
|
if(!reset_n)
|
first_byte_seen <= 1'b0;
|
first_byte_seen <= 1'b0;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
first_byte_seen <= 1'b1;
|
first_byte_seen <= 1'b1;
|
else if(mi2rx_rcv_vld)
|
else if(mi2rx_rcv_vld)
|
first_byte_seen <= 1'b0;
|
first_byte_seen <= 1'b0;
|
|
|
|
|
|
|
// adjust rcv_length reg for packet sizes < 64 bytes
|
// adjust rcv_length reg for packet sizes < 64 bytes
|
assign adj_rcv_length_reg = (rcv_length_reg < 8'h2E) ? 8'h2E : rcv_length_reg;
|
assign adj_rcv_length_reg = (rcv_length_reg < 8'h2E) ? 8'h2E : rcv_length_reg;
|
|
|
// subtr 18 bytes (sa + da + fcs + t/l)
|
// subtr 18 bytes (sa + da + fcs + t/l)
|
assign adj_rcv_byte_count = rcv_byte_count - 8'd18;
|
assign adj_rcv_byte_count = rcv_byte_count - 8'd18;
|
|
|
// configured max packet size should be 16'd1518.
|
// configured max packet size should be 16'd1518.
|
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
|
assign adj_cf2rx_max_pkt_sz = cf2rx_max_pkt_sz;
|
|
|
|
|
|
|
// Following state machine is to receive nibbles from the RMII/MII
|
// Following state machine is to receive nibbles from the RMII/MII
|
// block and packetize them to 32 bits with information of EOP and
|
// block and packetize them to 32 bits with information of EOP and
|
// valid bytes. It also discards packets which are less than minimum
|
// valid bytes. It also discards packets which are less than minimum
|
// frame size. It performs Address validity and Data validity.
|
// frame size. It performs Address validity and Data validity.
|
always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
|
always @(rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en
|
or cf2rx_snd_crc or look_at_length_field
|
or cf2rx_snd_crc or look_at_length_field
|
or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
|
or mi2rx_rcv_vld or first_dword or rc2rx_crc_ok
|
or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
|
or mi2rx_end_rcv or mi2rx_rx_byte or mi2rx_extend
|
or inc_length_counter or rcv_length_reg or commit_write_done
|
or inc_length_counter or rcv_length_reg or commit_write_done
|
or crc_count or shift_counter or bytes_to_fifo
|
or crc_count or shift_counter or bytes_to_fifo
|
or cf2rx_rcv_runt_pkt_en
|
or cf2rx_rcv_runt_pkt_en
|
or inc_rcv_byte_count or send_runt_packet
|
or inc_rcv_byte_count or send_runt_packet
|
or rcv_byte_count or first_dword
|
or rcv_byte_count or first_dword
|
or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
|
or commit_condition or rx_fifo_full or ap2rx_rx_fifo_err )
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_cur_st;
|
rx_fsm_nxt_st = rx_fsm_cur_st;
|
set_tag1_flag = 1'b0;
|
set_tag1_flag = 1'b0;
|
set_tag2_flag = 1'b0;
|
set_tag2_flag = 1'b0;
|
reset_tmp_count = 1'b0;
|
reset_tmp_count = 1'b0;
|
ld_length_byte_1 = 1'b0;
|
ld_length_byte_1 = 1'b0;
|
ld_length_byte_2 = 1'b0;
|
ld_length_byte_2 = 1'b0;
|
dec_data_len = 1'b0;
|
dec_data_len = 1'b0;
|
dec_pad_len = 1'b0;
|
dec_pad_len = 1'b0;
|
commit_write = 1'b0;
|
commit_write = 1'b0;
|
rewind_write = 1'b0;
|
rewind_write = 1'b0;
|
e_rx_sts_vld = 1'b0;
|
e_rx_sts_vld = 1'b0;
|
set_crc_error = 1'b0;
|
set_crc_error = 1'b0;
|
check_padding_in = 1'b0;
|
check_padding_in = 1'b0;
|
set_byte_allgn_error = 1'b0;
|
set_byte_allgn_error = 1'b0;
|
set_incomplete_frm = 1'b0;
|
set_incomplete_frm = 1'b0;
|
set_frm_lngth_error = 1'b0;
|
set_frm_lngth_error = 1'b0;
|
gen_eop = 1'b0;
|
gen_eop = 1'b0;
|
error = 1'b0;
|
error = 1'b0;
|
byte_boundary= 1'b0;
|
byte_boundary= 1'b0;
|
send_crc = 1'b0;
|
send_crc = 1'b0;
|
rcv_pad_data = 1'b0;
|
rcv_pad_data = 1'b0;
|
inc_shift_counter = 1'b0;
|
inc_shift_counter = 1'b0;
|
send_data_to_fifo = 1'b0;
|
send_data_to_fifo = 1'b0;
|
lengthfield_error = 1'b0;
|
lengthfield_error = 1'b0;
|
addr_stat_chk = 1'b0;
|
addr_stat_chk = 1'b0;
|
clr_rx_error_from_rx_fsm = 1'b0;
|
clr_rx_error_from_rx_fsm = 1'b0;
|
|
|
|
|
casex(rx_fsm_cur_st) // synopsys parallel_case full_case
|
case(rx_fsm_cur_st)
|
rx_fsm_idle_st:
|
rx_fsm_idle_st:
|
// Waiting for packet from mii block
|
// Waiting for packet from mii block
|
// Continues accepting data only if
|
// Continues accepting data only if
|
// receive has been enabled
|
// receive has been enabled
|
begin
|
begin
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
clr_rx_error_from_rx_fsm = 1'b1;
|
clr_rx_error_from_rx_fsm = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
else if (rx_fifo_full)
|
else if (rx_fifo_full)
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
else if(mi2rx_strt_rcv && rx_ch_en )
|
else if(mi2rx_strt_rcv && rx_ch_en )
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
|
|
rx_fsm_chkdestad_nib1_st:
|
rx_fsm_chkdestad_nib1_st:
|
begin
|
begin
|
// collecting the nibbles of destination
|
// collecting the nibbles of destination
|
// address
|
// address
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
if(cf2rx_rcv_runt_pkt_en)
|
if(cf2rx_rcv_runt_pkt_en)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
if (rcv_byte_count[2:0] > 5)
|
if (rcv_byte_count[2:0] > 5)
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
end
|
end
|
end // if (mi2rx_end_rcv)
|
end // if (mi2rx_end_rcv)
|
|
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd6)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_chkdestad_nib1_st;
|
end
|
end
|
end
|
end
|
|
|
rx_fsm_lk4srcad_nib1_st:
|
rx_fsm_lk4srcad_nib1_st:
|
// collecting nibbles of source address
|
// collecting nibbles of source address
|
// in case of termination of packet
|
// in case of termination of packet
|
// or carrier sense error then generate eop
|
// or carrier sense error then generate eop
|
// and generate status
|
// and generate status
|
begin
|
begin
|
if(ap2rx_rx_fifo_err )
|
if(ap2rx_rx_fifo_err )
|
begin
|
begin
|
rewind_write = 1;
|
rewind_write = 1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end // else: !if(mi2rx_end_rcv)
|
end // else: !if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
if(cf2rx_rcv_runt_pkt_en)
|
if(cf2rx_rcv_runt_pkt_en)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
end
|
end
|
end
|
end
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
|
else if(mi2rx_rcv_vld && inc_rcv_byte_count[14:0] == 15'd12)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4srcad_nib1_st;
|
end
|
end
|
end
|
end
|
|
|
rx_fsm_lk4len_byte1_st:
|
rx_fsm_lk4len_byte1_st:
|
// this state collects the odd nibbles of the length
|
// this state collects the odd nibbles of the length
|
// field.
|
// field.
|
begin
|
begin
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
rewind_write = 1;
|
rewind_write = 1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end // else: !if(mi2rx_end_rcv)
|
end // else: !if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
if(cf2rx_rcv_runt_pkt_en)
|
if(cf2rx_rcv_runt_pkt_en)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
end
|
end
|
end
|
end
|
else if(mi2rx_rcv_vld)
|
else if(mi2rx_rcv_vld)
|
begin
|
begin
|
ld_length_byte_1 = 1'b1;
|
ld_length_byte_1 = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte1_st;
|
end
|
end
|
|
|
rx_fsm_lk4len_byte2_st:
|
rx_fsm_lk4len_byte2_st:
|
// This state generates the even nibbles of the length
|
// This state generates the even nibbles of the length
|
// field
|
// field
|
begin
|
begin
|
if(ap2rx_rx_fifo_err )
|
if(ap2rx_rx_fifo_err )
|
begin
|
begin
|
rewind_write = 1;
|
rewind_write = 1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end // else: !if(mi2rx_end_rcv)
|
end // else: !if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
if(cf2rx_rcv_runt_pkt_en)
|
if(cf2rx_rcv_runt_pkt_en)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
end
|
end
|
end
|
end
|
else if(mi2rx_rcv_vld )
|
else if(mi2rx_rcv_vld )
|
begin
|
begin
|
ld_length_byte_2 = 1'b1;
|
ld_length_byte_2 = 1'b1;
|
check_padding_in = 1'b1;
|
check_padding_in = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
|
rx_fsm_nxt_st = rx_fsm_lk4len_byte2_st;
|
end // rx_fsm_lk4len_byte2_st
|
end // rx_fsm_lk4len_byte2_st
|
|
|
rx_fsm_getdt_nib1_st: //state number 7
|
rx_fsm_getdt_nib1_st: //state number 7
|
// This state collects the nibbles of the receive data
|
// This state collects the nibbles of the receive data
|
// This state makes a determination to remove padding
|
// This state makes a determination to remove padding
|
// only if strip padding is enabled and the length field
|
// only if strip padding is enabled and the length field
|
// detected is less than 64
|
// detected is less than 64
|
begin
|
begin
|
if (commit_condition)
|
if (commit_condition)
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
|
|
if((ap2rx_rx_fifo_err) && !commit_write_done)
|
if((ap2rx_rx_fifo_err) && !commit_write_done)
|
begin
|
begin
|
rewind_write = 1;
|
rewind_write = 1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end // else: !if(mi2rx_end_rcv)
|
end // else: !if(mi2rx_end_rcv)
|
else if (ap2rx_rx_fifo_err)
|
else if (ap2rx_rx_fifo_err)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
if(cf2rx_rcv_runt_pkt_en && !(commit_write_done | commit_condition))
|
if(cf2rx_rcv_runt_pkt_en && !(commit_write_done | commit_condition))
|
begin
|
begin
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
end
|
end
|
else if(!(commit_write_done | commit_condition) && !cf2rx_rcv_runt_pkt_en)
|
else if(!(commit_write_done | commit_condition) && !cf2rx_rcv_runt_pkt_en)
|
begin
|
begin
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
end
|
end
|
else if(mi2rx_rcv_vld && (inc_length_counter == rcv_length_reg) &&
|
else if(mi2rx_rcv_vld && (inc_length_counter == rcv_length_reg) &&
|
look_at_length_field)
|
look_at_length_field)
|
begin
|
begin
|
dec_data_len = 1'b1;
|
dec_data_len = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
|
end
|
end
|
else if(mi2rx_rcv_vld && look_at_length_field)
|
else if(mi2rx_rcv_vld && look_at_length_field)
|
begin
|
begin
|
dec_data_len = 1'b1;
|
dec_data_len = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_getdt_nib1_st;
|
end
|
end
|
|
|
rx_fsm_getpaddt_nib1_st:
|
rx_fsm_getpaddt_nib1_st:
|
// This state handles the padded data in case of less than 64
|
// This state handles the padded data in case of less than 64
|
// byte packets This handles the odd nibbles
|
// byte packets This handles the odd nibbles
|
begin
|
begin
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
if(rcv_byte_count[14:0] <= 15'd64) // mfilardo
|
if(rcv_byte_count[14:0] <= 15'd64) // mfilardo
|
//if(inc_rcv_byte_count[14:0] <= 15'd64)
|
//if(inc_rcv_byte_count[14:0] <= 15'd64)
|
begin
|
begin
|
rewind_write = 1'b1;
|
rewind_write = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else if(mi2rx_end_rcv)
|
else if(mi2rx_end_rcv)
|
begin
|
begin
|
//if(inc_rcv_byte_count[14:0] == 15'd64)
|
//if(inc_rcv_byte_count[14:0] == 15'd64)
|
if(rcv_byte_count[14:0] == 15'd64) // mfilardo
|
if(rcv_byte_count[14:0] == 15'd64) // mfilardo
|
lengthfield_error = 0;
|
lengthfield_error = 0;
|
else
|
else
|
lengthfield_error = 1;
|
lengthfield_error = 1;
|
|
|
rx_fsm_nxt_st = rx_fsm_extend_st;
|
rx_fsm_nxt_st = rx_fsm_extend_st;
|
end
|
end
|
else if(mi2rx_rcv_vld)
|
else if(mi2rx_rcv_vld)
|
begin
|
begin
|
if(cf2rx_strp_pad_en)
|
if(cf2rx_strp_pad_en)
|
rcv_pad_data = 1'b1;
|
rcv_pad_data = 1'b1;
|
end
|
end
|
else
|
else
|
rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
|
rx_fsm_nxt_st = rx_fsm_getpaddt_nib1_st;
|
end // case: rx_fsm_getpaddt_nib1_st
|
end // case: rx_fsm_getpaddt_nib1_st
|
|
|
|
|
rx_fsm_extend_st:
|
rx_fsm_extend_st:
|
//This state handles the first extend conditon in the
|
//This state handles the first extend conditon in the
|
//cf2rx_gigabit_xfr
|
//cf2rx_gigabit_xfr
|
//transfer
|
//transfer
|
begin
|
begin
|
if (mi2rx_extend)
|
if (mi2rx_extend)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_extend_st;
|
rx_fsm_nxt_st = rx_fsm_extend_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
commit_write = 1'b1;
|
commit_write = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
end
|
end
|
end
|
end
|
rx_fsm_chkval_st:
|
rx_fsm_chkval_st:
|
// This packet generates the validity of the packet
|
// This packet generates the validity of the packet
|
// This is reached either on clean or error type
|
// This is reached either on clean or error type
|
// completion of packet.
|
// completion of packet.
|
begin
|
begin
|
if(ap2rx_rx_fifo_err)
|
if(ap2rx_rx_fifo_err)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else if(cf2rx_rcv_runt_pkt_en && first_dword)
|
else if(cf2rx_rcv_runt_pkt_en && first_dword)
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
case(rcv_byte_count[2:0])
|
case(rcv_byte_count[2:0])
|
3'd1:
|
3'd1:
|
begin
|
begin
|
if(shift_counter == 3'd4)
|
if(shift_counter == 3'd4)
|
begin
|
begin
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
else
|
else
|
send_data_to_fifo = 1'b1;
|
send_data_to_fifo = 1'b1;
|
end // if (shift_counter == 3'd4)
|
end // if (shift_counter == 3'd4)
|
else
|
else
|
inc_shift_counter = 1;
|
inc_shift_counter = 1;
|
end // case: 3'd1
|
end // case: 3'd1
|
|
|
3'd2:
|
3'd2:
|
begin
|
begin
|
if(shift_counter == 3'd3)
|
if(shift_counter == 3'd3)
|
begin
|
begin
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
else
|
else
|
send_data_to_fifo = 1'b1;
|
send_data_to_fifo = 1'b1;
|
end // if (shift_counter == 3'd3)
|
end // if (shift_counter == 3'd3)
|
else
|
else
|
inc_shift_counter = 1;
|
inc_shift_counter = 1;
|
end // case: 3'd2
|
end // case: 3'd2
|
|
|
3'd3:
|
3'd3:
|
begin
|
begin
|
if(shift_counter == 3'd2)
|
if(shift_counter == 3'd2)
|
begin
|
begin
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else
|
else
|
send_data_to_fifo = 1'b1;
|
send_data_to_fifo = 1'b1;
|
end // if (shift_counter == 3'd2)
|
end // if (shift_counter == 3'd2)
|
else
|
else
|
inc_shift_counter = 1;
|
inc_shift_counter = 1;
|
end // case: 3'd3
|
end // case: 3'd3
|
|
|
3'd4:
|
3'd4:
|
begin
|
begin
|
if(shift_counter == 3'd1)
|
if(shift_counter == 3'd1)
|
begin
|
begin
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
if(bytes_to_fifo == rcv_byte_count[2:0])
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
end // if (bytes_to_fifo == rcv_nibble_count[3:1])
|
else
|
else
|
send_data_to_fifo = 1'b1;
|
send_data_to_fifo = 1'b1;
|
end
|
end
|
else
|
else
|
inc_shift_counter = 1;
|
inc_shift_counter = 1;
|
end // case: 3'd4
|
end // case: 3'd4
|
default:
|
default:
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
gen_eop = 1'b0;
|
gen_eop = 1'b0;
|
end
|
end
|
endcase // case(rcv_nibble_count[3
|
endcase // case(rcv_nibble_count[3
|
end // if (cf2rx_rcv_runt_pkt_en && first_dword)
|
end // if (cf2rx_rcv_runt_pkt_en && first_dword)
|
else if(((cf2rx_snd_crc || send_runt_packet || look_at_length_field)
|
else if(((cf2rx_snd_crc || send_runt_packet || look_at_length_field)
|
&& crc_count == 3'd4))
|
&& crc_count == 3'd4))
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else if(send_runt_packet || look_at_length_field)
|
else if(send_runt_packet || look_at_length_field)
|
begin
|
begin
|
send_crc = 1'b1;
|
send_crc = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
end
|
end
|
else if(!cf2rx_snd_crc)
|
else if(!cf2rx_snd_crc)
|
begin
|
begin
|
gen_eop = 1'b1;
|
gen_eop = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
rx_fsm_nxt_st = rx_fsm_updstat_st;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
send_crc = 1'b1;
|
send_crc = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
rx_fsm_nxt_st = rx_fsm_chkval_st;
|
end
|
end
|
end // case: rx_fsm_chkval_st
|
end // case: rx_fsm_chkval_st
|
|
|
rx_fsm_updstat_st:
|
rx_fsm_updstat_st:
|
// This state updates the status to the application
|
// This state updates the status to the application
|
// This allows the application to determine the validity
|
// This allows the application to determine the validity
|
// of the packet so that it can take the necessary action
|
// of the packet so that it can take the necessary action
|
begin
|
begin
|
e_rx_sts_vld = 1'b1;
|
e_rx_sts_vld = 1'b1;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
|
|
default:
|
default:
|
begin
|
begin
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
rx_fsm_nxt_st = rx_fsm_idle_st;
|
end
|
end
|
endcase // casex(rx_fsm_cur_st)
|
endcase // casex(rx_fsm_cur_st)
|
end // always @ (rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en...
|
end // always @ (rx_fsm_cur_st or mi2rx_strt_rcv or rx_ch_en or cf2rx_strp_pad_en...
|
|
|
always @(inc_rcv_byte_count)
|
always @(inc_rcv_byte_count)
|
begin
|
begin
|
if(inc_rcv_byte_count[14:0] < 15'd6)
|
if(inc_rcv_byte_count[14:0] < 15'd6)
|
first_dword = 1'b1;
|
first_dword = 1'b1;
|
else
|
else
|
first_dword = 1'b0;
|
first_dword = 1'b0;
|
end // always @ (inc_rcv_nibble_count or...
|
end // always @ (inc_rcv_nibble_count or...
|
|
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
crc_count <= 3'b000;
|
crc_count <= 3'b000;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
crc_count <= 3'b000;
|
crc_count <= 3'b000;
|
else if(send_crc)
|
else if(send_crc)
|
crc_count <= crc_count + 1;
|
crc_count <= crc_count + 1;
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
// These signals are used as intermediate flags to determine
|
// These signals are used as intermediate flags to determine
|
// whether to commit pointer or not to commit pointers
|
// whether to commit pointer or not to commit pointers
|
// to the application
|
// to the application
|
// error_seen helps in tracking errors which could occurs in between
|
// error_seen helps in tracking errors which could occurs in between
|
// packet transfer
|
// packet transfer
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
commit_write_done <= 1'b1;
|
commit_write_done <= 1'b1;
|
error_seen <= 1'b0;
|
error_seen <= 1'b0;
|
end
|
end
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
begin
|
begin
|
commit_write_done <= 1'b0;
|
commit_write_done <= 1'b0;
|
error_seen <= 1'b0;
|
error_seen <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(commit_write)
|
if(commit_write)
|
commit_write_done <= 1'b1;
|
commit_write_done <= 1'b1;
|
if(error)
|
if(error)
|
error_seen <= 1'b1;
|
error_seen <= 1'b1;
|
end
|
end
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
assign look_at_length_field = cf2rx_strp_pad_en &&
|
assign look_at_length_field = cf2rx_strp_pad_en &&
|
(rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
|
(rcv_length_reg < MIN_FRM_SIZE) && (|rcv_length_reg);
|
assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
|
assign send_runt_packet = cf2rx_rcv_runt_pkt_en &&
|
(rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
|
(rcv_byte_count[15:8] == 8'd0 && rcv_byte_count[7:0] < 8'd64);
|
|
|
|
|
|
|
|
|
assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
|
assign inc_rcv_byte_count = rcv_byte_count + 16'h1;
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
rcv_byte_count <= 16'h0000;
|
rcv_byte_count <= 16'h0000;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
rcv_byte_count <= 16'h0000;
|
rcv_byte_count <= 16'h0000;
|
else if(mi2rx_rcv_vld)
|
else if(mi2rx_rcv_vld)
|
rcv_byte_count <= inc_rcv_byte_count;
|
rcv_byte_count <= inc_rcv_byte_count;
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
// This signal is asserted wheneven there is no valid transfer on the
|
// This signal is asserted wheneven there is no valid transfer on the
|
// line. Valid transfer is only between mi2rx_strt_rcv and
|
// line. Valid transfer is only between mi2rx_strt_rcv and
|
// mi2rx_end_rcv. In case
|
// mi2rx_end_rcv. In case
|
// of rewind write transfer becomes invalid. Such data should not be
|
// of rewind write transfer becomes invalid. Such data should not be
|
// written in to the fifo
|
// written in to the fifo
|
reg dt_xfr_invalid;
|
reg dt_xfr_invalid;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
dt_xfr_invalid <= 1;
|
dt_xfr_invalid <= 1;
|
else if(rewind_write || ap2rx_rx_fifo_err)
|
else if(rewind_write || ap2rx_rx_fifo_err)
|
dt_xfr_invalid <= 1;
|
dt_xfr_invalid <= 1;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
dt_xfr_invalid <= 0;
|
dt_xfr_invalid <= 0;
|
end
|
end
|
// This is the mux to gather nibbles to two octets for the length field
|
// This is the mux to gather nibbles to two octets for the length field
|
// of the register
|
// of the register
|
assign inc_length_counter = length_counter + 16'h1;
|
assign inc_length_counter = length_counter + 16'h1;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rcv_length_reg <= 16'b0;
|
rcv_length_reg <= 16'b0;
|
length_counter <= 16'b0;
|
length_counter <= 16'b0;
|
end // if (reset_n)
|
end // if (reset_n)
|
else if (rx_ch_en)
|
else if (rx_ch_en)
|
begin
|
begin
|
if(mi2rx_strt_rcv)
|
if(mi2rx_strt_rcv)
|
begin
|
begin
|
length_counter <= 16'b0;
|
length_counter <= 16'b0;
|
rcv_length_reg <= 16'b0;
|
rcv_length_reg <= 16'b0;
|
end
|
end
|
else if(dec_data_len )
|
else if(dec_data_len )
|
length_counter <= inc_length_counter;
|
length_counter <= inc_length_counter;
|
else
|
else
|
begin
|
begin
|
if(ld_length_byte_1)
|
if(ld_length_byte_1)
|
begin
|
begin
|
rcv_length_reg[15:8] <= mi2rx_rx_byte;
|
rcv_length_reg[15:8] <= mi2rx_rx_byte;
|
end
|
end
|
else if(ld_length_byte_2)
|
else if(ld_length_byte_2)
|
begin
|
begin
|
rcv_length_reg[7:0] <= mi2rx_rx_byte;
|
rcv_length_reg[7:0] <= mi2rx_rx_byte;
|
end
|
end
|
end // else: !if(dec_data_len)
|
end // else: !if(dec_data_len)
|
end // else: !if(!reset_n)
|
end // else: !if(!reset_n)
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
// This signal helps in making sure that when packets are received the
|
// This signal helps in making sure that when packets are received the
|
// channel is enabled else ignore the complete packet until next start
|
// channel is enabled else ignore the complete packet until next start
|
// of packet
|
// of packet
|
reg enable_channel;
|
reg enable_channel;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
enable_channel <= 0;
|
enable_channel <= 0;
|
else if(gen_eop)
|
else if(gen_eop)
|
enable_channel <= 0;
|
enable_channel <= 0;
|
else if(mi2rx_strt_rcv && rx_ch_en)
|
else if(mi2rx_strt_rcv && rx_ch_en)
|
enable_channel <= 1;
|
enable_channel <= 1;
|
end
|
end
|
|
|
// This is the decremented padding length register
|
// This is the decremented padding length register
|
// Once it reaches zero CRC should follow
|
// Once it reaches zero CRC should follow
|
assign dec_pad_length = padding_len_reg - 7'h1;
|
assign dec_pad_length = padding_len_reg - 7'h1;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
padding_needed <= 1'b0;
|
padding_needed <= 1'b0;
|
padding_len_reg <= 6'b0;
|
padding_len_reg <= 6'b0;
|
end
|
end
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
begin
|
begin
|
padding_needed <= 1'b0;
|
padding_needed <= 1'b0;
|
padding_len_reg <= 6'b0;
|
padding_len_reg <= 6'b0;
|
end
|
end
|
else if(look_at_length_field &&
|
else if(look_at_length_field &&
|
check_padding)
|
check_padding)
|
begin
|
begin
|
padding_len_reg <= MIN_FRM_SIZE - rcv_length_reg[5:0];
|
padding_len_reg <= MIN_FRM_SIZE - rcv_length_reg[5:0];
|
padding_needed <= 1'b1;
|
padding_needed <= 1'b1;
|
end
|
end
|
else if(dec_pad_len)
|
else if(dec_pad_len)
|
begin
|
begin
|
padding_len_reg <= dec_pad_len;
|
padding_len_reg <= dec_pad_len;
|
padding_needed <= padding_needed;
|
padding_needed <= padding_needed;
|
end
|
end
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
/*********************************************************
|
/*********************************************************
|
Status Generation for Receive packets
|
Status Generation for Receive packets
|
Statuses in this case are checked at end of receive packets
|
Statuses in this case are checked at end of receive packets
|
and are registered and provided inthe next state along with
|
and are registered and provided inthe next state along with
|
rx_sts_valid bit asserted
|
rx_sts_valid bit asserted
|
*********************************************************/
|
*********************************************************/
|
|
|
reg[14:0] fifo_byte_count;
|
reg[14:0] fifo_byte_count;
|
wire [14:0] inc_fifo_byte_count;
|
wire [14:0] inc_fifo_byte_count;
|
wire [14:0] dec_fifo_byte_count;
|
wire [14:0] dec_fifo_byte_count;
|
assign inc_fifo_byte_count = fifo_byte_count + 15'h1;
|
assign inc_fifo_byte_count = fifo_byte_count + 15'h1;
|
assign dec_fifo_byte_count = fifo_byte_count - 15'h1;
|
assign dec_fifo_byte_count = fifo_byte_count - 15'h1;
|
|
|
always @(posedge phy_rx_clk or negedge reset_n)
|
always @(posedge phy_rx_clk or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
fifo_byte_count <= 15'd0;
|
fifo_byte_count <= 15'd0;
|
else if(rewind_write || mi2rx_strt_rcv)
|
else if(rewind_write || mi2rx_strt_rcv)
|
fifo_byte_count <= 15'd0;
|
fifo_byte_count <= 15'd0;
|
else if(rx2ap_rx_fsm_wrt)
|
else if(rx2ap_rx_fsm_wrt)
|
fifo_byte_count <= inc_fifo_byte_count;
|
fifo_byte_count <= inc_fifo_byte_count;
|
end
|
end
|
|
|
reg length_sz_mismatch;
|
reg length_sz_mismatch;
|
|
|
assign rx_sts_dt[31:16] = (e_rx_sts_vld && ap2rx_rx_fifo_err) ?
|
assign rx_sts_dt[31:16] = (e_rx_sts_vld && ap2rx_rx_fifo_err) ?
|
{dec_fifo_byte_count + 16'h1} : {fifo_byte_count + 16'h1};
|
{dec_fifo_byte_count + 16'h1} : {fifo_byte_count + 16'h1};
|
assign rx_sts_dt[15:13] = 3'd0;
|
assign rx_sts_dt[15:13] = 3'd0;
|
assign rx_sts_dt[12] = length_sz_mismatch;
|
assign rx_sts_dt[12] = length_sz_mismatch;
|
assign rx_sts_dt[11] = 1'b0;
|
assign rx_sts_dt[11] = 1'b0;
|
assign rx_sts_dt[10] = large_pkt_reg;
|
assign rx_sts_dt[10] = large_pkt_reg;
|
assign rx_sts_dt[7] = lengthfield_err_reg;
|
assign rx_sts_dt[7] = lengthfield_err_reg;
|
assign rx_sts_dt[6] = crc_stat_reg;
|
assign rx_sts_dt[6] = crc_stat_reg;
|
assign rx_sts_dt[5] = rx_runt_pkt_reg;
|
assign rx_sts_dt[5] = rx_runt_pkt_reg;
|
assign rx_sts_dt[4] = rx_fifo_overrun_reg;
|
assign rx_sts_dt[4] = rx_fifo_overrun_reg;
|
assign rx_sts_dt[2] = frm_length_err_reg;
|
assign rx_sts_dt[2] = frm_length_err_reg;
|
assign rx_sts_dt[1:0] = 2'd0;
|
assign rx_sts_dt[1:0] = 2'd0;
|
|
|
wire rx_sts_large_pkt;
|
wire rx_sts_large_pkt;
|
wire [15:0] rx_sts_bytes_rcvd;
|
wire [15:0] rx_sts_bytes_rcvd;
|
wire rx_sts_lengthfield_err;
|
wire rx_sts_lengthfield_err;
|
wire rx_sts_crc_err;
|
wire rx_sts_crc_err;
|
wire rx_sts_runt_pkt_rcvd;
|
wire rx_sts_runt_pkt_rcvd;
|
wire rx_sts_rx_overrun;
|
wire rx_sts_rx_overrun;
|
wire rx_sts_frm_length_err;
|
wire rx_sts_frm_length_err;
|
wire rx_sts_len_mismatch;
|
wire rx_sts_len_mismatch;
|
|
|
assign rx_sts_bytes_rcvd = rx_sts[31:16];
|
assign rx_sts_bytes_rcvd = rx_sts[31:16];
|
assign rx_sts_len_mismatch = rx_sts[12];
|
assign rx_sts_len_mismatch = rx_sts[12];
|
assign rx_sts_large_pkt = rx_sts[10];
|
assign rx_sts_large_pkt = rx_sts[10];
|
assign rx_sts_lengthfield_err = rx_sts[7];
|
assign rx_sts_lengthfield_err = rx_sts[7];
|
assign rx_sts_crc_err = rx_sts[6];
|
assign rx_sts_crc_err = rx_sts[6];
|
assign rx_sts_runt_pkt_rcvd = rx_sts[5];
|
assign rx_sts_runt_pkt_rcvd = rx_sts[5];
|
assign rx_sts_rx_overrun = rx_sts[4];
|
assign rx_sts_rx_overrun = rx_sts[4];
|
assign rx_sts_frm_length_err = rx_sts[2];
|
assign rx_sts_frm_length_err = rx_sts[2];
|
|
|
|
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
crc_stat_reg <= 1'b0;
|
crc_stat_reg <= 1'b0;
|
frm_length_err_reg <= 1'b0;
|
frm_length_err_reg <= 1'b0;
|
lengthfield_err_reg <= 1'b0;
|
lengthfield_err_reg <= 1'b0;
|
rx_fifo_overrun_reg <= 1'b0;
|
rx_fifo_overrun_reg <= 1'b0;
|
rx_runt_pkt_reg <= 1'b0;
|
rx_runt_pkt_reg <= 1'b0;
|
large_pkt_reg <= 1'b0;
|
large_pkt_reg <= 1'b0;
|
length_sz_mismatch <= 1'b0;
|
length_sz_mismatch <= 1'b0;
|
end
|
end
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
begin
|
begin
|
crc_stat_reg <= 1'b0;
|
crc_stat_reg <= 1'b0;
|
frm_length_err_reg <= 1'b0;
|
frm_length_err_reg <= 1'b0;
|
lengthfield_err_reg <= 1'b0;
|
lengthfield_err_reg <= 1'b0;
|
rx_fifo_overrun_reg <= 1'b0;
|
rx_fifo_overrun_reg <= 1'b0;
|
rx_runt_pkt_reg <= 1'b0;
|
rx_runt_pkt_reg <= 1'b0;
|
large_pkt_reg <= 1'b0;
|
large_pkt_reg <= 1'b0;
|
length_sz_mismatch <= 1'b0;
|
length_sz_mismatch <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(rx_overrun_error)
|
if(rx_overrun_error)
|
rx_fifo_overrun_reg <= 1'b1;
|
rx_fifo_overrun_reg <= 1'b1;
|
|
|
if(lengthfield_error)
|
if(lengthfield_error)
|
lengthfield_err_reg <= 1'b1;
|
lengthfield_err_reg <= 1'b1;
|
|
|
if(mi2rx_end_rcv && mi2rx_frame_err)
|
if(mi2rx_end_rcv && mi2rx_frame_err)
|
frm_length_err_reg <= 1'b1;
|
frm_length_err_reg <= 1'b1;
|
|
|
if(mi2rx_end_rcv)
|
if(mi2rx_end_rcv)
|
begin
|
begin
|
if(!rc2rx_crc_ok)
|
if(!rc2rx_crc_ok)
|
crc_stat_reg <= 1'b1;
|
crc_stat_reg <= 1'b1;
|
if(rcv_byte_count[14:0] < 15'd64)
|
if(rcv_byte_count[14:0] < 15'd64)
|
rx_runt_pkt_reg <= 1'b1;
|
rx_runt_pkt_reg <= 1'b1;
|
if(rcv_byte_count[14:0] > adj_cf2rx_max_pkt_sz)
|
if(rcv_byte_count[14:0] > adj_cf2rx_max_pkt_sz)
|
large_pkt_reg <= 1'b1;
|
large_pkt_reg <= 1'b1;
|
if( (adj_rcv_byte_count[15:0] != adj_rcv_length_reg) && (adj_rcv_length_reg <= 16'd1500) )
|
if( (adj_rcv_byte_count[15:0] != adj_rcv_length_reg) && (adj_rcv_length_reg <= 16'd1500) )
|
length_sz_mismatch <= 1'b1;
|
length_sz_mismatch <= 1'b1;
|
end // if (mi2rx_end_rcv)
|
end // if (mi2rx_end_rcv)
|
end // else: !if(mi2rx_strt_rcv)
|
end // else: !if(mi2rx_strt_rcv)
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
/***************************************************/
|
/***************************************************/
|
//
|
//
|
// Additions for Byte operation
|
// Additions for Byte operation
|
//
|
//
|
/***************************************************/
|
/***************************************************/
|
always @(posedge phy_rx_clk or
|
always @(posedge phy_rx_clk or
|
negedge reset_n)
|
negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
shift_counter <= 3'd0;
|
shift_counter <= 3'd0;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
shift_counter <= 3'd0;
|
shift_counter <= 3'd0;
|
else if(inc_shift_counter)
|
else if(inc_shift_counter)
|
shift_counter <= shift_counter + 1;
|
shift_counter <= shift_counter + 1;
|
end // always @ (posedge phy_rx_clk or...
|
end // always @ (posedge phy_rx_clk or...
|
|
|
always @(posedge phy_rx_clk or
|
always @(posedge phy_rx_clk or
|
negedge reset_n)
|
negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
bytes_to_fifo <= 3'd0;
|
bytes_to_fifo <= 3'd0;
|
else if(mi2rx_strt_rcv)
|
else if(mi2rx_strt_rcv)
|
bytes_to_fifo <= 3'd1;
|
bytes_to_fifo <= 3'd1;
|
else if(send_data_to_fifo)
|
else if(send_data_to_fifo)
|
bytes_to_fifo <= bytes_to_fifo + 1;
|
bytes_to_fifo <= bytes_to_fifo + 1;
|
end // always @ (posedge phy_rx_clk or...
|
end // always @ (posedge phy_rx_clk or...
|
|
|
wire[8:0] e_rx_fsm_dt;
|
wire[8:0] e_rx_fsm_dt;
|
wire e_rx_fsm_wrt;
|
wire e_rx_fsm_wrt;
|
assign e_rx_fsm_dt[7:0] = buf_latch4;
|
assign e_rx_fsm_dt[7:0] = buf_latch4;
|
// assign e_rx_fsm_dt[8] = (rx_fifo_full) ? 1'b1 :gen_eop;
|
// assign e_rx_fsm_dt[8] = (rx_fifo_full) ? 1'b1 :gen_eop;
|
assign e_rx_fsm_dt[8] = gen_eop;
|
assign e_rx_fsm_dt[8] = gen_eop;
|
|
|
always @(posedge phy_rx_clk or
|
always @(posedge phy_rx_clk or
|
negedge reset_n)
|
negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
rx2ap_rx_fsm_dt <= 9'd0;
|
rx2ap_rx_fsm_dt <= 9'd0;
|
rx2ap_rx_fsm_wrt <= 1'b0;
|
rx2ap_rx_fsm_wrt <= 1'b0;
|
rx2ap_commit_write <= 1'b0;
|
rx2ap_commit_write <= 1'b0;
|
rx2ap_rewind_write <= 1'b0;
|
rx2ap_rewind_write <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx2ap_rx_fsm_wrt <= e_rx_fsm_wrt && (!ap2rx_rx_fifo_err);
|
rx2ap_rx_fsm_wrt <= e_rx_fsm_wrt && (!ap2rx_rx_fifo_err);
|
rx2ap_rx_fsm_dt <= e_rx_fsm_dt;
|
rx2ap_rx_fsm_dt <= e_rx_fsm_dt;
|
rx2ap_commit_write <= commit_write;
|
rx2ap_commit_write <= commit_write;
|
rx2ap_rewind_write <= rewind_write;
|
rx2ap_rewind_write <= rewind_write;
|
end
|
end
|
end // always @ (posedge phy_rx_clk or...
|
end // always @ (posedge phy_rx_clk or...
|
|
|
assign e_rx_fsm_wrt = ((enable_channel &&
|
assign e_rx_fsm_wrt = ((enable_channel &&
|
mi2rx_rcv_vld && !first_dword) ||
|
mi2rx_rcv_vld && !first_dword) ||
|
(enable_channel &&
|
(enable_channel &&
|
(gen_eop || send_crc)) ||
|
(gen_eop || send_crc)) ||
|
(enable_channel && send_data_to_fifo)) && !rcv_pad_data
|
(enable_channel && send_data_to_fifo)) && !rcv_pad_data
|
&& !dt_xfr_invalid && !rewind_write;
|
&& !dt_xfr_invalid && !rewind_write;
|
assign ld_buf = enable_channel && !rcv_pad_data && (|rcv_byte_count == 1) &&
|
assign ld_buf = enable_channel && !rcv_pad_data && (|rcv_byte_count == 1) &&
|
(mi2rx_rcv_vld) || send_crc || inc_shift_counter || send_data_to_fifo;
|
(mi2rx_rcv_vld) || send_crc || inc_shift_counter || send_data_to_fifo;
|
|
|
assign ld_buf4 = ld_buf ;
|
assign ld_buf4 = ld_buf ;
|
assign ld_buf3 = ld_buf ;
|
assign ld_buf3 = ld_buf ;
|
assign ld_buf2 = ld_buf ;
|
assign ld_buf2 = ld_buf ;
|
assign ld_buf1 = ld_buf ;
|
assign ld_buf1 = ld_buf ;
|
always @(posedge phy_rx_clk
|
always @(posedge phy_rx_clk
|
or negedge reset_n)
|
or negedge reset_n)
|
begin
|
begin
|
if(!reset_n)
|
if(!reset_n)
|
begin
|
begin
|
buf_latch4 <= 8'b0;
|
buf_latch4 <= 8'b0;
|
buf_latch3 <= 8'b0;
|
buf_latch3 <= 8'b0;
|
buf_latch2 <= 8'b0;
|
buf_latch2 <= 8'b0;
|
buf_latch1 <= 8'b0;
|
buf_latch1 <= 8'b0;
|
buf_latch0 <= 8'b0;
|
buf_latch0 <= 8'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(ld_buf4)
|
if(ld_buf4)
|
buf_latch4 <= buf_latch3;
|
buf_latch4 <= buf_latch3;
|
|
|
if(ld_buf3)
|
if(ld_buf3)
|
buf_latch3 <= buf_latch2;
|
buf_latch3 <= buf_latch2;
|
|
|
if(ld_buf2)
|
if(ld_buf2)
|
buf_latch2 <= buf_latch1;
|
buf_latch2 <= buf_latch1;
|
|
|
if(ld_buf1)
|
if(ld_buf1)
|
buf_latch1 <= buf_latch0;
|
buf_latch1 <= buf_latch0;
|
|
|
if (rx_ch_en)
|
if (rx_ch_en)
|
begin
|
begin
|
if(mi2rx_strt_rcv)
|
if(mi2rx_strt_rcv)
|
begin
|
begin
|
buf_latch0 <= 8'b0;
|
buf_latch0 <= 8'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(mi2rx_rcv_vld && !rcv_pad_data)
|
if(mi2rx_rcv_vld && !rcv_pad_data)
|
begin
|
begin
|
buf_latch0 <= mi2rx_rx_byte;
|
buf_latch0 <= mi2rx_rx_byte;
|
end
|
end
|
end // else: !if(mi2rx_strt_rcv)
|
end // else: !if(mi2rx_strt_rcv)
|
end // if (rx_ch_en)
|
end // if (rx_ch_en)
|
end // else: !if(!reset_n)
|
end // else: !if(!reset_n)
|
end // always @ (posedge phy_rx_clk...
|
end // always @ (posedge phy_rx_clk...
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
