//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/***************************************************************
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/***************************************************************
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Description:
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Description:
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tx_top.v: This module has the top level of the transmit block
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tx_top.v: This module has the top level of the transmit block
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It instantiates the following blocks
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It instantiates the following blocks
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1. tx_fsm
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1. tx_fsm
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2. tx_crc
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2. tx_crc
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3. tx_fifo_mgmt
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3. tx_fifo_mgmt
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4. deferral
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4. deferral
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5. backoff
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5. backoff
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***********************************************************************/
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***********************************************************************/
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module g_tx_top(
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module g_tx_top(
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app_clk,
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app_clk,
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set_fifo_undrn,
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set_fifo_undrn,
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//Outputs
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//Outputs
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//TX FIFO management
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//TX FIFO management
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tx_commit_read,
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tx_commit_read,
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tx_dt_rd,
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tx_dt_rd,
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//MII interface
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//MII interface
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tx2mi_strt_preamble,
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tx2mi_strt_preamble,
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tx2mi_byte_valid,
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tx2mi_byte_valid,
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tx2mi_byte,
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tx2mi_byte,
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tx2mi_end_transmit,
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tx2mi_end_transmit,
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tx_ch_en,
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tx_ch_en,
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//Status to application
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//Status to application
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tx_sts_vld,
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tx_sts_vld,
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tx_sts_byte_cntr,
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tx_sts_byte_cntr,
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tx_sts_fifo_underrun,
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tx_sts_fifo_underrun,
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//Inputs
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//Inputs
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//MII interface
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//MII interface
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phy_tx_en,
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phy_tx_en,
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phy_tx_er,
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phy_tx_er,
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//configuration
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//configuration
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cf2tx_ch_en,
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cf2tx_ch_en,
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cf2df_dfl_single,
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cf2df_dfl_single,
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cf2tx_pad_enable,
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cf2tx_pad_enable,
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cf2tx_append_fcs,
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cf2tx_append_fcs,
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cf_mac_mode,
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cf_mac_mode,
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cf_mac_sa,
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cf_mac_sa,
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cf2tx_force_bad_fcs,
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cf2tx_force_bad_fcs,
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//FIFO data
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//FIFO data
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app_tx_dt_in,
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app_tx_dt_in,
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app_tx_fifo_empty,
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app_tx_fifo_empty,
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app_tx_rdy,
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app_tx_rdy,
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//MII
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//MII
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mi2tx_byte_ack,
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mi2tx_byte_ack,
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app_reset_n,
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app_reset_n,
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tx_reset_n,
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tx_reset_n,
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tx_clk);
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tx_clk);
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input app_reset_n; // Global app_reset for the MAC
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input app_reset_n; // Global app_reset for the MAC
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input tx_reset_n;
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input tx_reset_n;
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input tx_clk; // Transmit clock
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input tx_clk; // Transmit clock
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input [8:0] app_tx_dt_in;
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input [8:0] app_tx_dt_in;
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input app_tx_fifo_empty;
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input app_tx_fifo_empty;
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input app_tx_rdy;
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input app_tx_rdy;
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input phy_tx_en; // Transmit data Enable
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input phy_tx_en; // Transmit data Enable
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input phy_tx_er; // Transmit Error
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input phy_tx_er; // Transmit Error
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input cf2tx_ch_en; // Transmit channel Enable
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input cf2tx_ch_en; // Transmit channel Enable
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input [7:0] cf2df_dfl_single;
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input [7:0] cf2df_dfl_single;
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input cf2tx_pad_enable; // Padding Enabled
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input cf2tx_pad_enable; // Padding Enabled
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input cf2tx_append_fcs; // Append CRC to packets
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input cf2tx_append_fcs; // Append CRC to packets
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input cf2tx_force_bad_fcs; // force bad fcs
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input cf2tx_force_bad_fcs; // force bad fcs
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input [47:0] cf_mac_sa; // MAC Source Address
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input [47:0] cf_mac_sa; // MAC Source Address
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input cf_mac_mode; // Gigabit or 10/100
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input cf_mac_mode; // Gigabit or 10/100
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input mi2tx_byte_ack; // Transmit byte ack from RMII
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input mi2tx_byte_ack; // Transmit byte ack from RMII
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output tx_commit_read;
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output tx_commit_read;
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output tx_dt_rd; //get the next fsm data
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output tx_dt_rd; //get the next fsm data
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output tx2mi_strt_preamble; // Start preamble indicated to RMII
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output tx2mi_strt_preamble; // Start preamble indicated to RMII
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output tx2mi_byte_valid; // Byte valid from the Tx State Macine
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output tx2mi_byte_valid; // Byte valid from the Tx State Macine
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output [7:0] tx2mi_byte; // Transmit byte to RMII
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output [7:0] tx2mi_byte; // Transmit byte to RMII
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output tx2mi_end_transmit; // Transmit complete
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output tx2mi_end_transmit; // Transmit complete
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output tx_sts_vld; //tx_sts is valid on valid tx_sts_vld
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output tx_sts_vld; //tx_sts is valid on valid tx_sts_vld
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output [15:0] tx_sts_byte_cntr;
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output [15:0] tx_sts_byte_cntr;
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output tx_sts_fifo_underrun;
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output tx_sts_fifo_underrun;
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output tx_ch_en;
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output tx_ch_en;
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output set_fifo_undrn;
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output set_fifo_undrn;
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input app_clk;
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input app_clk;
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wire [31:0] tc2tx_fcs;
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wire [31:0] tc2tx_fcs;
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wire set_fifo_undrn;
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wire set_fifo_undrn;
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// Instantiate Defferal block
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// Instantiate Defferal block
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g_deferral U_deferral (
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g_deferral U_deferral (
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//Outputs
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//Outputs
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.df2tx_dfl_dn(df2tx_dfl_dn),
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.df2tx_dfl_dn(df2tx_dfl_dn),
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.cf2df_dfl_single(cf2df_dfl_single),
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.cf2df_dfl_single(cf2df_dfl_single),
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.phy_tx_en(phy_tx_en),
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.phy_tx_en(phy_tx_en),
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.phy_tx_er(phy_tx_er),
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.phy_tx_er(phy_tx_er),
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.tx_clk(tx_clk),
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.tx_clk(tx_clk),
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.app_reset_n(tx_reset_n));
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.app_reset_n(tx_reset_n));
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// Instantiate Transmit State machine block
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// Instantiate Transmit State machine block
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g_tx_fsm U_tx_fsm(
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g_tx_fsm U_tx_fsm(
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.app_clk(app_clk), /
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.app_clk(app_clk),
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.set_fifo_undrn(set_fifo_undrn),
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.set_fifo_undrn(set_fifo_undrn),
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//Outputs
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//Outputs
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.tx_commit_read(tx_commit_read),
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.tx_commit_read(tx_commit_read),
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.tx_dt_rd(tx_dt_rd),
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.tx_dt_rd(tx_dt_rd),
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//FCS block interface
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//FCS block interface
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.tx2tc_fcs_active(tx2tc_fcs_active),
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.tx2tc_fcs_active(tx2tc_fcs_active),
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.tx2tc_gen_crc(tx2tc_gen_crc),
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.tx2tc_gen_crc(tx2tc_gen_crc),
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//MII or RMII interface signals
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//MII or RMII interface signals
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.tx2mi_strt_preamble(tx2mi_strt_preamble),
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.tx2mi_strt_preamble(tx2mi_strt_preamble),
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.tx2mi_byte_valid(tx2mi_byte_valid),
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.tx2mi_byte_valid(tx2mi_byte_valid),
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.tx2mi_byte(tx2mi_byte),
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.tx2mi_byte(tx2mi_byte),
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.tx2mi_end_transmit(tx2mi_end_transmit),
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.tx2mi_end_transmit(tx2mi_end_transmit),
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.tx_ch_en(tx_ch_en),
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.tx_ch_en(tx_ch_en),
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.phy_tx_en(phy_tx_en),
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.phy_tx_en(phy_tx_en),
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//tx fifo management outputs
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//tx fifo management outputs
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.tx_sts_vld(tx_sts_vld),
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.tx_sts_vld(tx_sts_vld),
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.tx_sts_byte_cntr(tx_sts_byte_cntr),
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.tx_sts_byte_cntr(tx_sts_byte_cntr),
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.tx_sts_fifo_underrun(tx_sts_fifo_underrun),
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.tx_sts_fifo_underrun(tx_sts_fifo_underrun),
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.app_tx_rdy(app_tx_rdy),
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.app_tx_rdy(app_tx_rdy),
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.tx_end_frame(app_tx_dt_in[8]),
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.tx_end_frame(app_tx_dt_in[8]),
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.app_tx_dt_in(app_tx_dt_in[7:0]),
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.app_tx_dt_in(app_tx_dt_in[7:0]),
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.app_tx_fifo_empty(app_tx_fifo_empty),
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.app_tx_fifo_empty(app_tx_fifo_empty),
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//dfl and back off
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//dfl and back off
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.df2tx_dfl_dn(df2tx_dfl_dn),
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.df2tx_dfl_dn(df2tx_dfl_dn),
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//inputs from FCS
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//inputs from FCS
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.tc2tx_fcs(tc2tx_fcs),
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.tc2tx_fcs(tc2tx_fcs),
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.cf2tx_ch_en(cf2tx_ch_en),
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.cf2tx_ch_en(cf2tx_ch_en),
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.cf2tx_pad_enable(cf2tx_pad_enable),
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.cf2tx_pad_enable(cf2tx_pad_enable),
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.cf2tx_append_fcs(cf2tx_append_fcs),
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.cf2tx_append_fcs(cf2tx_append_fcs),
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.cf_mac_mode(cf_mac_mode),
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.cf_mac_mode(cf_mac_mode),
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.cf_mac_sa(cf_mac_sa),
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.cf_mac_sa(cf_mac_sa),
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.cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
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.cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
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//MII
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//MII
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.mi2tx_byte_ack(mi2tx_byte_ack),
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.mi2tx_byte_ack(mi2tx_byte_ack),
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.tx_clk(tx_clk),
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.tx_clk(tx_clk),
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.tx_reset_n(tx_reset_n),
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.tx_reset_n(tx_reset_n),
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.app_reset_n(app_reset_n));
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.app_reset_n(app_reset_n));
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// Instantiate CRC 32 block for Transmit
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// Instantiate CRC 32 block for Transmit
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g_tx_crc32 U_tx_crc32 (
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g_tx_crc32 U_tx_crc32 (
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// List of outputs.
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// List of outputs.
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.tx_fcs (tc2tx_fcs),
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.tx_fcs (tc2tx_fcs),
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// List of inputs
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// List of inputs
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.gen_tx_crc(tx2tc_gen_crc),
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.gen_tx_crc(tx2tc_gen_crc),
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.tx_reset_crc(tx2mi_strt_preamble),
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.tx_reset_crc(tx2mi_strt_preamble),
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.tx_data(tx2mi_byte),
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.tx_data(tx2mi_byte),
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.sclk(tx_clk),
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.sclk(tx_clk),
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.reset_n(tx_reset_n)
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.reset_n(tx_reset_n)
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);
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);
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endmodule
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endmodule
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