//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// Tubo 8051 cores MAC Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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// Description :
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// Description :
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// This module instantiates the MAC block and the FIFO interface
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// This module instantiates the MAC block and the FIFO interface
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//
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//
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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module g_mac_top (
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module g_mac_top (
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scan_mode,
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scan_mode,
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s_reset_n,
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s_reset_n,
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tx_reset_n,
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tx_reset_n,
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rx_reset_n,
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rx_reset_n,
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reset_mdio_clk_n,
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reset_mdio_clk_n,
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app_reset_n,
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app_reset_n,
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|
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app_clk,
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app_clk,
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app_send_pause_i,
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app_send_pause_i,
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app_send_pause_active_o,
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app_send_pause_active_o,
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app_send_jam_i,
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app_send_jam_i,
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|
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// Application RX FIFO Interface
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// Application RX FIFO Interface
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app_txfifo_wren_i,
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app_txfifo_wren_i,
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app_txfifo_wrdata_i,
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app_txfifo_wrdata_i,
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app_txfifo_full_o,
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app_txfifo_full_o,
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app_txfifo_afull_o,
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app_txfifo_space_o,
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app_txfifo_space_o,
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// Application TX FIFO Interface
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// Application TX FIFO Interface
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app_rxfifo_rden_i,
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app_rxfifo_rden_i,
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app_rxfifo_empty_o,
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app_rxfifo_empty_o,
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app_rxfifo_aempty_o,
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app_rxfifo_cnt_o,
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app_rxfifo_cnt_o,
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app_rxfifo_rdata_o,
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app_rxfifo_rdata_o,
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|
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// Conntrol Bus Sync with Application Clock
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// Conntrol Bus Sync with Application Clock
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reg_cs,
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reg_cs,
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reg_wr,
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reg_wr,
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reg_addr,
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reg_addr,
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reg_wdata,
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reg_wdata,
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reg_be,
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reg_be,
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// Outputs
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// Outputs
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reg_rdata,
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reg_rdata,
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reg_ack,
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reg_ack,
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|
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|
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// Phy Signals
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// Phy Signals
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// Line Side Interface TX Path
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// Line Side Interface TX Path
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phy_tx_en,
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phy_tx_en,
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phy_tx_er,
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phy_tx_er,
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phy_txd,
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phy_txd,
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phy_tx_clk,
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phy_tx_clk,
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// Line Side Interface RX Path
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// Line Side Interface RX Path
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phy_rx_clk,
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phy_rx_clk,
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phy_rx_er,
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phy_rx_er,
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phy_rx_dv,
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phy_rx_dv,
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phy_rxd,
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phy_rxd,
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phy_crs,
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phy_crs,
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|
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//MDIO interface
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//MDIO interface
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mdio_clk,
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mdio_clk,
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mdio_in,
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mdio_in,
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mdio_out_en,
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mdio_out_en,
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mdio_out
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mdio_out
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);
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);
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parameter W = 8'd9;
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parameter W = 8'd9;
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parameter DP = 8'd32;
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parameter DP = 8'd32;
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parameter AW = (DP == 2) ? 1 :
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parameter AW = (DP == 2) ? 1 :
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(DP == 4) ? 2 :
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(DP == 4) ? 2 :
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(DP == 8) ? 3 :
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(DP == 8) ? 3 :
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(DP == 16) ? 4 :
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(DP == 16) ? 4 :
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(DP == 32) ? 5 :
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(DP == 32) ? 5 :
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(DP == 64) ? 6 :
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(DP == 64) ? 6 :
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(DP == 128) ? 7 :
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(DP == 128) ? 7 :
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(DP == 256) ? 8 : 0;
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(DP == 256) ? 8 : 0;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// INPUT/OUTPUT DECLARATIONS
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// INPUT/OUTPUT DECLARATIONS
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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input scan_mode;
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input scan_mode;
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input s_reset_n;
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input s_reset_n;
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input tx_reset_n;
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input tx_reset_n;
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input rx_reset_n;
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input rx_reset_n;
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input reset_mdio_clk_n;
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input reset_mdio_clk_n;
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input app_reset_n;
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input app_reset_n;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Application Clock Related Declaration
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// Application Clock Related Declaration
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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input app_clk;
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input app_clk;
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input app_send_pause_i;
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input app_send_pause_i;
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output app_send_pause_active_o;
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output app_send_pause_active_o;
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input app_send_jam_i;
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input app_send_jam_i;
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// Application RX FIFO Interface
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// Application RX FIFO Interface
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input app_txfifo_wren_i;
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input app_txfifo_wren_i;
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input [8:0] app_txfifo_wrdata_i;
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input [8:0] app_txfifo_wrdata_i;
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output app_txfifo_full_o;
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output app_txfifo_full_o;
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output app_txfifo_afull_o;
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output [AW:0] app_txfifo_space_o;
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output [AW:0] app_txfifo_space_o;
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// Application TX FIFO Interface
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// Application TX FIFO Interface
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input app_rxfifo_rden_i;
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input app_rxfifo_rden_i;
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output app_rxfifo_empty_o;
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output app_rxfifo_empty_o;
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output app_rxfifo_aempty_o;
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output [AW:0] app_rxfifo_cnt_o;
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output [AW:0] app_rxfifo_cnt_o;
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output [8:0] app_rxfifo_rdata_o;
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output [8:0] app_rxfifo_rdata_o;
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|
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// Conntrol Bus Sync with Application Clock
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// Conntrol Bus Sync with Application Clock
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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input reg_cs ;
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input reg_cs ;
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input reg_wr ;
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input reg_wr ;
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input [3:0] reg_addr ;
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input [3:0] reg_addr ;
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input [31:0] reg_wdata ;
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input [31:0] reg_wdata ;
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input [3:0] reg_be ;
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input [3:0] reg_be ;
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// Outputs
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// Outputs
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output [31:0] reg_rdata ;
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output [31:0] reg_rdata ;
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output reg_ack ;
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output reg_ack ;
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Line-Tx Signal
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// Line-Tx Signal
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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output phy_tx_en;
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output phy_tx_en;
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output phy_tx_er;
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output phy_tx_er;
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output [7:0] phy_txd;
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output [7:0] phy_txd;
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input phy_tx_clk;
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input phy_tx_clk;
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|
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// Line-Rx Signal
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// Line-Rx Signal
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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input phy_rx_clk;
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input phy_rx_clk;
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input phy_rx_er;
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input phy_rx_er;
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input phy_rx_dv;
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input phy_rx_dv;
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input [7:0] phy_rxd;
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input [7:0] phy_rxd;
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input phy_crs;
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input phy_crs;
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|
|
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// MDIO Signal
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// MDIO Signal
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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input mdio_clk;
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input mdio_clk;
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input mdio_in;
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input mdio_in;
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output mdio_out_en;
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output mdio_out_en;
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output mdio_out;
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output mdio_out;
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//---------------------
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//---------------------
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// RX FIFO Interface Signal
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// RX FIFO Interface Signal
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wire clr_rx_error_from_rx_fsm_o;
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wire clr_rx_error_from_rx_fsm_o;
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wire rx_fifo_full_i;
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wire rx_fifo_full_i;
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wire rx_fifo_wr_o;
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wire rx_fifo_wr_o;
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wire [8:0] rx_fifo_data_o;
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wire [8:0] rx_fifo_data_o;
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wire rx_commit_wr_o;
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wire rx_commit_wr_o;
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wire rx_commit_write_done_o;
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wire rx_commit_write_done_o;
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wire rx_rewind_wr_o;
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wire rx_rewind_wr_o;
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wire rx_fifo_error = 1'b0;
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wire rx_fifo_error = 1'b0;
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|
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// TX-Clock Domain Status Signal
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// TX-Clock Domain Status Signal
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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wire tx_commit_read;
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wire tx_commit_read;
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wire tx_fifo_rd;
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wire tx_fifo_rd;
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|
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wire [8:0] tx_fifo_data;
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wire [8:0] tx_fifo_data;
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wire tx_fifo_empty;
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wire tx_fifo_empty;
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wire tx_fifo_rdy;
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wire tx_fifo_rdy;
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wire [AW:0] tx_fifo_aval;
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wire [AW:0] tx_fifo_aval;
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|
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g_mac_core u_mac_core (
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g_mac_core u_mac_core (
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.scan_mode (scan_mode),
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.scan_mode (scan_mode),
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.s_reset_n (s_reset_n) ,
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.s_reset_n (s_reset_n) ,
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.tx_reset_n (tx_reset_n) ,
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.tx_reset_n (tx_reset_n) ,
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.rx_reset_n (rx_reset_n) ,
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.rx_reset_n (rx_reset_n) ,
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.reset_mdio_clk_n (reset_mdio_clk_n) ,
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.reset_mdio_clk_n (reset_mdio_clk_n) ,
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.app_reset_n (app_reset_n) ,
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.app_reset_n (app_reset_n) ,
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|
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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. reg_cs (reg_cs),
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. reg_cs (reg_cs),
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. reg_wr (reg_wr),
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. reg_wr (reg_wr),
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. reg_addr (reg_addr),
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. reg_addr (reg_addr),
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. reg_wdata (reg_wdata),
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. reg_wdata (reg_wdata),
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. reg_be (reg_be),
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. reg_be (reg_be),
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|
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// Outputs
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// Outputs
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. reg_rdata (reg_rdata),
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. reg_rdata (reg_rdata),
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. reg_ack (reg_ack),
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. reg_ack (reg_ack),
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|
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.app_clk (app_clk) ,
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.app_clk (app_clk) ,
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.app_send_pause_i (app_send_pause_i) ,
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.app_send_pause_i (app_send_pause_i) ,
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.app_send_pause_active_o (app_send_pause_active_o) ,
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.app_send_pause_active_o (app_send_pause_active_o) ,
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.app_send_jam_i (app_send_jam_i) ,
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.app_send_jam_i (app_send_jam_i) ,
|
|
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// Conntrol Bus Sync with Application Clock
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// Conntrol Bus Sync with Application Clock
|
|
|
|
|
|
|
// RX FIFO Interface Signal
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// RX FIFO Interface Signal
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.rx_fifo_full_i (rx_fifo_full_i) ,
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.rx_fifo_full_i (rx_fifo_full_i) ,
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.rx_fifo_wr_o (rx_fifo_wr_o) ,
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.rx_fifo_wr_o (rx_fifo_wr_o) ,
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.rx_fifo_data_o (rx_fifo_data_o) ,
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.rx_fifo_data_o (rx_fifo_data_o) ,
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.rx_commit_wr_o (rx_commit_wr_o) ,
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.rx_commit_wr_o (rx_commit_wr_o) ,
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.rx_rewind_wr_o (rx_rewind_wr_o) ,
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.rx_rewind_wr_o (rx_rewind_wr_o) ,
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.rx_commit_write_done_o (rx_commit_write_done_o) ,
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.rx_commit_write_done_o (rx_commit_write_done_o) ,
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.clr_rx_error_from_rx_fsm_o(clr_rx_error_from_rx_fsm_o) ,
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.clr_rx_error_from_rx_fsm_o(clr_rx_error_from_rx_fsm_o) ,
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.rx_fifo_error_i (rx_fifo_error) ,
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.rx_fifo_error_i (rx_fifo_error) ,
|
|
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// TX FIFO Interface Signal
|
// TX FIFO Interface Signal
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.tx_fifo_data_i (tx_fifo_data) ,
|
.tx_fifo_data_i (tx_fifo_data) ,
|
.tx_fifo_empty_i (tx_fifo_empty) ,
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.tx_fifo_empty_i (tx_fifo_empty) ,
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.tx_fifo_rdy_i (tx_fifo_rdy) , // See to connect to config
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.tx_fifo_rdy_i (tx_fifo_rdy) , // See to connect to config
|
.tx_fifo_rd_o (tx_fifo_rd) ,
|
.tx_fifo_rd_o (tx_fifo_rd) ,
|
.tx_commit_read_o (tx_commit_read) ,
|
.tx_commit_read_o (tx_commit_read) ,
|
|
|
// Phy Signals
|
// Phy Signals
|
|
|
// Line Side Interface TX Path
|
// Line Side Interface TX Path
|
.phy_tx_en (phy_tx_en) ,
|
.phy_tx_en (phy_tx_en) ,
|
.phy_tx_er (phy_tx_er) ,
|
.phy_tx_er (phy_tx_er) ,
|
.phy_txd (phy_txd) ,
|
.phy_txd (phy_txd) ,
|
.phy_tx_clk (phy_tx_clk) ,
|
.phy_tx_clk (phy_tx_clk) ,
|
|
|
// Line Side Interface RX Path
|
// Line Side Interface RX Path
|
.phy_rx_clk (phy_rx_clk) ,
|
.phy_rx_clk (phy_rx_clk) ,
|
.phy_rx_er (phy_rx_er) ,
|
.phy_rx_er (phy_rx_er) ,
|
.phy_rx_dv (phy_rx_dv) ,
|
.phy_rx_dv (phy_rx_dv) ,
|
.phy_rxd (phy_rxd) ,
|
.phy_rxd (phy_rxd) ,
|
.phy_crs (phy_crs) ,
|
.phy_crs (phy_crs) ,
|
|
|
//MDIO interface
|
//MDIO interface
|
.mdio_clk (mdio_clk) ,
|
.mdio_clk (mdio_clk) ,
|
.mdio_in (mdio_in) ,
|
.mdio_in (mdio_in) ,
|
.mdio_out_en (mdio_out_en) ,
|
.mdio_out_en (mdio_out_en) ,
|
.mdio_out (mdio_out)
|
.mdio_out (mdio_out)
|
);
|
);
|
|
|
assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
|
assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
|
|
|
async_fifo #(W,DP,0,0) u_mac_txfifo (
|
async_fifo #(W,DP,0,0) u_mac_txfifo (
|
.wr_clk (app_clk),
|
.wr_clk (app_clk),
|
.wr_reset_n (app_reset_n),
|
.wr_reset_n (app_reset_n),
|
.wr_en (app_txfifo_wren_i),
|
.wr_en (app_txfifo_wren_i),
|
.wr_data (app_txfifo_wrdata_i),
|
.wr_data (app_txfifo_wrdata_i),
|
.full (app_txfifo_full_o), // sync'ed to wr_clk
|
.full (app_txfifo_full_o), // sync'ed to wr_clk
|
|
.afull (app_txfifo_afull_o), // sync'ed to wr_clk
|
.wr_total_free_space (app_txfifo_space_o),
|
.wr_total_free_space (app_txfifo_space_o),
|
|
|
.rd_clk (phy_tx_clk),
|
.rd_clk (phy_tx_clk),
|
.rd_reset_n (tx_reset_n),
|
.rd_reset_n (tx_reset_n),
|
.rd_en (tx_fifo_rd),
|
.rd_en (tx_fifo_rd),
|
.empty (tx_fifo_empty), // sync'ed to rd_clk
|
.empty (tx_fifo_empty), // sync'ed to rd_clk
|
|
.aempty (tx_fifo_aempty), // sync'ed to rd_clk
|
.rd_total_aval (tx_fifo_aval),
|
.rd_total_aval (tx_fifo_aval),
|
.rd_data (tx_fifo_data)
|
.rd_data (tx_fifo_data)
|
);
|
);
|
|
|
async_fifo #(W,DP,0,0) u_mac_rxfifo (
|
async_fifo #(W,DP,0,0) u_mac_rxfifo (
|
.wr_clk (phy_rx_clk),
|
.wr_clk (phy_rx_clk),
|
.wr_reset_n (rx_reset_n),
|
.wr_reset_n (rx_reset_n),
|
.wr_en (rx_fifo_wr_o),
|
.wr_en (rx_fifo_wr_o),
|
.wr_data (rx_fifo_data_o),
|
.wr_data (rx_fifo_data_o),
|
.full (rx_fifo_full_i), // sync'ed to wr_clk
|
.full (rx_fifo_full_i), // sync'ed to wr_clk
|
|
.afull (rx_fifo_afull_i), // sync'ed to wr_clk
|
.wr_total_free_space (),
|
.wr_total_free_space (),
|
|
|
.rd_clk (app_clk),
|
.rd_clk (app_clk),
|
.rd_reset_n (app_reset_n),
|
.rd_reset_n (app_reset_n),
|
.rd_en (app_rxfifo_rden_i),
|
.rd_en (app_rxfifo_rden_i),
|
.empty (app_rxfifo_empty_o), // sync'ed to rd_clk
|
.empty (app_rxfifo_empty_o), // sync'ed to rd_clk
|
|
.aempty (app_rxfifo_aempty_o), // sync'ed to rd_clk
|
.rd_total_aval (app_rxfifo_cnt_o),
|
.rd_total_aval (app_rxfifo_cnt_o),
|
.rd_data (app_rxfifo_rdata_o)
|
.rd_data (app_rxfifo_rdata_o)
|
);
|
);
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|