//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores common library Module ////
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//// Tubo 8051 cores common library Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//-------------------------------------------
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//-------------------------------------------
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// async_fifo:: async FIFO
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// async_fifo:: async FIFO
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// Basic RTL is ported from p600 async_fifo.v
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// Basic RTL is ported from p600 async_fifo.v
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// Following two ports are newly added
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// Following two ports are newly added
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// 1. At write clock domain:
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// 1. At write clock domain:
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// wr_total_free_space --> Indicate total free transfer available
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// wr_total_free_space --> Indicate total free transfer available
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// 2. At read clock domain:
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// 2. At read clock domain:
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// rd_total_aval --> Indicate total no of transfer available
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// rd_total_aval --> Indicate total no of transfer available
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//-----------------------------------------------
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//-----------------------------------------------
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|
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module async_fifo (wr_clk,
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module async_fifo (wr_clk,
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wr_reset_n,
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wr_reset_n,
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wr_en,
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wr_en,
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wr_data,
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wr_data,
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full, // sync'ed to wr_clk
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full, // sync'ed to wr_clk
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afull, // sync'ed to wr_clk
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afull, // sync'ed to wr_clk
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wr_total_free_space,
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wr_total_free_space,
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rd_clk,
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rd_clk,
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rd_reset_n,
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rd_reset_n,
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rd_en,
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rd_en,
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empty, // sync'ed to rd_clk
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empty, // sync'ed to rd_clk
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aempty, // sync'ed to rd_clk
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aempty, // sync'ed to rd_clk
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rd_total_aval,
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rd_total_aval,
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rd_data);
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rd_data);
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parameter W = 4'd8;
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parameter W = 4'd8;
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parameter DP = 3'd4;
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parameter DP = 3'd4;
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parameter WR_FAST = 1'b1;
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parameter WR_FAST = 1'b1;
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parameter RD_FAST = 1'b1;
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parameter RD_FAST = 1'b1;
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parameter FULL_DP = DP;
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parameter FULL_DP = DP;
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parameter EMPTY_DP = 1'b0;
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parameter EMPTY_DP = 1'b0;
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|
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parameter AW = (DP == 2) ? 1 :
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parameter AW = (DP == 2) ? 1 :
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(DP == 4) ? 2 :
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(DP == 4) ? 2 :
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(DP == 8) ? 3 :
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(DP == 8) ? 3 :
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(DP == 16) ? 4 :
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(DP == 16) ? 4 :
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(DP == 32) ? 5 :
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(DP == 32) ? 5 :
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(DP == 64) ? 6 :
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(DP == 64) ? 6 :
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(DP == 128) ? 7 :
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(DP == 128) ? 7 :
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(DP == 256) ? 8 : 0;
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(DP == 256) ? 8 : 0;
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output [W-1 : 0] rd_data;
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output [W-1 : 0] rd_data;
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input [W-1 : 0] wr_data;
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input [W-1 : 0] wr_data;
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input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
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input wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
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rd_en;
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rd_en;
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output full, empty;
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output full, empty;
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output afull, aempty; // about full and about to empty
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output afull, aempty; // about full and about to empty
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output [AW:0] wr_total_free_space; // Total Number of free space aval
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output [AW:0] wr_total_free_space; // Total Number of free space aval
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// w.r.t write clk
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// w.r.t write clk
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// note: Without accounting byte enables
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// note: Without accounting byte enables
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output [AW:0] rd_total_aval; // Total Number of words avaialble
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output [AW:0] rd_total_aval; // Total Number of words avaialble
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// w.r.t rd clock,
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// w.r.t rd clock,
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// note: Without accounting byte enables
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// note: Without accounting byte enables
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// synopsys translate_off
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// synopsys translate_off
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initial begin
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initial begin
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if (AW == 0) begin
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if (AW == 0) begin
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$display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
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$display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
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end // if (AW == 0)
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end // if (AW == 0)
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end // initial begin
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end // initial begin
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// synopsys translate_on
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// synopsys translate_on
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reg [W-1 : 0] mem[DP-1 : 0];
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reg [W-1 : 0] mem[DP-1 : 0];
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/*********************** write side ************************/
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/*********************** write side ************************/
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reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
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reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1;
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wire [AW:0] sync_rd_ptr;
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wire [AW:0] sync_rd_ptr;
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reg [AW:0] wr_ptr, grey_wr_ptr;
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reg [AW:0] wr_ptr, grey_wr_ptr;
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reg [AW:0] grey_rd_ptr;
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reg [AW:0] grey_rd_ptr;
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reg full_q;
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reg full_q;
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wire full_c;
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wire full_c;
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wire afull_c;
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wire afull_c;
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wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
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wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
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wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
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wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
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assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
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assign full_c = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
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assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
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assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
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//--------------------------
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//--------------------------
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// Shows total number of words
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// Shows total number of words
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// of free space available w.r.t write clock
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// of free space available w.r.t write clock
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//---------------------------
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//---------------------------
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assign wr_total_free_space = FULL_DP - wr_cnt;
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assign wr_total_free_space = FULL_DP - wr_cnt;
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|
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always @(posedge wr_clk or negedge wr_reset_n) begin
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always @(posedge wr_clk or negedge wr_reset_n) begin
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if (!wr_reset_n) begin
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if (!wr_reset_n) begin
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wr_ptr <= 0;
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wr_ptr <= 0;
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grey_wr_ptr <= 0;
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grey_wr_ptr <= 0;
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full_q <= 0;
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full_q <= 0;
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end
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end
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else if (wr_en) begin
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else if (wr_en) begin
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wr_ptr <= wr_ptr_inc;
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wr_ptr <= wr_ptr_inc;
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grey_wr_ptr <= bin2grey(wr_ptr_inc);
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grey_wr_ptr <= bin2grey(wr_ptr_inc);
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if (wr_cnt == (FULL_DP-1)) begin
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if (wr_cnt == (FULL_DP-1)) begin
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full_q <= 1'b1;
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full_q <= 1'b1;
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end
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end
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end
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end
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else begin
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else begin
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if (full_q && (wr_cnt<FULL_DP)) begin
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if (full_q && (wr_cnt<FULL_DP)) begin
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full_q <= 1'b0;
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full_q <= 1'b0;
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end
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end
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end
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end
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end
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end
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assign full = (WR_FAST == 1) ? full_c : full_q;
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assign full = (WR_FAST == 1) ? full_c : full_q;
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assign afull = full_c;
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assign afull = afull_c;
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always @(posedge wr_clk) begin
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always @(posedge wr_clk) begin
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if (wr_en) begin
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if (wr_en) begin
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mem[wr_ptr[AW-1:0]] <= wr_data;
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mem[wr_ptr[AW-1:0]] <= wr_data;
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end
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end
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end
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end
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wire [AW:0] grey_rd_ptr_dly ;
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wire [AW:0] grey_rd_ptr_dly ;
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assign #1 grey_rd_ptr_dly = grey_rd_ptr;
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assign #1 grey_rd_ptr_dly = grey_rd_ptr;
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|
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// read pointer synchronizer
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// read pointer synchronizer
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always @(posedge wr_clk or negedge wr_reset_n) begin
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always @(posedge wr_clk or negedge wr_reset_n) begin
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if (!wr_reset_n) begin
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if (!wr_reset_n) begin
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sync_rd_ptr_0 <= 0;
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sync_rd_ptr_0 <= 0;
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sync_rd_ptr_1 <= 0;
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sync_rd_ptr_1 <= 0;
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end
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end
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else begin
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else begin
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sync_rd_ptr_0 <= grey_rd_ptr_dly;
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sync_rd_ptr_0 <= grey_rd_ptr_dly;
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sync_rd_ptr_1 <= sync_rd_ptr_0;
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sync_rd_ptr_1 <= sync_rd_ptr_0;
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end
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end
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end
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end
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assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
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assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
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/************************ read side *****************************/
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/************************ read side *****************************/
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reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
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reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1;
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wire [AW:0] sync_wr_ptr;
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wire [AW:0] sync_wr_ptr;
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reg [AW:0] rd_ptr;
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reg [AW:0] rd_ptr;
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reg empty_q;
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reg empty_q;
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wire empty_c;
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wire empty_c;
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wire aempty_c;
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wire aempty_c;
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wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
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wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
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wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
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wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
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wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
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wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
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|
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assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
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assign empty_c = (rd_cnt == 0) ? 1'b1 : 1'b0;
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assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
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assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
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//--------------------------
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//--------------------------
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// Shows total number of words
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// Shows total number of words
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// space available w.r.t write clock
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// space available w.r.t write clock
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//---------------------------
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//---------------------------
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assign rd_total_aval = rd_cnt;
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assign rd_total_aval = rd_cnt;
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|
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always @(posedge rd_clk or negedge rd_reset_n) begin
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always @(posedge rd_clk or negedge rd_reset_n) begin
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if (!rd_reset_n) begin
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if (!rd_reset_n) begin
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rd_ptr <= 0;
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rd_ptr <= 0;
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grey_rd_ptr <= 0;
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grey_rd_ptr <= 0;
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empty_q <= 1'b1;
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empty_q <= 1'b1;
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end
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end
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else begin
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else begin
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if (rd_en) begin
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if (rd_en) begin
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rd_ptr <= rd_ptr_inc;
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rd_ptr <= rd_ptr_inc;
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grey_rd_ptr <= bin2grey(rd_ptr_inc);
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grey_rd_ptr <= bin2grey(rd_ptr_inc);
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if (rd_cnt==(EMPTY_DP+1)) begin
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if (rd_cnt==(EMPTY_DP+1)) begin
|
empty_q <= 1'b1;
|
empty_q <= 1'b1;
|
end
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end
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end
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end
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else begin
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else begin
|
if (empty_q && (rd_cnt!=EMPTY_DP)) begin
|
if (empty_q && (rd_cnt!=EMPTY_DP)) begin
|
empty_q <= 1'b0;
|
empty_q <= 1'b0;
|
end
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end
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end
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end
|
end
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end
|
end
|
end
|
|
|
assign empty = (RD_FAST == 1) ? empty_c : empty_q;
|
assign empty = (RD_FAST == 1) ? empty_c : empty_q;
|
assign aempty = aempty_c;
|
assign aempty = aempty_c;
|
|
|
assign rd_data = mem[rd_ptr[AW-1:0]];
|
assign rd_data = mem[rd_ptr[AW-1:0]];
|
|
|
wire [AW:0] grey_wr_ptr_dly ;
|
wire [AW:0] grey_wr_ptr_dly ;
|
assign #1 grey_wr_ptr_dly = grey_wr_ptr;
|
assign #1 grey_wr_ptr_dly = grey_wr_ptr;
|
|
|
// write pointer synchronizer
|
// write pointer synchronizer
|
always @(posedge rd_clk or negedge rd_reset_n) begin
|
always @(posedge rd_clk or negedge rd_reset_n) begin
|
if (!rd_reset_n) begin
|
if (!rd_reset_n) begin
|
sync_wr_ptr_0 <= 0;
|
sync_wr_ptr_0 <= 0;
|
sync_wr_ptr_1 <= 0;
|
sync_wr_ptr_1 <= 0;
|
end
|
end
|
else begin
|
else begin
|
sync_wr_ptr_0 <= grey_wr_ptr_dly;
|
sync_wr_ptr_0 <= grey_wr_ptr_dly;
|
sync_wr_ptr_1 <= sync_wr_ptr_0;
|
sync_wr_ptr_1 <= sync_wr_ptr_0;
|
end
|
end
|
end
|
end
|
assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
|
assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
|
|
|
|
|
/************************ functions ******************************/
|
/************************ functions ******************************/
|
function [AW:0] bin2grey;
|
function [AW:0] bin2grey;
|
input [AW:0] bin;
|
input [AW:0] bin;
|
reg [8:0] bin_8;
|
reg [8:0] bin_8;
|
reg [8:0] grey_8;
|
reg [8:0] grey_8;
|
begin
|
begin
|
bin_8 = bin;
|
bin_8 = bin;
|
grey_8[1:0] = do_grey(bin_8[2:0]);
|
grey_8[1:0] = do_grey(bin_8[2:0]);
|
grey_8[3:2] = do_grey(bin_8[4:2]);
|
grey_8[3:2] = do_grey(bin_8[4:2]);
|
grey_8[5:4] = do_grey(bin_8[6:4]);
|
grey_8[5:4] = do_grey(bin_8[6:4]);
|
grey_8[7:6] = do_grey(bin_8[8:6]);
|
grey_8[7:6] = do_grey(bin_8[8:6]);
|
grey_8[8] = bin_8[8];
|
grey_8[8] = bin_8[8];
|
bin2grey = grey_8;
|
bin2grey = grey_8;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
function [AW:0] grey2bin;
|
function [AW:0] grey2bin;
|
input [AW:0] grey;
|
input [AW:0] grey;
|
reg [8:0] grey_8;
|
reg [8:0] grey_8;
|
reg [8:0] bin_8;
|
reg [8:0] bin_8;
|
begin
|
begin
|
grey_8 = grey;
|
grey_8 = grey;
|
bin_8[8] = grey_8[8];
|
bin_8[8] = grey_8[8];
|
bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
|
bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
|
bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
|
bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
|
bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
|
bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
|
bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
|
bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
|
grey2bin = bin_8;
|
grey2bin = bin_8;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
|
function [1:0] do_grey;
|
function [1:0] do_grey;
|
input [2:0] bin;
|
input [2:0] bin;
|
begin
|
begin
|
if (bin[2]) begin // do reverse grey
|
if (bin[2]) begin // do reverse grey
|
case (bin[1:0])
|
case (bin[1:0])
|
2'b00: do_grey = 2'b10;
|
2'b00: do_grey = 2'b10;
|
2'b01: do_grey = 2'b11;
|
2'b01: do_grey = 2'b11;
|
2'b10: do_grey = 2'b01;
|
2'b10: do_grey = 2'b01;
|
2'b11: do_grey = 2'b00;
|
2'b11: do_grey = 2'b00;
|
endcase
|
endcase
|
end
|
end
|
else begin
|
else begin
|
case (bin[1:0])
|
case (bin[1:0])
|
2'b00: do_grey = 2'b00;
|
2'b00: do_grey = 2'b00;
|
2'b01: do_grey = 2'b01;
|
2'b01: do_grey = 2'b01;
|
2'b10: do_grey = 2'b11;
|
2'b10: do_grey = 2'b11;
|
2'b11: do_grey = 2'b10;
|
2'b11: do_grey = 2'b10;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
endfunction
|
endfunction
|
|
|
function [1:0] do_bin;
|
function [1:0] do_bin;
|
input [2:0] grey;
|
input [2:0] grey;
|
begin
|
begin
|
if (grey[2]) begin // actually bin[2]
|
if (grey[2]) begin // actually bin[2]
|
case (grey[1:0])
|
case (grey[1:0])
|
2'b10: do_bin = 2'b00;
|
2'b10: do_bin = 2'b00;
|
2'b11: do_bin = 2'b01;
|
2'b11: do_bin = 2'b01;
|
2'b01: do_bin = 2'b10;
|
2'b01: do_bin = 2'b10;
|
2'b00: do_bin = 2'b11;
|
2'b00: do_bin = 2'b11;
|
endcase
|
endcase
|
end
|
end
|
else begin
|
else begin
|
case (grey[1:0])
|
case (grey[1:0])
|
2'b00: do_bin = 2'b00;
|
2'b00: do_bin = 2'b00;
|
2'b01: do_bin = 2'b01;
|
2'b01: do_bin = 2'b01;
|
2'b11: do_bin = 2'b10;
|
2'b11: do_bin = 2'b10;
|
2'b10: do_bin = 2'b11;
|
2'b10: do_bin = 2'b11;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
endfunction
|
endfunction
|
|
|
function [AW:0] get_cnt;
|
function [AW:0] get_cnt;
|
input [AW:0] wr_ptr, rd_ptr;
|
input [AW:0] wr_ptr, rd_ptr;
|
begin
|
begin
|
if (wr_ptr >= rd_ptr) begin
|
if (wr_ptr >= rd_ptr) begin
|
get_cnt = (wr_ptr - rd_ptr);
|
get_cnt = (wr_ptr - rd_ptr);
|
end
|
end
|
else begin
|
else begin
|
get_cnt = DP*2 - (rd_ptr - wr_ptr);
|
get_cnt = DP*2 - (rd_ptr - wr_ptr);
|
end
|
end
|
end
|
end
|
endfunction
|
endfunction
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
always @(posedge wr_clk) begin
|
always @(posedge wr_clk) begin
|
if (wr_en && full) begin
|
if (wr_en && full) begin
|
$display($time, "%m Error! afifo overflow!");
|
$display($time, "%m Error! afifo overflow!");
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge rd_clk) begin
|
always @(posedge rd_clk) begin
|
if (rd_en && empty) begin
|
if (rd_en && empty) begin
|
$display($time, "%m error! afifo underflow!");
|
$display($time, "%m error! afifo underflow!");
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
// gray code monitor
|
// gray code monitor
|
reg [AW:0] last_gwr_ptr;
|
reg [AW:0] last_gwr_ptr;
|
always @(posedge wr_clk or negedge wr_reset_n) begin
|
always @(posedge wr_clk or negedge wr_reset_n) begin
|
if (!wr_reset_n) begin
|
if (!wr_reset_n) begin
|
last_gwr_ptr <= #1 0;
|
last_gwr_ptr <= #1 0;
|
end
|
end
|
else if (last_gwr_ptr !== grey_wr_ptr) begin
|
else if (last_gwr_ptr !== grey_wr_ptr) begin
|
check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
|
check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
|
last_gwr_ptr <= #1 grey_wr_ptr;
|
last_gwr_ptr <= #1 grey_wr_ptr;
|
end
|
end
|
end
|
end
|
|
|
reg [AW:0] last_grd_ptr;
|
reg [AW:0] last_grd_ptr;
|
always @(posedge rd_clk or negedge rd_reset_n) begin
|
always @(posedge rd_clk or negedge rd_reset_n) begin
|
if (!rd_reset_n) begin
|
if (!rd_reset_n) begin
|
last_grd_ptr <= #1 0;
|
last_grd_ptr <= #1 0;
|
end
|
end
|
else if (last_grd_ptr !== grey_rd_ptr) begin
|
else if (last_grd_ptr !== grey_rd_ptr) begin
|
check_ptr_chg(last_grd_ptr, grey_rd_ptr);
|
check_ptr_chg(last_grd_ptr, grey_rd_ptr);
|
last_grd_ptr <= #1 grey_rd_ptr;
|
last_grd_ptr <= #1 grey_rd_ptr;
|
end
|
end
|
end
|
end
|
|
|
task check_ptr_chg;
|
task check_ptr_chg;
|
input [AW:0] last_ptr;
|
input [AW:0] last_ptr;
|
input [AW:0] cur_ptr;
|
input [AW:0] cur_ptr;
|
integer i;
|
integer i;
|
integer ptr_diff;
|
integer ptr_diff;
|
begin
|
begin
|
ptr_diff = 0;
|
ptr_diff = 0;
|
for (i=0; i<= AW; i=i+ 1'b1) begin
|
for (i=0; i<= AW; i=i+ 1'b1) begin
|
if (last_ptr[i] != cur_ptr[i]) begin
|
if (last_ptr[i] != cur_ptr[i]) begin
|
ptr_diff = ptr_diff + 1'b1;
|
ptr_diff = ptr_diff + 1'b1;
|
end
|
end
|
end
|
end
|
if (ptr_diff !== 1) begin
|
if (ptr_diff !== 1) begin
|
$display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
|
$display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
|
last_ptr, cur_ptr);
|
last_ptr, cur_ptr);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
endmodule
|
endmodule
|
|
|