//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Tubo 8051 cores SPI Interface Module ////
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//// Tubo 8051 cores SPI Interface Module ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module spi_ctl
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module spi_ctl
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( clk,
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( clk,
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reset_n,
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reset_n,
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sck_int,
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sck_int,
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cfg_op_req,
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cfg_op_req,
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cfg_op_type,
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cfg_op_type,
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cfg_transfer_size,
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cfg_transfer_size,
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cfg_sck_period,
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cfg_sck_period,
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cfg_sck_cs_period,
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cfg_sck_cs_period,
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cfg_cs_byte,
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cfg_cs_byte,
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cfg_datain,
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cfg_datain,
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cfg_dataout,
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cfg_dataout,
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op_done,
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op_done,
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cs_int_n,
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cs_int_n,
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sck_pe,
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sck_pe,
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sck_ne,
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sck_ne,
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shift_out,
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shift_out,
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shift_in,
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shift_in,
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byte_out,
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byte_out,
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byte_in,
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byte_in,
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load_byte
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load_byte
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);
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);
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//*************************************************************************
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//*************************************************************************
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input clk, reset_n;
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input clk, reset_n;
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input cfg_op_req;
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input cfg_op_req;
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input [1:0] cfg_op_type;
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input [1:0] cfg_op_type;
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input [1:0] cfg_transfer_size;
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input [1:0] cfg_transfer_size;
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input [5:0] cfg_sck_period;
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input [5:0] cfg_sck_period;
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input [4:0] cfg_sck_cs_period; // cs setup & hold period
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input [4:0] cfg_sck_cs_period; // cs setup & hold period
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input [7:0] cfg_cs_byte;
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input [7:0] cfg_cs_byte;
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input [31:0] cfg_datain;
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input [31:0] cfg_datain;
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output [31:0] cfg_dataout;
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output [31:0] cfg_dataout;
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output [7:0] byte_out; // Byte out for Serial Shifting out
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output [7:0] byte_out; // Byte out for Serial Shifting out
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input [7:0] byte_in; // Serial Received Byte
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input [7:0] byte_in; // Serial Received Byte
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output sck_int;
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output sck_int;
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output cs_int_n;
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output cs_int_n;
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output sck_pe;
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output sck_pe;
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output sck_ne;
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output sck_ne;
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output shift_out;
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output shift_out;
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output shift_in;
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output shift_in;
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output load_byte;
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output load_byte;
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output op_done;
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output op_done;
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reg [31:0] cfg_dataout;
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reg [31:0] cfg_dataout;
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reg sck_ne;
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reg sck_ne;
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reg sck_pe;
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reg sck_pe;
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reg sck_int;
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reg sck_int;
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reg [5:0] clk_cnt;
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reg [5:0] clk_cnt;
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reg [5:0] sck_cnt;
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reg [5:0] sck_cnt;
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reg [3:0] spiif_cs;
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reg [3:0] spiif_cs;
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reg shift_enb;
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reg shift_enb;
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reg cs_int_n;
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reg cs_int_n;
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reg clr_sck_cnt ;
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reg clr_sck_cnt ;
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reg sck_out_en;
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reg sck_out_en;
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wire [5:0] sck_half_period;
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wire [5:0] sck_half_period;
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reg load_byte;
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reg load_byte;
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reg shift_in;
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reg shift_in;
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reg op_done;
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reg op_done;
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reg [2:0] byte_cnt;
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reg [2:0] byte_cnt;
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`define SPI_IDLE 4'b0000
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`define SPI_IDLE 4'b0000
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`define SPI_CS_SU 4'b0001
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`define SPI_CS_SU 4'b0001
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`define SPI_WRITE 4'b0010
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`define SPI_WRITE 4'b0010
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`define SPI_READ 4'b0011
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`define SPI_READ 4'b0011
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`define SPI_CS_HLD 4'b0100
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`define SPI_CS_HLD 4'b0100
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`define SPI_WAIT 4'b0101
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`define SPI_WAIT 4'b0101
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assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
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assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
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// The first transition on the sck_toggle happens one SCK period
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// The first transition on the sck_toggle happens one SCK period
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// after op_en or boot_en is asserted
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// after op_en or boot_en is asserted
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if(!reset_n) begin
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if(!reset_n) begin
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sck_ne <= 1'b0;
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sck_ne <= 1'b0;
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clk_cnt <= 6'h1;
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clk_cnt <= 6'h1;
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sck_pe <= 1'b0;
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sck_pe <= 1'b0;
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sck_int <= 1'b0;
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sck_int <= 1'b0;
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end // if (!reset_n)
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end // if (!reset_n)
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else
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else
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begin
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begin
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if(cfg_op_req)
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if(cfg_op_req)
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begin
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begin
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if(clk_cnt == sck_half_period)
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if(clk_cnt == sck_half_period)
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begin
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begin
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sck_ne <= 1'b1;
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sck_ne <= 1'b1;
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sck_pe <= 1'b0;
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sck_pe <= 1'b0;
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if(sck_out_en) sck_int <= 0;
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if(sck_out_en) sck_int <= 0;
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clk_cnt <= clk_cnt + 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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end // if (clk_cnt == sck_half_period)
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end // if (clk_cnt == sck_half_period)
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else
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else
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begin
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begin
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if(clk_cnt == cfg_sck_period)
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if(clk_cnt == cfg_sck_period)
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begin
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begin
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sck_ne <= 1'b0;
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sck_ne <= 1'b0;
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sck_pe <= 1'b1;
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sck_pe <= 1'b1;
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if(sck_out_en) sck_int <= 1;
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if(sck_out_en) sck_int <= 1;
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clk_cnt <= 6'h1;
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clk_cnt <= 6'h1;
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end // if (clk_cnt == cfg_sck_period)
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end // if (clk_cnt == cfg_sck_period)
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else
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else
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begin
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begin
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clk_cnt <= clk_cnt + 1'b1;
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clk_cnt <= clk_cnt + 1'b1;
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sck_pe <= 1'b0;
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sck_pe <= 1'b0;
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sck_ne <= 1'b0;
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sck_ne <= 1'b0;
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end // else: !if(clk_cnt == cfg_sck_period)
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end // else: !if(clk_cnt == cfg_sck_period)
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end // else: !if(clk_cnt == sck_half_period)
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end // else: !if(clk_cnt == sck_half_period)
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end // if (op_en)
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end // if (op_en)
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else
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else
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begin
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begin
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clk_cnt <= 6'h1;
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clk_cnt <= 6'h1;
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sck_pe <= 1'b0;
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sck_pe <= 1'b0;
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sck_ne <= 1'b0;
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sck_ne <= 1'b0;
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end // else: !if(op_en)
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end // else: !if(op_en)
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge clk or negedge reset_n)
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end // always @ (posedge clk or negedge reset_n)
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wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] :
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wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] :
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(byte_cnt == 2'b01) ? cfg_cs_byte[5:4] :
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(byte_cnt == 2'b01) ? cfg_cs_byte[5:4] :
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(byte_cnt == 2'b10) ? cfg_cs_byte[3:2] : cfg_cs_byte[1:0] ;
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(byte_cnt == 2'b10) ? cfg_cs_byte[3:2] : cfg_cs_byte[1:0] ;
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wire [7:0] byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] :
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wire [7:0] byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] :
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(byte_cnt == 2'b01) ? cfg_datain[23:16] :
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(byte_cnt == 2'b01) ? cfg_datain[23:16] :
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(byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0] ;
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(byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0] ;
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assign shift_out = shift_enb && sck_ne;
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assign shift_out = shift_enb && sck_ne;
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if(!reset_n) begin
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if(!reset_n) begin
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spiif_cs <= `SPI_IDLE;
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spiif_cs <= `SPI_IDLE;
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sck_cnt <= 6'h0;
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sck_cnt <= 6'h0;
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shift_in <= 1'b0;
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shift_in <= 1'b0;
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clr_sck_cnt <= 1'b1;
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clr_sck_cnt <= 1'b1;
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byte_cnt <= 2'b00;
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byte_cnt <= 2'b00;
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cs_int_n <= 1'b1;
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cs_int_n <= 1'b1;
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sck_out_en <= 1'b0;
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sck_out_en <= 1'b0;
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shift_enb <= 1'b0;
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shift_enb <= 1'b0;
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cfg_dataout <= 32'h0;
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cfg_dataout <= 32'h0;
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load_byte <= 1'b0;
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load_byte <= 1'b0;
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end
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end
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else begin
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else begin
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if(sck_ne)
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if(sck_ne)
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sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ;
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sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ;
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case(spiif_cs)
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case(spiif_cs)
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`SPI_IDLE :
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`SPI_IDLE :
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begin
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begin
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op_done <= 0;
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op_done <= 0;
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clr_sck_cnt <= 1'b1;
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clr_sck_cnt <= 1'b1;
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sck_out_en <= 1'b0;
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sck_out_en <= 1'b0;
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shift_enb <= 1'b0;
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shift_enb <= 1'b0;
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if(cfg_op_req)
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if(cfg_op_req)
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begin
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begin
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cfg_dataout <= 32'h0;
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cfg_dataout <= 32'h0;
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spiif_cs <= `SPI_CS_SU;
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spiif_cs <= `SPI_CS_SU;
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end
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end
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else begin
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else begin
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spiif_cs <= `SPI_IDLE;
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spiif_cs <= `SPI_IDLE;
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end
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end
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end
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end
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`SPI_CS_SU :
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`SPI_CS_SU :
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begin
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begin
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if(sck_ne) begin
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if(sck_ne) begin
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cs_int_n <= cs_data[1];
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cs_int_n <= cs_data[1];
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if(sck_cnt == cfg_sck_cs_period) begin
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if(sck_cnt == cfg_sck_cs_period) begin
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clr_sck_cnt <= 1'b1;
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clr_sck_cnt <= 1'b1;
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if(cfg_op_type == 0) begin // Write Mode
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if(cfg_op_type == 0) begin // Write Mode
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load_byte <= 1'b1;
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load_byte <= 1'b1;
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spiif_cs <= `SPI_WRITE;
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spiif_cs <= `SPI_WRITE;
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shift_enb <= 1'b0;
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shift_enb <= 1'b0;
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end else begin
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end else begin
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shift_in <= 1;
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shift_in <= 1;
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spiif_cs <= `SPI_READ;
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spiif_cs <= `SPI_READ;
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end
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end
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end
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end
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else begin
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else begin
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clr_sck_cnt <= 1'b0;
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clr_sck_cnt <= 1'b0;
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end
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end
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end
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end
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end
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end
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`SPI_WRITE :
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`SPI_WRITE :
|
begin
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begin
|
load_byte <= 1'b0;
|
load_byte <= 1'b0;
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if(sck_ne) begin
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if(sck_ne) begin
|
if(sck_cnt == 3'h7 )begin
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if(sck_cnt == 3'h7 )begin
|
clr_sck_cnt <= 1'b1;
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clr_sck_cnt <= 1'b1;
|
spiif_cs <= `SPI_CS_HLD;
|
spiif_cs <= `SPI_CS_HLD;
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shift_enb <= 1'b0;
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shift_enb <= 1'b0;
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sck_out_en <= 1'b0; // Disable clock output
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sck_out_en <= 1'b0; // Disable clock output
|
end
|
end
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else begin
|
else begin
|
shift_enb <= 1'b1;
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shift_enb <= 1'b1;
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sck_out_en <= 1'b1;
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sck_out_en <= 1'b1;
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clr_sck_cnt <= 1'b0;
|
clr_sck_cnt <= 1'b0;
|
end
|
end
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end else begin
|
end else begin
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shift_enb <= 1'b1;
|
shift_enb <= 1'b1;
|
end
|
end
|
end
|
end
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|
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`SPI_READ :
|
`SPI_READ :
|
begin
|
begin
|
if(sck_ne) begin
|
if(sck_ne) begin
|
if( sck_cnt == 3'h7 ) begin
|
if( sck_cnt == 3'h7 ) begin
|
clr_sck_cnt <= 1'b1;
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clr_sck_cnt <= 1'b1;
|
shift_in <= 0;
|
shift_in <= 0;
|
spiif_cs <= `SPI_CS_HLD;
|
spiif_cs <= `SPI_CS_HLD;
|
sck_out_en <= 1'b0; // Disable clock output
|
sck_out_en <= 1'b0; // Disable clock output
|
end
|
end
|
else begin
|
else begin
|
sck_out_en <= 1'b1; // Disable clock output
|
sck_out_en <= 1'b1; // Disable clock output
|
clr_sck_cnt <= 1'b0;
|
clr_sck_cnt <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
`SPI_CS_HLD : begin
|
`SPI_CS_HLD : begin
|
if(sck_ne) begin
|
if(sck_ne) begin
|
cs_int_n <= cs_data[0];
|
cs_int_n <= cs_data[0];
|
if(sck_cnt == cfg_sck_cs_period) begin
|
if(sck_cnt == cfg_sck_cs_period) begin
|
if(cfg_op_type == 1) begin // Read Mode
|
if(cfg_op_type == 1) begin // Read Mode
|
cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } :
|
cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } :
|
(byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] ,
|
(byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] ,
|
byte_in, cfg_dataout[15:0] } :
|
byte_in, cfg_dataout[15:0] } :
|
(byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] ,
|
(byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] ,
|
byte_in, cfg_dataout[7:0] } :
|
byte_in, cfg_dataout[7:0] } :
|
{ cfg_dataout[31:8] ,
|
{ cfg_dataout[31:8] ,
|
byte_in } ;
|
byte_in } ;
|
end
|
end
|
clr_sck_cnt <= 1'b1;
|
clr_sck_cnt <= 1'b1;
|
if(byte_cnt == cfg_transfer_size) begin
|
if(byte_cnt == cfg_transfer_size) begin
|
spiif_cs <= `SPI_WAIT;
|
spiif_cs <= `SPI_WAIT;
|
byte_cnt <= 0;
|
byte_cnt <= 0;
|
op_done <= 1;
|
op_done <= 1;
|
end else begin
|
end else begin
|
byte_cnt <= byte_cnt +1;
|
byte_cnt <= byte_cnt +1;
|
spiif_cs <= `SPI_CS_SU;
|
spiif_cs <= `SPI_CS_SU;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
clr_sck_cnt <= 1'b0;
|
clr_sck_cnt <= 1'b0;
|
end
|
end
|
end
|
end
|
end // case: `SPI_CS_HLD
|
end // case: `SPI_CS_HLD
|
`SPI_WAIT : begin
|
`SPI_WAIT : begin
|
if(!cfg_op_req) // Wait for Request de-assertion
|
if(!cfg_op_req) // Wait for Request de-assertion
|
spiif_cs <= `SPI_IDLE;
|
spiif_cs <= `SPI_IDLE;
|
end
|
end
|
endcase // casex(spiif_cs)
|
endcase // casex(spiif_cs)
|
end
|
end
|
end // always @(sck_ne
|
end // always @(sck_ne
|
|
|
endmodule
|
endmodule
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