|
|
/*-----------------------------------------------------------------
|
/*-----------------------------------------------------------------
|
| Ethernet MAC Traffic Generator Testbench |
|
| Ethernet MAC Traffic Generator Testbench |
|
| |
|
| |
|
------------------------------------------------------------------*/
|
------------------------------------------------------------------*/
|
|
|
/*-----------------------------------------------------------------\
|
/*-----------------------------------------------------------------\
|
| DESCRIPTION: |
|
| DESCRIPTION: |
|
| tb_top.v: Top of MAC testbench hierarchy |
|
| tb_top.v: Top of MAC testbench hierarchy |
|
| |
|
| |
|
| Instantiates the following modules: |
|
| Instantiates the following modules: |
|
| tb_mii.v: MII interface |
|
| tb_mii.v: MII interface |
|
| tb_rmii.v: Reduced MII interface |
|
| tb_rmii.v: Reduced MII interface |
|
| tb_smii.v: Serial MII interface (add-on module) |
|
| tb_smii.v: Serial MII interface (add-on module) |
|
| tb_gmii.v: Gigabit MII interface (add-on module) |
|
| tb_gmii.v: Gigabit MII interface (add-on module) |
|
| tb_serd.v: Gigabit SERDES 10-bit interface (add-on module) |
|
| tb_serd.v: Gigabit SERDES 10-bit interface (add-on module) |
|
| |
|
| |
|
| Included files: |
|
| Included files: |
|
| tb_conf.v |
|
| tb_conf.v |
|
| tb_defs.v |
|
| tb_defs.v |
|
| tb_objs.v |
|
| tb_objs.v |
|
| tb_tasks.v |
|
| tb_tasks.v |
|
| tb_pktgn.v |
|
| tb_pktgn.v |
|
\-----------------------------------------------------------------*/
|
\-----------------------------------------------------------------*/
|
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
`include "tb_eth_conf.v"
|
`include "tb_eth_conf.v"
|
`include "tb_eth_defs.v"
|
`include "tb_eth_defs.v"
|
|
|
module tb_eth_top(
|
module tb_eth_top(
|
|
|
REFCLK_50_MHz, // 50 MHz Reference clock input
|
REFCLK_50_MHz, // 50 MHz Reference clock input
|
REFCLK_125_MHz, // 125 MHz reference clock
|
REFCLK_125_MHz, // 125 MHz reference clock
|
transmit_enable, // transmit enable for testbench
|
transmit_enable, // transmit enable for testbench
|
|
|
// Separate interfaces for each MII port type
|
// Separate interfaces for each MII port type
|
|
|
// Full MII, 4-bit interface
|
// Full MII, 4-bit interface
|
// Transmit interface
|
// Transmit interface
|
MII_RXD, // Receive data (output)
|
MII_RXD, // Receive data (output)
|
MII_RX_CLK, // Receive clock for MII (output)
|
MII_RX_CLK, // Receive clock for MII (output)
|
MII_CRS, // carrier sense (output)
|
MII_CRS, // carrier sense (output)
|
MII_COL, // Collision signal for MII (output)
|
MII_COL, // Collision signal for MII (output)
|
MII_RX_DV, // Receive data valid for MII (output)
|
MII_RX_DV, // Receive data valid for MII (output)
|
// Receive interface
|
// Receive interface
|
MII_TXD, // Transmit data (input)
|
MII_TXD, // Transmit data (input)
|
MII_TX_EN, // Tx enable (input)
|
MII_TX_EN, // Tx enable (input)
|
MII_TX_CLK, // Transmit clock (output)
|
MII_TX_CLK, // Transmit clock (output)
|
|
|
// Reduced MII, 2-bit interface
|
// Reduced MII, 2-bit interface
|
// Transmit interface
|
// Transmit interface
|
RMII_RXD, // Receive data (output)
|
RMII_RXD, // Receive data (output)
|
RMII_CRS_DV, // carrier sense (output)
|
RMII_CRS_DV, // carrier sense (output)
|
// Receive interface
|
// Receive interface
|
RMII_TXD, // Transmit data (input)
|
RMII_TXD, // Transmit data (input)
|
RMII_TX_EN, // Tx enable (input)
|
RMII_TX_EN, // Tx enable (input)
|
|
|
// Serial MII interface
|
// Serial MII interface
|
SMII_RXD, // Receive data (output)
|
SMII_RXD, // Receive data (output)
|
SMII_TXD, // Transmit data (input)
|
SMII_TXD, // Transmit data (input)
|
SMII_SYNC, // SMII SYNC signal (input)
|
SMII_SYNC, // SMII SYNC signal (input)
|
|
|
// GMII, 8-bit/10-bit interface
|
// GMII, 8-bit/10-bit interface
|
// Transmit interface
|
// Transmit interface
|
GMII_RXD, // Receive data (output)
|
GMII_RXD, // Receive data (output)
|
GMII_RX_CLK, // Receive clock for MII (output)
|
GMII_RX_CLK, // Receive clock for MII (output)
|
GMII_CRS, // carrier sense (output)
|
GMII_CRS, // carrier sense (output)
|
GMII_COL, // Collision signal for MII (output)
|
GMII_COL, // Collision signal for MII (output)
|
GMII_RX_DV, // Receive data valid for MII (output)
|
GMII_RX_DV, // Receive data valid for MII (output)
|
// Receive interface
|
// Receive interface
|
GMII_TXD, // Transmit data (input)
|
GMII_TXD, // Transmit data (input)
|
GMII_TX_EN, // Tx enable (input)
|
GMII_TX_EN, // Tx enable (input)
|
GMII_TX_CLK, // Transmit clock (output)
|
GMII_TX_CLK, // Transmit clock (output)
|
GMII_GTX_CLK, // Gigabit Transmit clock (input), 125 MHz
|
GMII_GTX_CLK, // Gigabit Transmit clock (input), 125 MHz
|
|
|
// MII management interface
|
// MII management interface
|
MDIO, // serial I/O data
|
MDIO, // serial I/O data
|
MDC // clock
|
MDC // clock
|
);
|
);
|
|
|
|
|
input REFCLK_50_MHz, REFCLK_125_MHz;
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input REFCLK_50_MHz, REFCLK_125_MHz;
|
|
|
input transmit_enable;
|
input transmit_enable;
|
|
|
// Full-MII signals
|
// Full-MII signals
|
output [`MII_WIDTH-1: 0] MII_RXD;
|
output [`MII_WIDTH-1: 0] MII_RXD;
|
output MII_RX_CLK,
|
output MII_RX_CLK,
|
MII_CRS,
|
MII_CRS,
|
MII_COL,
|
MII_COL,
|
MII_RX_DV;
|
MII_RX_DV;
|
input [`MII_WIDTH-1: 0] MII_TXD;
|
input [`MII_WIDTH-1: 0] MII_TXD;
|
input MII_TX_EN;
|
input MII_TX_EN;
|
output MII_TX_CLK;
|
output MII_TX_CLK;
|
|
|
// RMII signals
|
// RMII signals
|
output [`RMII_WIDTH-1: 0] RMII_RXD;
|
output [`RMII_WIDTH-1: 0] RMII_RXD;
|
output RMII_CRS_DV;
|
output RMII_CRS_DV;
|
input [`RMII_WIDTH-1: 0] RMII_TXD;
|
input [`RMII_WIDTH-1: 0] RMII_TXD;
|
input RMII_TX_EN;
|
input RMII_TX_EN;
|
|
|
// Serial MII signals
|
// Serial MII signals
|
output SMII_RXD;
|
output SMII_RXD;
|
input SMII_TXD;
|
input SMII_TXD;
|
input SMII_SYNC;
|
input SMII_SYNC;
|
|
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//Gigabit-MII signals
|
//Gigabit-MII signals
|
output [`GMII_WIDTH-1: 0] GMII_RXD;
|
output [`GMII_WIDTH-1: 0] GMII_RXD;
|
output GMII_RX_CLK,
|
output GMII_RX_CLK,
|
GMII_CRS,
|
GMII_CRS,
|
GMII_COL,
|
GMII_COL,
|
GMII_RX_DV;
|
GMII_RX_DV;
|
input [`GMII_WIDTH-1: 0] GMII_TXD;
|
input [`GMII_WIDTH-1: 0] GMII_TXD;
|
input GMII_TX_EN;
|
input GMII_TX_EN;
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output GMII_TX_CLK;
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output GMII_TX_CLK;
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input GMII_GTX_CLK;
|
input GMII_GTX_CLK;
|
|
|
|
|
// MII Management
|
// MII Management
|
inout MDIO;
|
inout MDIO;
|
input MDC;
|
input MDC;
|
|
|
`include "tb_eth_objs.v"
|
`include "tb_eth_objs.v"
|
|
|
// transmit buffer
|
// transmit buffer
|
reg [`MAX_PKT_SIZE*8 -1:0] transmit_pkt;
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reg [`MAX_PKT_SIZE*8 -1:0] transmit_pkt;
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integer transmit_pkt_size;
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integer transmit_pkt_size;
|
|
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// receive buffer
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// receive buffer
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reg [`MAX_PKT_SIZE*8 -1:0] receive_pkt;
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reg [`MAX_PKT_SIZE*8 -1:0] receive_pkt;
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integer receive_pkt_size;
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integer receive_pkt_size;
|
|
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reg transmit_data_valid;
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reg transmit_data_valid;
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wire transmit_done;
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wire transmit_done;
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wire receive_data_valid;
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wire receive_data_valid;
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reg receive_data_available;
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reg receive_data_available;
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|
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integer transmit_packet_count, packets_sent, transmit_timer;
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integer transmit_packet_count, packets_sent, transmit_timer;
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reg transmit_timer_active, transmit_timer_expired, port_tx_busy;
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reg transmit_timer_active, transmit_timer_expired, port_tx_busy;
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// flag set during transmission of
|
// flag set during transmission of
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// a packet sequence
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// a packet sequence
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//Current transmit packet parameters
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//Current transmit packet parameters
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integer current_pkt_size;
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integer current_pkt_size;
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reg [47:0] current_src_mac, current_dstn_mac;
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reg [47:0] current_src_mac, current_dstn_mac;
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reg [15:0] current_VLAN_TCI;
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reg [15:0] current_VLAN_TCI;
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reg user_frame; // currently transmitting
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reg user_frame; // currently transmitting
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// frame from user buffer
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// frame from user buffer
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integer user_frame_current_ifg;
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integer user_frame_current_ifg;
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// ifg for user frame
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// ifg for user frame
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wire SMII_TX_EN;
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wire SMII_TX_EN;
|
|
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reg [1:0] user_crc_option; // CRC generation option for user frames
|
reg [1:0] user_crc_option; // CRC generation option for user frames
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reg [31:0] user_crc_value; // user-supplied CRC for user-generated frames
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reg [31:0] user_crc_value; // user-supplied CRC for user-generated frames
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|
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// State variables exported to MII module
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// State variables exported to MII module
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integer mii_transmit_state,
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integer mii_transmit_state,
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mii_receive_state,
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mii_receive_state,
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mii_collision_counter; // for normal cols
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mii_collision_counter; // for normal cols
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reg mii_SFD_received;
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reg mii_SFD_received;
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// wire [31:0] event_file;
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// wire [31:0] event_file;
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/* MII port instantiations */
|
/* MII port instantiations */
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/* Comment out unnecessary interfaces to save simulation cycles */
|
/* Comment out unnecessary interfaces to save simulation cycles */
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|
|
tb_mii full_mii(
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tb_mii full_mii(
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.port_type ({port_duplex_status, port_speed[2:0]}),
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.port_type ({port_duplex_status, port_speed[2:0]}),
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.port_tx_enable (MII_port_tx_enable),
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.port_tx_enable (MII_port_tx_enable),
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.port_rx_enable (MII_port_rx_enable),
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.port_rx_enable (MII_port_rx_enable),
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|
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.REFCLK (REFCLK_50_MHz),
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.REFCLK (REFCLK_50_MHz),
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.RXD (MII_RXD),
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.RXD (MII_RXD),
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.RX_CLK (MII_RX_CLK),
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.RX_CLK (MII_RX_CLK),
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.CRS (MII_CRS),
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.CRS (MII_CRS),
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.COL (MII_COL),
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.COL (MII_COL),
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.RX_DV (MII_RX_DV),
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.RX_DV (MII_RX_DV),
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.TXD (MII_TXD),
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.TXD (MII_TXD),
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.TX_EN (MII_TX_EN),
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.TX_EN (MII_TX_EN),
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.TX_CLK (MII_TX_CLK),
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.TX_CLK (MII_TX_CLK),
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.transmit_data_valid (transmit_data_valid),
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.transmit_data_valid (transmit_data_valid),
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.transmit_complete (transmit_done),
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.transmit_complete (transmit_done),
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.receive_data_valid (receive_data_valid),
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.receive_data_valid (receive_data_valid),
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.event_file (event_file)
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.event_file (event_file)
|
);
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);
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tb_rmii reduced_mii(
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tb_rmii reduced_mii(
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.port_type ({port_duplex_status, port_speed[2:0]}),
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.port_type ({port_duplex_status, port_speed[2:0]}),
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.port_tx_enable (RMII_port_tx_enable),
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.port_tx_enable (RMII_port_tx_enable),
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.port_rx_enable (RMII_port_rx_enable),
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.port_rx_enable (RMII_port_rx_enable),
|
|
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.REFCLK (REFCLK_50_MHz),
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.REFCLK (REFCLK_50_MHz),
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.RXD (RMII_RXD),
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.RXD (RMII_RXD),
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.CRS_DV (RMII_CRS_DV),
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.CRS_DV (RMII_CRS_DV),
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.TXD (RMII_TXD),
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.TXD (RMII_TXD),
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.TX_EN (RMII_TX_EN),
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.TX_EN (RMII_TX_EN),
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.transmit_data_valid (transmit_data_valid),
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.transmit_data_valid (transmit_data_valid),
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.transmit_complete (transmit_done),
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.transmit_complete (transmit_done),
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.receive_data_valid (receive_data_valid),
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.receive_data_valid (receive_data_valid),
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.event_file (event_file)
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.event_file (event_file)
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);
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);
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|
|
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integer i;
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integer i;
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|
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initial
|
initial
|
begin
|
begin
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transmit_data_valid = 0;
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transmit_data_valid = 0;
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transmit_packet_count = 0;
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transmit_packet_count = 0;
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receive_data_available =0;
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receive_data_available =0;
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port_mii_type = 3'b111; // set port MII type to invalid
|
port_mii_type = 3'b111; // set port MII type to invalid
|
packets_sent = 0;
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packets_sent = 0;
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transmit_timer_active = 0;
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transmit_timer_active = 0;
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transmit_timer_expired = 0;
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transmit_timer_expired = 0;
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port_tx_busy = 0;
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port_tx_busy = 0;
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user_frame = 0;
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user_frame = 0;
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|
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MII_port_tx_enable = 0;
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MII_port_tx_enable = 0;
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MII_port_rx_enable = 0;
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MII_port_rx_enable = 0;
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RMII_port_tx_enable = 0;
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RMII_port_tx_enable = 0;
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RMII_port_rx_enable = 0;
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RMII_port_rx_enable = 0;
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GMII_port_tx_enable = 0;
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GMII_port_tx_enable = 0;
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GMII_port_rx_enable = 0;
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GMII_port_rx_enable = 0;
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SMII_port_tx_enable = 0;
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SMII_port_tx_enable = 0;
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SMII_port_rx_enable = 0;
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SMII_port_rx_enable = 0;
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SERDES_tx_enable = 0;
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SERDES_tx_enable = 0;
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SERDES_rx_enable = 0;
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SERDES_rx_enable = 0;
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custom_tx_enable = 0;
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custom_tx_enable = 0;
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custom_rx_enable = 0;
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custom_rx_enable = 0;
|
|
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seqno_enable = 0; // do not insert sequence numbers in transmitted pkts
|
seqno_enable = 0; // do not insert sequence numbers in transmitted pkts
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timestamp_enable = 0; // do not insert timestamps
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timestamp_enable = 0; // do not insert timestamps
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packet_seq_no = 0; // initialize sequence number
|
packet_seq_no = 0; // initialize sequence number
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L3_sequence_number = 0; // initialize IP sequence number
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L3_sequence_number = 0; // initialize IP sequence number
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flow_type = 0; // default = Layer-2 unicast
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flow_type = 0; // default = Layer-2 unicast
|
|
|
user_crc_option = 0; // enable CRC insertion for user frames, good CRC
|
user_crc_option = 0; // enable CRC insertion for user frames, good CRC
|
user_crc_value = 0; // defaulr for user_generated CRC
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user_crc_value = 0; // defaulr for user_generated CRC
|
|
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// set default backoff parameters
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// set default backoff parameters
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collision_limit = 16;
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collision_limit = 16;
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backoff_slots[1] = 32'd2;
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backoff_slots[1] = 32'd2;
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backoff_type[1] = 1; // random backoff
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backoff_type[1] = 1; // random backoff
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for (i=2; i <= `MAX_COLLISIONS; i=i+1)
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for (i=2; i <= `MAX_COLLISIONS; i=i+1)
|
begin
|
begin
|
backoff_slots[i] = backoff_slots[i-1] *2;
|
backoff_slots[i] = backoff_slots[i-1] *2;
|
if (backoff_slots[i] > 1024)
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if (backoff_slots[i] > 1024)
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backoff_slots[i] = 1024; // clamp at 1024 slots
|
backoff_slots[i] = 1024; // clamp at 1024 slots
|
backoff_type[i] = 1; // random backoff
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backoff_type[i] = 1; // random backoff
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end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
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end // for (i=2; i <= `MAX_COLLISIONS; i=i+1)
|
|
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set_default_header_parameters; // initialize headers to default patterns
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set_default_header_parameters; // initialize headers to default patterns
|
//outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
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//outfile = $fopen(`PARAM_LOG_FILENAME); // open parameter log
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// while (1)
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// while (1)
|
// begin
|
// begin
|
// #20;
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// #20;
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// event_file = "eth_events_log"; // open event log
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// event_file = "eth_events_log"; // open event log
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// #20;
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// #20;
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// end
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// end
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end // initial begin
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end // initial begin
|
|
|
|
|
|
|
`include "tb_eth_tasks.v"
|
`include "tb_eth_tasks.v"
|
|
|
//Generate a 1MHz clock for generating transmit timeout
|
//Generate a 1MHz clock for generating transmit timeout
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reg clock_1_MHz;
|
reg clock_1_MHz;
|
integer clk_cnt_1_MHz;
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integer clk_cnt_1_MHz;
|
|
|
initial
|
initial
|
begin
|
begin
|
clock_1_MHz = 0;
|
clock_1_MHz = 0;
|
clk_cnt_1_MHz = 0;
|
clk_cnt_1_MHz = 0;
|
end // initial begin
|
end // initial begin
|
|
|
always @(posedge REFCLK_50_MHz)
|
always @(posedge REFCLK_50_MHz)
|
begin
|
begin
|
if (clk_cnt_1_MHz == 24)
|
if (clk_cnt_1_MHz == 24)
|
begin
|
begin
|
clock_1_MHz = ~clock_1_MHz;
|
clock_1_MHz = ~clock_1_MHz;
|
clk_cnt_1_MHz = 0;
|
clk_cnt_1_MHz = 0;
|
end
|
end
|
else
|
else
|
clk_cnt_1_MHz = clk_cnt_1_MHz +1;
|
clk_cnt_1_MHz = clk_cnt_1_MHz +1;
|
end
|
end
|
|
|
//Transmit timeout
|
//Transmit timeout
|
always @(posedge clock_1_MHz)
|
always @(posedge clock_1_MHz)
|
if (transmit_timer_active)
|
if (transmit_timer_active)
|
begin
|
begin
|
transmit_timer = transmit_timer -1;
|
transmit_timer = transmit_timer -1;
|
if (transmit_timer == 0)
|
if (transmit_timer == 0)
|
begin
|
begin
|
$display("%t ns: Testbench transmit timer timed out", $time);
|
$display("%t ns: Testbench transmit timer timed out", $time);
|
if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
|
if (`TERMINATE_ON_TRANSMIT_TIMEOUT)
|
$finish;
|
$finish;
|
transmit_timer_expired= 1;
|
transmit_timer_expired= 1;
|
transmit_timer_active = 0;
|
transmit_timer_active = 0;
|
end // if (transmit_timer == 0)
|
end // if (transmit_timer == 0)
|
end // if (transmit_timer_active)
|
end // if (transmit_timer_active)
|
|
|
// Main transmit loop
|
// Main transmit loop
|
always @(posedge REFCLK_50_MHz)
|
always @(posedge REFCLK_50_MHz)
|
if ((port_tx_busy == 1) &&
|
if ((port_tx_busy == 1) &&
|
((port_speed == 0) || (port_speed == 1)))
|
((port_speed == 0) || (port_speed == 1)))
|
//only for 10 and 100 Mb ports
|
//only for 10 and 100 Mb ports
|
begin: main_transmit_block
|
begin: main_transmit_block
|
integer delay, i;
|
integer delay, i;
|
|
|
if (!user_frame)
|
if (!user_frame)
|
construct_frame;
|
construct_frame;
|
transmit_data_valid= 1; // send signal to MII to transmit
|
transmit_data_valid= 1; // send signal to MII to transmit
|
@(posedge REFCLK_50_MHz)
|
@(posedge REFCLK_50_MHz)
|
transmit_data_valid = 0;
|
transmit_data_valid = 0;
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wait(transmit_done);
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wait(transmit_done);
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packets_sent = packets_sent +1;
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packets_sent = packets_sent +1;
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packet_seq_no = packet_seq_no +1; // increment sequence number;
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packet_seq_no = packet_seq_no +1; // increment sequence number;
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// update fields for next packet
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// update fields for next packet
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if (!user_frame)
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if (!user_frame)
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update_header_parameters;
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update_header_parameters;
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if ((packets_sent >= transmit_packet_count) ||
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if ((packets_sent >= transmit_packet_count) ||
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(transmit_timer_expired)) // transmit no more packets
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(transmit_timer_expired)) // transmit no more packets
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port_tx_busy = 0;
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port_tx_busy = 0;
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else
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else
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begin
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begin
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// wait for inter-packet spacing
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// wait for inter-packet spacing
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delay = current_ifg - port_min_ifg; // delay in bit times
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delay = current_ifg - port_min_ifg; // delay in bit times
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case(port_speed)
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case(port_speed)
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0: begin // 10 Mb/s = 100 ns per bit
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0: begin // 10 Mb/s = 100 ns per bit
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for (i = delay*5; i >= 0; i = i-1)
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for (i = delay*5; i >= 0; i = i-1)
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if (!transmit_timer_expired)
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if (!transmit_timer_expired)
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@(posedge REFCLK_50_MHz);
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@(posedge REFCLK_50_MHz);
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end // case: 0
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end // case: 0
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1: begin // 100 Mb/s = 10 ns per bit
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1: begin // 100 Mb/s = 10 ns per bit
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for (i = delay/2; i >= 0; i = i-1)
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for (i = delay/2; i >= 0; i = i-1)
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if (!transmit_timer_expired)
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if (!transmit_timer_expired)
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@(posedge REFCLK_50_MHz);
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@(posedge REFCLK_50_MHz);
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end // case: 1
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end // case: 1
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default: begin // we shouldn't get here
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default: begin // we shouldn't get here
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end // case: default
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end // case: default
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endcase // case(port_speed)
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endcase // case(port_speed)
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if (transmit_timer_expired)
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if (transmit_timer_expired)
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port_tx_busy = 0;
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port_tx_busy = 0;
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end // else: !if((packets_sent >= transmit_packet_count) ||...
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end // else: !if((packets_sent >= transmit_packet_count) ||...
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end // block: main_transmit_block
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end // block: main_transmit_block
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// Main loop for gigabit port
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// Main loop for gigabit port
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always @(posedge REFCLK_125_MHz)
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always @(posedge REFCLK_125_MHz)
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if ((port_tx_busy == 1) &&
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if ((port_tx_busy == 1) &&
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(port_speed == 2))
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(port_speed == 2))
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begin: main_transmit_block_gigabit
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begin: main_transmit_block_gigabit
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integer delay, i;
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integer delay, i;
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|
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if (!user_frame)
|
if (!user_frame)
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construct_frame;
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construct_frame;
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transmit_data_valid= 1; // send signal to MII to transmit
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transmit_data_valid= 1; // send signal to MII to transmit
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@(posedge REFCLK_125_MHz)
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@(posedge REFCLK_125_MHz)
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transmit_data_valid = 0;
|
transmit_data_valid = 0;
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wait(transmit_done);
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wait(transmit_done);
|
|
|
packets_sent = packets_sent +1;
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packets_sent = packets_sent +1;
|
packet_seq_no = packet_seq_no +1; // increment sequence number;
|
packet_seq_no = packet_seq_no +1; // increment sequence number;
|
|
|
// update fields for next packet
|
// update fields for next packet
|
if (!user_frame)
|
if (!user_frame)
|
update_header_parameters;
|
update_header_parameters;
|
if ((packets_sent >= transmit_packet_count) ||
|
if ((packets_sent >= transmit_packet_count) ||
|
(transmit_timer_expired)) // transmit no more packets
|
(transmit_timer_expired)) // transmit no more packets
|
port_tx_busy = 0;
|
port_tx_busy = 0;
|
else
|
else
|
begin
|
begin
|
// wait for inter-packet spacing
|
// wait for inter-packet spacing
|
delay = current_ifg - port_min_ifg; // delay in bit times
|
delay = current_ifg - port_min_ifg; // delay in bit times
|
for (i = delay/8; i >= 0; i = i-1)
|
for (i = delay/8; i >= 0; i = i-1)
|
if (!transmit_timer_expired)
|
if (!transmit_timer_expired)
|
@(posedge REFCLK_125_MHz);
|
@(posedge REFCLK_125_MHz);
|
|
|
if (transmit_timer_expired)
|
if (transmit_timer_expired)
|
port_tx_busy = 0;
|
port_tx_busy = 0;
|
end // else: !if((packets_sent >= transmit_packet_count) ||...
|
end // else: !if((packets_sent >= transmit_packet_count) ||...
|
end // block: main_transmit_block_gigabit
|
end // block: main_transmit_block_gigabit
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`include "tb_eth_pktgn.v" // packet generation tasks
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`include "tb_eth_pktgn.v" // packet generation tasks
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endmodule // testbench
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endmodule // testbench
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