// Author: Mehdi SEBBANE
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// Author: Mehdi SEBBANE
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// May 2002
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// May 2002
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// Verilog model
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// Verilog model
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// project: M25P20 25 MHz,
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// project: M25P20 25 MHz,
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// release: 1.4.1
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// release: 1.4.1
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// These Verilog HDL models are provided "as is" without warranty
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// These Verilog HDL models are provided "as is" without warranty
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// of any kind, included but not limited to, implied warranty
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// of any kind, included but not limited to, implied warranty
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// of merchantability and fitness for a particular purpose.
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// of merchantability and fitness for a particular purpose.
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`timescale 1ns/1ns
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`ifdef SFLASH_SPDUP
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`ifdef SFLASH_SPDUP
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`include "parameter_fast.v"
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`include "parameter_fast.v"
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`else
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`else
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`include "parameter.v"
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`include "parameter.v"
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`endif
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`endif
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module m25p20(c,data_in,s,w,hold,data_out);
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module m25p20(c,data_in,s,w,hold,data_out);
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input c;
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input c;
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input data_in;
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input data_in;
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input s;
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input s;
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input w;
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input w;
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input hold;
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input hold;
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output data_out;
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output data_out;
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///reg data_out;
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///reg data_out;
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wire [(`NB_BIT_ADD_MEM-1):0] adresse;
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wire [(`NB_BIT_ADD_MEM-1):0] adresse;
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wire [(`NB_BIT_DATA-1):0] dtr;
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wire [(`NB_BIT_DATA-1):0] dtr;
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wire [(`NB_BIT_DATA-1):0] data_to_write;
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wire [(`NB_BIT_DATA-1):0] data_to_write;
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wire [(`LSB_TO_CODE_PAGE-1):0] page_index;
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wire [(`LSB_TO_CODE_PAGE-1):0] page_index;
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wire wr_op;
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wire wr_op;
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wire rd_op;
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wire rd_op;
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wire s_en;
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wire s_en;
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wire b_en;
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wire b_en;
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wire add_pp_en;
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wire add_pp_en;
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wire pp_en;
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wire pp_en;
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wire r_en;
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wire r_en;
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wire d_req;
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wire d_req;
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wire clck;
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wire clck;
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assign clck = c ;
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assign clck = c ;
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memory_access mem_access(adresse, b_en, s_en, add_pp_en, pp_en, r_en, d_req, data_to_write, page_index, dtr);
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memory_access mem_access(adresse, b_en, s_en, add_pp_en, pp_en, r_en, d_req, data_to_write, page_index, dtr);
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acdc_check acdc_watch(clck, data_in, s, hold, wr_op, rd_op);
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acdc_check acdc_watch(clck, data_in, s, hold, wr_op, rd_op);
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internal_logic spi_decoder(clck, data_in, w, s, hold, dtr, data_out, data_to_write, page_index, adresse, wr_op, rd_op, b_en, s_en, add_pp_en, pp_en, r_en, d_req);
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internal_logic spi_decoder(clck, data_in, w, s, hold, dtr, data_out, data_to_write, page_index, adresse, wr_op, rd_op, b_en, s_en, add_pp_en, pp_en, r_en, d_req);
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endmodule
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endmodule
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