// Author: Mehdi SEBBANE
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// Author: Mehdi SEBBANE
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// May 2002
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// May 2002
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// Verilog model
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// Verilog model
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// project: M25P20 25 MHz,
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// project: M25P20 25 MHz,
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// release: 1.4.1
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// release: 1.4.1
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// These Verilog HDL models are provided "as is" without warranty
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// These Verilog HDL models are provided "as is" without warranty
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// of any kind, included but not limited to, implied warranty
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// of any kind, included but not limited to, implied warranty
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// of merchantability and fitness for a particular purpose.
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// of merchantability and fitness for a particular purpose.
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`timescale 1ns/1ns
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`ifdef SFLASH_SPDUP
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`ifdef SFLASH_SPDUP
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`include "parameter_fast.v"
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`include "parameter_fast.v"
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`else
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`else
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`include "parameter.v"
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`include "parameter.v"
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`endif
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`endif
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module internal_logic (c, d, w, s, hold, data_to_read, q, data_to_write, page_add_index, add_mem, write_op, read_op, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request);
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module internal_logic (c, d, w, s, hold, data_to_read, q, data_to_write, page_add_index, add_mem, write_op, read_op, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request);
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////////////////////////////////
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////////////////////////////////
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// declaration of the parameters
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// declaration of the parameters
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////////////////////////////////
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////////////////////////////////
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input c;
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input c;
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input d;
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input d;
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input w;
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input w;
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input s;
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input s;
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input hold;
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input hold;
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input[(`NB_BIT_DATA - 1):0] data_to_read;
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input[(`NB_BIT_DATA - 1):0] data_to_read;
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output q;
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output q;
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reg q;
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reg q;
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output[(`NB_BIT_DATA - 1):0] data_to_write;
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output[(`NB_BIT_DATA - 1):0] data_to_write;
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reg[(`NB_BIT_DATA - 1):0] data_to_write;
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reg[(`NB_BIT_DATA - 1):0] data_to_write;
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output[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; // position to write data_to_write inside the page
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output[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; // position to write data_to_write inside the page
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reg[(`LSB_TO_CODE_PAGE - 1):0] page_add_index;
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reg[(`LSB_TO_CODE_PAGE - 1):0] page_add_index;
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output[(`NB_BIT_ADD_MEM - 1):0] add_mem;
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output[(`NB_BIT_ADD_MEM - 1):0] add_mem;
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reg[(`NB_BIT_ADD_MEM - 1):0] add_mem;
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reg[(`NB_BIT_ADD_MEM - 1):0] add_mem;
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output write_op;
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output write_op;
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reg write_op;
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reg write_op;
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output read_op;
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output read_op;
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reg read_op;
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reg read_op;
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output be_enable;
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output be_enable;
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reg be_enable;
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reg be_enable;
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output se_enable;
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output se_enable;
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reg se_enable;
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reg se_enable;
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output add_pp_enable;
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output add_pp_enable;
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reg add_pp_enable;
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reg add_pp_enable;
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output pp_enable;
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output pp_enable;
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reg pp_enable;
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reg pp_enable;
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output read_enable;
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output read_enable;
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reg read_enable;
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reg read_enable;
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output data_request;
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output data_request;
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reg data_request;
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reg data_request;
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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// declaration of internal variables
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// declaration of internal variables
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///////////////////////////////////////////////
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///////////////////////////////////////////////
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reg only_rdsr;
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reg only_rdsr;
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reg only_res;
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reg only_res;
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reg write_protect;
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reg write_protect;
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reg select_ok;
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reg select_ok;
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reg raz;
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reg raz;
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reg byte_ok;
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reg byte_ok;
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reg wren;
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reg wren;
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reg wrdi;
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reg wrdi;
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reg rdsr;
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reg rdsr;
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reg wrsr;
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reg wrsr;
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reg read_data;
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reg read_data;
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reg fast_read;
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reg fast_read;
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reg pp;
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reg pp;
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reg se;
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reg se;
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reg be;
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reg be;
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reg dp;
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reg dp;
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reg res;
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reg res;
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reg q_bis;
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reg q_bis;
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reg protect;
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reg protect;
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reg wr_cycle;
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reg wr_cycle;
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reg hold_cond;
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reg hold_cond;
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reg inhib_wren;
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reg inhib_wren;
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reg inhib_wrdi;
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reg inhib_wrdi;
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reg inhib_rdsr;
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reg inhib_rdsr;
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reg inhib_wrsr;
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reg inhib_wrsr;
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reg inhib_read;
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reg inhib_read;
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reg inhib_pp;
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reg inhib_pp;
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reg inhib_se;
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reg inhib_se;
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reg inhib_be;
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reg inhib_be;
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reg inhib_dp;
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reg inhib_dp;
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reg inhib_res;
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reg inhib_res;
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reg reset_wel;
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reg reset_wel;
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reg wel;
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reg wel;
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reg wip;
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reg wip;
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reg c_int;
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reg c_int;
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reg [2:0] cpt;
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reg [2:0] cpt;
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reg [2:0] bit_index; // to allow shift inside a byte
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reg [2:0] bit_index; // to allow shift inside a byte
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reg [2:0] bit_res; // to allow shift inside signature
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reg [2:0] bit_res; // to allow shift inside signature
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reg [2:0] bit_register; // to allow shift inside status register
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reg [2:0] bit_register; // to allow shift inside status register
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reg [7:0] data;
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reg [7:0] data;
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reg [7:0] adress_1;
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reg [7:0] adress_1;
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reg [7:0] adress_2;
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reg [7:0] adress_2;
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reg [7:0] adress_3;
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reg [7:0] adress_3;
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reg [7:0] sr_mask;
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reg [7:0] sr_mask;
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reg [7:0] signature;
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reg [7:0] signature;
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reg [(`NB_BIT_DATA-1):0] wr_latch;
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reg [(`NB_BIT_DATA-1):0] wr_latch;
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reg [(`NB_BIT_DATA-1):0] page_ini;
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reg [(`NB_BIT_DATA-1):0] page_ini;
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reg [(`NB_BIT_DATA-1):0] data_latch;
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reg [(`NB_BIT_DATA-1):0] data_latch;
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reg [(`NB_BIT_DATA-1):0] register_bis;
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reg [(`NB_BIT_DATA-1):0] register_bis;
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reg [(`NB_BIT_DATA-1):0] register_temp;
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reg [(`NB_BIT_DATA-1):0] register_temp;
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reg [(`NB_BIT_DATA-1):0] status_register;
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reg [(`NB_BIT_DATA-1):0] status_register;
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reg [(`NB_BPI-1):0] bp;
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reg [(`NB_BPI-1):0] bp;
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reg [(`NB_BIT_ADD_MEM-1):0] adress;
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reg [(`NB_BIT_ADD_MEM-1):0] adress;
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reg [(`BIT_TO_CODE_MEM-1):0] cut_add;
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reg [(`BIT_TO_CODE_MEM-1):0] cut_add;
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reg [(`LSB_TO_CODE_PAGE -1) :0] lsb_adress;
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reg [(`LSB_TO_CODE_PAGE -1) :0] lsb_adress;
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integer byte_cpt;
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integer byte_cpt;
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integer int_add;
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integer int_add;
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integer i;
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integer i;
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integer count_enable;
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integer count_enable;
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time t_only_res ;
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time t_only_res ;
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initial
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initial
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begin
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begin
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////////////////////////////////////////////
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////////////////////////////////////////////
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// Initialization of the internal variables
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// Initialization of the internal variables
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////////////////////////////////////////////
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////////////////////////////////////////////
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only_rdsr = `FALSE;
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only_rdsr = `FALSE;
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only_res = `FALSE;
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only_res = `FALSE;
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write_protect = `FALSE;
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write_protect = `FALSE;
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select_ok = `FALSE;
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select_ok = `FALSE;
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raz = `FALSE;
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raz = `FALSE;
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byte_ok = `FALSE;
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byte_ok = `FALSE;
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cpt = 0;
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cpt = 0;
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byte_cpt = 0;
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byte_cpt = 0;
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data_to_write = 8'bxxxxxxxx;
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data_to_write = 8'bxxxxxxxx;
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data_latch = 8'bxxxxxxxx;
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data_latch = 8'bxxxxxxxx;
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data_request <= `FALSE;
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data_request <= `FALSE;
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wren = `FALSE;
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wren = `FALSE;
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wrdi = `FALSE;
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wrdi = `FALSE;
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rdsr = `FALSE;
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rdsr = `FALSE;
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wrsr = `FALSE;
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wrsr = `FALSE;
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read_data = `FALSE;
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read_data = `FALSE;
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fast_read = `FALSE;
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fast_read = `FALSE;
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pp = `FALSE;
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pp = `FALSE;
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se = `FALSE;
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se = `FALSE;
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be = `FALSE;
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be = `FALSE;
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dp = `FALSE;
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dp = `FALSE;
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res = `FALSE;
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res = `FALSE;
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q_bis = 1'bz;
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q_bis = 1'bz;
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register_bis = 8'b00000000;
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register_bis = 8'b00000000;
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wr_latch = 8'b00000000;
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wr_latch = 8'b00000000;
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protect = `FALSE;
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protect = `FALSE;
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wr_cycle = `FALSE;
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wr_cycle = `FALSE;
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hold_cond = `FALSE;
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hold_cond = `FALSE;
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write_op = `FALSE;
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write_op = `FALSE;
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read_op = `FALSE;
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read_op = `FALSE;
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inhib_wren = `FALSE;
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inhib_wren = `FALSE;
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inhib_wrdi = `FALSE;
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inhib_wrdi = `FALSE;
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inhib_rdsr = `FALSE;
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inhib_rdsr = `FALSE;
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inhib_wrsr = `FALSE;
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inhib_wrsr = `FALSE;
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inhib_read = `FALSE;
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inhib_read = `FALSE;
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inhib_pp = `FALSE;
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inhib_pp = `FALSE;
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inhib_se = `FALSE;
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inhib_se = `FALSE;
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inhib_be = `FALSE;
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inhib_be = `FALSE;
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inhib_dp = `FALSE;
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inhib_dp = `FALSE;
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inhib_res = `FALSE;
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inhib_res = `FALSE;
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add_pp_enable = `FALSE;
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add_pp_enable = `FALSE;
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read_enable = `FALSE;
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read_enable = `FALSE;
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pp_enable = `FALSE;
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pp_enable = `FALSE;
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be_enable = `FALSE;
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be_enable = `FALSE;
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se_enable = `FALSE;
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se_enable = `FALSE;
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count_enable = `FALSE;
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count_enable = `FALSE;
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data = 8'b00000000;
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data = 8'b00000000;
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// decode process
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// decode process
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bit_index = 8'b00000000;
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bit_index = 8'b00000000;
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bit_res = 8'b00000000;
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bit_res = 8'b00000000;
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bit_register = 8'b00000000;
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bit_register = 8'b00000000;
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bp = `NB_BPI'h0 ;
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bp = `NB_BPI'h0 ;
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int_add = 0;
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int_add = 0;
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sr_mask = 8'b10000000;
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sr_mask = 8'b10000000;
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page_ini = 8'b11111111;
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page_ini = 8'b11111111;
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reset_wel = 1'b0;
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reset_wel = 1'b0;
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wel = 1'b0;
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wel = 1'b0;
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wip = 1'b0;
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wip = 1'b0;
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signature = `SIGNATURE ;
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signature = `SIGNATURE ;
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end // initial
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end // initial
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always @(register_bis) status_register = register_bis ;
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always @(register_bis) status_register = register_bis ;
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//assign status_register = register_bis ; // Continuous Assignment
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//assign status_register = register_bis ; // Continuous Assignment
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//-----------------------------------------------------------
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//-----------------------------------------------------------
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// This process generates the Hold condition when it is valid
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// This process generates the Hold condition when it is valid
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always
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always
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begin : hold_com
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begin : hold_com
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@(hold);
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@(hold);
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begin
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begin
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if ((hold == 1'b0) && (s == 1'b0))
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if ((hold == 1'b0) && (s == 1'b0))
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begin
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begin
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if (c == 1'b0)
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if (c == 1'b0)
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begin
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begin
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hold_cond <= `TRUE;
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hold_cond <= `TRUE;
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if ($time != 0) $display("NOTE: COMMUNICATION PAUSED");
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if ($time != 0) $display("NOTE: COMMUNICATION PAUSED");
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end
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end
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else
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else
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begin
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begin
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@(c or hold);
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@(c or hold);
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if (c == 1'b0)
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if (c == 1'b0)
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begin
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begin
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hold_cond <= `TRUE;
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hold_cond <= `TRUE;
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if ($time != 0) $display("NOTE: COMMUNICATION PAUSED");
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if ($time != 0) $display("NOTE: COMMUNICATION PAUSED");
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end
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end
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end
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end
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end
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end
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else if (hold == 1'b1)
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else if (hold == 1'b1)
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begin
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begin
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if (c == 1'b0)
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if (c == 1'b0)
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begin
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begin
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hold_cond <= `FALSE;
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hold_cond <= `FALSE;
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if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED");
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if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED");
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end
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end
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else
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else
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begin
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begin
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@(c or hold);
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@(c or hold);
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if (c == 1'b0)
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if (c == 1'b0)
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begin
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begin
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hold_cond <= `FALSE;
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hold_cond <= `FALSE;
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if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED");
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if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED");
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// This process inhibits the internal clock when hold condition is valid
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// This process inhibits the internal clock when hold condition is valid
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always
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always
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begin : horloge
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begin : horloge
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@(c);
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@(c);
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begin
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begin
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if (!hold_cond)
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if (!hold_cond)
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begin
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begin
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c_int <= c ;
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c_int <= c ;
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end
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end
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else
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else
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begin
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begin
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c_int <= 1'b0 ;
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c_int <= 1'b0 ;
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end
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end
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end
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end
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end
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end
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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// This process inhibits data output when hold condition is valid
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// This process inhibits data output when hold condition is valid
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always @(posedge hold_cond ) q <= #`THLQZ 1'bz ;
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always @(posedge hold_cond ) q <= #`THLQZ 1'bz ;
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always @(negedge hold_cond) q <= #`THHQX q_bis ;
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always @(negedge hold_cond) q <= #`THHQX q_bis ;
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always @ (q_bis or s)
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always @ (q_bis or s)
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if (!hold_cond)
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if (!hold_cond)
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begin
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begin
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q <= q_bis ;
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q <= q_bis ;
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end
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end
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//----------------------------------------------------------
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//----------------------------------------------------------
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// This process increments 2 counters: one bit counter (cpt)
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// This process increments 2 counters: one bit counter (cpt)
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// one byte counter (byte_cpt)
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// one byte counter (byte_cpt)
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always
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always
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begin : count_bit_raz
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begin : count_bit_raz
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@(raz);
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@(raz);
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begin
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begin
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if (raz || !select_ok)
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if (raz || !select_ok)
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begin
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begin
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cpt <= 0 ;
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cpt <= 0 ;
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byte_cpt <= 0 ;
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byte_cpt <= 0 ;
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count_enable = `FALSE;
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count_enable = `FALSE;
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end
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end
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end
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end
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end
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end
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always
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always
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begin : count_bit_enable
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begin : count_bit_enable
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@(posedge c_int or negedge raz);
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@(posedge c_int or negedge raz);
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begin
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begin
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if (!raz && select_ok)
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if (!raz && select_ok)
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begin
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begin
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// count enable is an intermediate variable which allows cpt to be
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// count enable is an intermediate variable which allows cpt to be
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// constant during a whole period
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// constant during a whole period
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count_enable = `TRUE;
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count_enable = `TRUE;
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end
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end
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end
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end
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end
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end
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always
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always
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begin : count_bit
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begin : count_bit
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@(negedge c_int);
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@(negedge c_int);
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begin
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begin
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if (!raz && select_ok)
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if (!raz && select_ok)
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begin
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begin
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if (count_enable)
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if (count_enable)
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begin
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begin
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cpt <= cpt + 1 ;
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cpt <= cpt + 1 ;
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end
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end
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end
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end
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end
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end
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end
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end
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always @(negedge c_int)
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always @(negedge c_int)
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if (byte_ok)
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if (byte_ok)
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begin
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begin
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//byte_cpt = (byte_cpt + 1) ;
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//byte_cpt = (byte_cpt + 1) ;
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byte_cpt <= (byte_cpt + 1) ;
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byte_cpt <= (byte_cpt + 1) ;
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end
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end
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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// This process latches every byte of data received and returns byte_ok
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// This process latches every byte of data received and returns byte_ok
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always
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always
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begin : data_in_reset
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begin : data_in_reset
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@(c_int or select_ok);
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@(c_int or select_ok);
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begin
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begin
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if (!select_ok)
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if (!select_ok)
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begin
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begin
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raz <= `TRUE ;
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raz <= `TRUE ;
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byte_ok <= `FALSE ;
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byte_ok <= `FALSE ;
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data_latch <= 8'b00000000 ;
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data_latch <= 8'b00000000 ;
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data = 8'b00000000;
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data = 8'b00000000;
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end
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end
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end
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end
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end
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end
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always
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always
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begin : data_in
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begin : data_in
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@(posedge c_int);
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@(posedge c_int);
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begin
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begin
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if (select_ok)
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if (select_ok)
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begin
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begin
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raz <= `FALSE ;
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raz <= `FALSE ;
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if (cpt == 0)
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if (cpt == 0)
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begin
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begin
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data_latch <= 8'b00000000 ;
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data_latch <= 8'b00000000 ;
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byte_ok <= `FALSE ;
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byte_ok <= `FALSE ;
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end
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end
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data[7 - cpt] = d;
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data[7 - cpt] = d;
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if (cpt == 7)
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if (cpt == 7)
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begin
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begin
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byte_ok <= `TRUE ;
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byte_ok <= `TRUE ;
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data_latch <= data ;
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data_latch <= data ;
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end
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end
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else data_latch <= 8'bxxxxxxxx;
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else data_latch <= 8'bxxxxxxxx;
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end
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end
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end
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end
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end
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end
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//-------------------------------------------------------------
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//-------------------------------------------------------------
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//--------------- ASYNCHRONOUS DECODE PROCESS -----------------
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//--------------- ASYNCHRONOUS DECODE PROCESS -----------------
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//-------------------------------------------------------------
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//-------------------------------------------------------------
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always
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always
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begin : decode
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begin : decode
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//-------------------------
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//-------------------------
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// status register mask ini
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// status register mask ini
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//-------------------------
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//-------------------------
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for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
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for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
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begin
|
begin
|
sr_mask[i + 2] = 1'b1;
|
sr_mask[i + 2] = 1'b1;
|
end
|
end
|
|
|
|
|
@(byte_ok);
|
@(byte_ok);
|
if (byte_ok == 1'b1)
|
if (byte_ok == 1'b1)
|
begin
|
begin
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
//-- op_code decode
|
//-- op_code decode
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
if (byte_cpt == 0)
|
if (byte_cpt == 0)
|
begin
|
begin
|
if (data_latch == 8'b00000110)
|
if (data_latch == 8'b00000110)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR :This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR :This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wren <= `TRUE ;
|
wren <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00000100)
|
else if (data_latch == 8'b00000100)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wrdi <= `TRUE ;
|
wrdi <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00000101)
|
else if (data_latch == 8'b00000101)
|
begin
|
begin
|
if (only_res)
|
if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rdsr <= `TRUE ;
|
rdsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00000001)
|
else if (data_latch == 8'b00000001)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wrsr <= `TRUE ;
|
wrsr <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00000011)
|
else if (data_latch == 8'b00000011)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
read_data <= `TRUE ;
|
read_data <= `TRUE ;
|
read_op <= `TRUE ;
|
read_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00001011)
|
else if (data_latch == 8'b00001011)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
fast_read <= `TRUE ;
|
fast_read <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b00000010)
|
else if (data_latch == 8'b00000010)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
pp <= `TRUE ;
|
pp <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b11011000)
|
else if (data_latch == 8'b11011000)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
se <= `TRUE ;
|
se <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b11000111)
|
else if (data_latch == 8'b11000111)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
be <= `TRUE ;
|
be <= `TRUE ;
|
write_op <= `TRUE ;
|
write_op <= `TRUE ;
|
for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
|
for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
|
begin
|
begin
|
bp[i] = status_register[i + 2];
|
bp[i] = status_register[i + 2];
|
end
|
end
|
if (bp != 2'b00)
|
if (bp != 2'b00)
|
begin
|
begin
|
protect <= `TRUE ;
|
protect <= `TRUE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b10111001)
|
else if (data_latch == 8'b10111001)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else if (only_res)
|
else if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dp <= `TRUE ;
|
dp <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if (data_latch == 8'b10101011)
|
else if (data_latch == 8'b10101011)
|
begin
|
begin
|
if (only_rdsr)
|
if (only_rdsr)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle ");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
res <= `TRUE ;
|
res <= `TRUE ;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ($time != 0) $display("ERROR : False instruction, please retry ");
|
if ($time != 0) $display("ERROR : False instruction, please retry ");
|
end
|
end
|
end
|
end
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
// addresses and data reception and treatment
|
// addresses and data reception and treatment
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
if ( (byte_cpt == 1) && (!only_rdsr) && (!only_res))
|
if ( (byte_cpt == 1) && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
begin
|
begin
|
adress_1 = data_latch;
|
adress_1 = data_latch;
|
end
|
end
|
else if (wrsr && (!rdsr))
|
else if (wrsr && (!rdsr))
|
begin
|
begin
|
wr_latch <= data_latch ;
|
wr_latch <= data_latch ;
|
end
|
end
|
end
|
end
|
|
|
if ((byte_cpt == 2) && (!only_rdsr) && (!only_res))
|
if ((byte_cpt == 2) && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
begin
|
begin
|
adress_2 = data_latch;
|
adress_2 = data_latch;
|
end
|
end
|
end
|
end
|
if ((byte_cpt == 3) && (!only_rdsr) && (!only_res))
|
if ((byte_cpt == 3) && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr))
|
begin
|
begin
|
adress_3 = data_latch;
|
adress_3 = data_latch;
|
for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
|
for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
|
begin
|
begin
|
adress[i] = adress_3[i];
|
adress[i] = adress_3[i];
|
adress[i + `NB_BIT_ADD] = adress_2[i];
|
adress[i + `NB_BIT_ADD] = adress_2[i];
|
adress[i + 2 * `NB_BIT_ADD] = adress_1[i];
|
adress[i + 2 * `NB_BIT_ADD] = adress_1[i];
|
add_mem <= adress ;
|
add_mem <= adress ;
|
end
|
end
|
for(i = (`LSB_TO_CODE_PAGE - 1); i >= 0; i = i - 1)
|
for(i = (`LSB_TO_CODE_PAGE - 1); i >= 0; i = i - 1)
|
begin
|
begin
|
lsb_adress[i] = adress[i];
|
lsb_adress[i] = adress[i];
|
end
|
end
|
end
|
end
|
if ((se || pp) && (!rdsr))
|
if ((se || pp) && (!rdsr))
|
begin
|
begin
|
//-----------------------------------------
|
//-----------------------------------------
|
// To ignore don't care MSB of the adress
|
// To ignore don't care MSB of the adress
|
//-----------------------------------------
|
//-----------------------------------------
|
for(i = 0; i <= `BIT_TO_CODE_MEM -1; i = i + 1)
|
for(i = 0; i <= `BIT_TO_CODE_MEM -1; i = i + 1)
|
begin
|
begin
|
cut_add[i] = adress[i];
|
cut_add[i] = adress[i];
|
end
|
end
|
int_add = cut_add;
|
int_add = cut_add;
|
//------------------------------------------------
|
//------------------------------------------------
|
// Sector protection detection
|
// Sector protection detection
|
//------------------------------------------------
|
//------------------------------------------------
|
for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
|
for(i = 0; i <= (`NB_BPI - 1); i = i + 1)
|
begin
|
begin
|
bp[i] = status_register[i + 2];
|
bp[i] = status_register[i + 2];
|
end
|
end
|
if (bp == 2'b11)
|
if (bp == 2'b11)
|
begin
|
begin
|
protect <= `TRUE ;
|
protect <= `TRUE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
else if (bp == 2'b10)
|
else if (bp == 2'b10)
|
begin
|
begin
|
if (int_add >= ((`TOP_MEM + 1) / 2))
|
if (int_add >= ((`TOP_MEM + 1) / 2))
|
begin
|
begin
|
protect <= `TRUE ;
|
protect <= `TRUE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
end
|
end
|
else if (bp == 2'b01)
|
else if (bp == 2'b01)
|
begin
|
begin
|
if (int_add >= ((`TOP_MEM + 1) * 3 / 4))
|
if (int_add >= ((`TOP_MEM + 1) * 3 / 4))
|
begin
|
begin
|
protect <= `TRUE ;
|
protect <= `TRUE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
protect <= `FALSE ;
|
protect <= `FALSE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
//---------------------------------------------------------------------------
|
//---------------------------------------------------------------------------
|
// PAGE PROGRAM
|
// PAGE PROGRAM
|
// The adress's LSBs necessary to code a whole page are converted to a natural
|
// The adress's LSBs necessary to code a whole page are converted to a natural
|
// and used to fullfill the page buffer p_prog the same way as the memory page
|
// and used to fullfill the page buffer p_prog the same way as the memory page
|
// will be fullfilled.
|
// will be fullfilled.
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
if ( (byte_cpt >= 4) && (pp) && (!only_rdsr) && (!rdsr))
|
if ( (byte_cpt >= 4) && (pp) && (!only_rdsr) && (!rdsr))
|
begin
|
begin
|
data_to_write = data_latch ;
|
data_to_write = data_latch ;
|
page_add_index = (byte_cpt - 1 - (`NB_BIT_ADD_MEM / `NB_BIT_ADD) + lsb_adress);
|
page_add_index = (byte_cpt - 1 - (`NB_BIT_ADD_MEM / `NB_BIT_ADD) + lsb_adress);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
data_to_write = 8'bxxxxxxxx;
|
data_to_write = 8'bxxxxxxxx;
|
page_add_index = 8'bxxxxxxxx;
|
page_add_index = 8'bxxxxxxxx;
|
end
|
end
|
|
|
// to launch adress treatment in memory access
|
// to launch adress treatment in memory access
|
if (( read_data && (byte_cpt == 3)) || (fast_read && (byte_cpt == 4)))
|
if (( read_data && (byte_cpt == 3)) || (fast_read && (byte_cpt == 4)))
|
begin
|
begin
|
read_enable <= `TRUE ;
|
read_enable <= `TRUE ;
|
end
|
end
|
// to send a request for the data pointed by the adress
|
// to send a request for the data pointed by the adress
|
if (( read_data && (byte_cpt >= 3)) || ( fast_read && (byte_cpt >= 4)))
|
if (( read_data && (byte_cpt >= 3)) || ( fast_read && (byte_cpt >= 4)))
|
begin
|
begin
|
data_request <= `TRUE ;
|
data_request <= `TRUE ;
|
end
|
end
|
end //(if byte_ok)
|
end //(if byte_ok)
|
end //(process decode)
|
end //(process decode)
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// adresses initialization and reset
|
// adresses initialization and reset
|
//-----------------------------------------
|
//-----------------------------------------
|
always @(posedge select_ok)
|
always @(posedge select_ok)
|
begin
|
begin
|
for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
|
for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1)
|
begin
|
begin
|
adress_1[i] = 1'b0;
|
adress_1[i] = 1'b0;
|
adress_2[i] = 1'b0;
|
adress_2[i] = 1'b0;
|
adress_3[i] = 1'b0;
|
adress_3[i] = 1'b0;
|
end
|
end
|
for(i = 0; i <= (`NB_BIT_ADD_MEM - 1); i = i + 1)
|
for(i = 0; i <= (`NB_BIT_ADD_MEM - 1); i = i + 1)
|
begin
|
begin
|
adress[i] = 1'b0;
|
adress[i] = 1'b0;
|
end
|
end
|
add_mem <= adress ;
|
add_mem <= adress ;
|
end
|
end
|
|
|
|
|
always @(negedge byte_ok)
|
always @(negedge byte_ok)
|
begin
|
begin
|
if ((read_data && (byte_cpt > 3) ) || (fast_read && (byte_cpt > 4) ))
|
if ((read_data && (byte_cpt > 3) ) || (fast_read && (byte_cpt > 4) ))
|
begin
|
begin
|
data_request <= `FALSE ;
|
data_request <= `FALSE ;
|
|
|
end
|
end
|
end
|
end
|
|
|
always @(posedge inhib_read)
|
always @(posedge inhib_read)
|
begin
|
begin
|
read_op <= `FALSE ;
|
read_op <= `FALSE ;
|
read_data <= `FALSE ;
|
read_data <= `FALSE ;
|
fast_read <= `FALSE ;
|
fast_read <= `FALSE ;
|
read_enable <= `FALSE ;
|
read_enable <= `FALSE ;
|
data_request <= `FALSE ;
|
data_request <= `FALSE ;
|
|
|
end
|
end
|
//------------------------------------------------------
|
//------------------------------------------------------
|
// STATUS REGISTER INSTRUCTIONS
|
// STATUS REGISTER INSTRUCTIONS
|
//------------------------------------------------------
|
//------------------------------------------------------
|
// WREN/WRDI instructions
|
// WREN/WRDI instructions
|
//-----------------------
|
//-----------------------
|
always @(posedge wel)
|
always @(posedge wel)
|
begin
|
begin
|
register_bis[1] <= 1'b1 ;
|
register_bis[1] <= 1'b1 ;
|
|
|
end
|
end
|
|
|
always @(posedge inhib_wren)
|
always @(posedge inhib_wren)
|
begin
|
begin
|
wren <= `FALSE ;
|
wren <= `FALSE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
|
|
always @(posedge inhib_wrdi)
|
always @(posedge inhib_wrdi)
|
begin
|
begin
|
wrdi <= `FALSE ;
|
wrdi <= `FALSE ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
end
|
end
|
|
|
//----------------------
|
//----------------------
|
// RESET WEL instruction
|
// RESET WEL instruction
|
//----------------------
|
//----------------------
|
always @(posedge reset_wel)
|
always @(posedge reset_wel)
|
begin
|
begin
|
register_bis[1] <= 1'b0 ;
|
register_bis[1] <= 1'b0 ;
|
end
|
end
|
//-------------------
|
//-------------------
|
// WRSR instructions
|
// WRSR instructions
|
//-------------------
|
//-------------------
|
always @(posedge wr_cycle)
|
always @(posedge wr_cycle)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Write status register cycle has begun ");
|
if ($time != 0) $display("NOTE : Write status register cycle has begun ");
|
register_bis <= ((register_bis) | (8'b00000011)) ;
|
register_bis <= ((register_bis) | (8'b00000011)) ;
|
end
|
end
|
always @(negedge wr_cycle)
|
always @(negedge wr_cycle)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Write status register cycle is finished");
|
if ($time != 0) $display("NOTE : Write status register cycle is finished");
|
register_bis <= ((wr_latch) & sr_mask) ;
|
register_bis <= ((wr_latch) & sr_mask) ;
|
wrsr <= `FALSE ;
|
wrsr <= `FALSE ;
|
end
|
end
|
|
|
always @(posedge inhib_wrsr) wrsr <= `FALSE ;
|
always @(posedge inhib_wrsr) wrsr <= `FALSE ;
|
|
|
always @(negedge wrsr) wr_latch <= 8'b00000000 ;
|
always @(negedge wrsr) wr_latch <= 8'b00000000 ;
|
|
|
//------
|
//------
|
// PROG
|
// PROG
|
//------
|
//------
|
always @(wip)
|
always @(wip)
|
begin
|
begin
|
if (wip == 1'b1)
|
if (wip == 1'b1)
|
begin
|
begin
|
register_bis[0] <= 1'b1 ;
|
register_bis[0] <= 1'b1 ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
register_bis[0] <= 1'b0 ;
|
register_bis[0] <= 1'b0 ;
|
write_op <= `FALSE ;
|
write_op <= `FALSE ;
|
|
|
end
|
end
|
end
|
end
|
//------------------
|
//------------------
|
// rdsr instruction
|
// rdsr instruction
|
//------------------
|
//------------------
|
always @(posedge inhib_rdsr) rdsr <= `FALSE ;
|
always @(posedge inhib_rdsr) rdsr <= `FALSE ;
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
// BULK/SECTOR ERASE INSTRUCTIONS
|
// BULK/SECTOR ERASE INSTRUCTIONS
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
always @(posedge inhib_be)
|
always @(posedge inhib_be)
|
begin
|
begin
|
protect <= `FALSE ;
|
protect <= `FALSE ;
|
be <= `FALSE ;
|
be <= `FALSE ;
|
end
|
end
|
always @(posedge inhib_se)
|
always @(posedge inhib_se)
|
begin
|
begin
|
protect <= `FALSE ;
|
protect <= `FALSE ;
|
se <= `FALSE ;
|
se <= `FALSE ;
|
end
|
end
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
//PAGE PROGRAM INSTRUCTIONS
|
//PAGE PROGRAM INSTRUCTIONS
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
always @(posedge inhib_pp)
|
always @(posedge inhib_pp)
|
begin
|
begin
|
protect <= `FALSE ;
|
protect <= `FALSE ;
|
pp <= `FALSE ;
|
pp <= `FALSE ;
|
end
|
end
|
//----------------------------------------------------------
|
//----------------------------------------------------------
|
// DEEP POWER DOWN
|
// DEEP POWER DOWN
|
// RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE
|
// RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
always @(posedge inhib_dp) dp <= `FALSE ;
|
always @(posedge inhib_dp) dp <= `FALSE ;
|
|
|
always @(posedge inhib_res) res <= `FALSE ;
|
always @(posedge inhib_res) res <= `FALSE ;
|
|
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
//--------------- SYNCHRONOUS PROCESS ----------------
|
//--------------- SYNCHRONOUS PROCESS ----------------
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
wel <= 1'b0 ;
|
wel <= 1'b0 ;
|
reset_wel <= 1'b0 ;
|
reset_wel <= 1'b0 ;
|
end
|
end
|
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// READ_data
|
// READ_data
|
//-------------------------------------------
|
//-------------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
if ((!read_data) && (!fast_read))
|
if ((!read_data) && (!fast_read))
|
begin
|
begin
|
inhib_read <= `FALSE ;
|
inhib_read <= `FALSE ;
|
end
|
end
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && (cpt != 7))) && read_data && (!select_ok))
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && (cpt != 7))) && read_data && (!select_ok))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_read <= `TRUE ;
|
inhib_read <= `TRUE ;
|
bit_index <= 8'b00000000;
|
bit_index <= 8'b00000000;
|
end
|
end
|
if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
|
if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
inhib_read <= `TRUE ;
|
inhib_read <= `TRUE ;
|
bit_index <= 8'b00000000;
|
bit_index <= 8'b00000000;
|
q_bis <= #`TSHQZ 1'bz ;
|
q_bis <= #`TSHQZ 1'bz ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(negedge c_int)
|
@(negedge c_int)
|
begin
|
begin
|
if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
|
if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)))
|
begin
|
begin
|
|
|
if (select_ok)
|
if (select_ok)
|
begin
|
begin
|
q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
|
q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
|
bit_index = bit_index + 1;
|
bit_index = bit_index + 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
// Fast_Read
|
// Fast_Read
|
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && (cpt != 7))) && fast_read && (!select_ok))
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && (cpt != 7))) && fast_read && (!select_ok))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_read <= `TRUE ;
|
inhib_read <= `TRUE ;
|
bit_index <= 8'b00000000;
|
bit_index <= 8'b00000000;
|
end
|
end
|
if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
|
if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
inhib_read <= `TRUE ;
|
inhib_read <= `TRUE ;
|
bit_index <= 8'b00000000;
|
bit_index <= 8'b00000000;
|
q_bis <= #`TSHQZ 1'bz ;
|
q_bis <= #`TSHQZ 1'bz ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(negedge c_int)
|
@(negedge c_int)
|
begin
|
begin
|
if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
|
if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5)))
|
begin
|
begin
|
if (select_ok)
|
if (select_ok)
|
begin
|
begin
|
q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
|
q_bis <= #`TCLQV data_to_read[7 - bit_index] ;
|
bit_index = bit_index + 1 ;
|
bit_index = bit_index + 1 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// Write_enable
|
// Write_enable
|
//-----------------------------------------
|
//-----------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
if (!wren)
|
if (!wren)
|
begin
|
begin
|
inhib_wren <= `FALSE ;
|
inhib_wren <= `FALSE ;
|
end
|
end
|
if (wren && (!only_rdsr) && (!only_res))
|
if (wren && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
wel <= 1'b1 ;
|
wel <= 1'b1 ;
|
inhib_wren <= `TRUE ;
|
inhib_wren <= `TRUE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(posedge c_int)
|
@(posedge c_int)
|
begin
|
begin
|
if (wren && (!only_rdsr) && (!only_res) && select_ok)
|
if (wren && (!only_rdsr) && (!only_res) && select_ok)
|
begin
|
begin
|
inhib_wren <= `TRUE ;
|
inhib_wren <= `TRUE ;
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
end
|
end
|
end
|
end
|
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// Write_disable
|
// Write_disable
|
//-------------------------------------------
|
//-------------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
if (!wrdi)
|
if (!wrdi)
|
begin
|
begin
|
inhib_wrdi <= `FALSE ;
|
inhib_wrdi <= `FALSE ;
|
end
|
end
|
if (wrdi && (!only_rdsr) && (!only_res))
|
if (wrdi && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
reset_wel <= 1'b1 ;
|
reset_wel <= 1'b1 ;
|
inhib_wrdi <= `TRUE ;
|
inhib_wrdi <= `TRUE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(posedge c_int)
|
@(posedge c_int)
|
begin
|
begin
|
if (wrdi && (!only_rdsr) && (!only_res) && select_ok)
|
if (wrdi && (!only_rdsr) && (!only_res) && select_ok)
|
begin
|
begin
|
inhib_wrdi <= `TRUE ;
|
inhib_wrdi <= `TRUE ;
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// Write_status_register
|
// Write_status_register
|
//-----------------------------------------
|
//-----------------------------------------
|
always
|
always
|
@(c_int or select_ok)
|
@(c_int or select_ok)
|
begin
|
begin
|
if (!wrsr)
|
if (!wrsr)
|
begin
|
begin
|
inhib_wrsr <= `FALSE ;
|
inhib_wrsr <= `FALSE ;
|
end
|
end
|
if (wrsr && (!only_rdsr) && (!only_res))
|
if (wrsr && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if ((byte_cpt == 1) && ((cpt != 7) || (!byte_ok)) && (!wr_cycle))
|
if ((byte_cpt == 1) && ((cpt != 7) || (!byte_ok)) && (!wr_cycle))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_wrsr <= `TRUE ;
|
inhib_wrsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
else if ((byte_cpt == 1) && (cpt == 7) && byte_ok)
|
else if ((byte_cpt == 1) && (cpt == 7) && byte_ok)
|
begin
|
begin
|
if (write_protect)
|
if (write_protect)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because status register is hardware protected");
|
if ($time != 0) $display("WARNING : Instruction canceled because status register is hardware protected");
|
inhib_wrsr <= `TRUE ;
|
inhib_wrsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(negedge select_ok)
|
@(negedge select_ok)
|
begin
|
begin
|
if (wrsr && (!only_rdsr) && (!only_res))
|
if (wrsr && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if ((byte_cpt == 1) && (cpt == 7) && byte_ok && (!write_protect))
|
if ((byte_cpt == 1) && (cpt == 7) && byte_ok && (!write_protect))
|
begin
|
begin
|
if ((status_register[1]) == 1'b0)
|
if ((status_register[1]) == 1'b0)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
inhib_wrsr <= `TRUE ;
|
inhib_wrsr <= `TRUE ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wr_cycle <= `TRUE ;
|
wr_cycle <= `TRUE ;
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
#`TW;
|
#`TW;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
wr_cycle <= `FALSE ;
|
wr_cycle <= `FALSE ;
|
end
|
end
|
end
|
end
|
else if (byte_cpt == 2)
|
else if (byte_cpt == 2)
|
begin
|
begin
|
if ((status_register[1]) == 1'b0)
|
if ((status_register[1]) == 1'b0)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
inhib_wrsr <= `TRUE ;
|
inhib_wrsr <= `TRUE ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
wr_cycle <= `TRUE ;
|
wr_cycle <= `TRUE ;
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
#`TW;
|
#`TW;
|
wr_cycle <= `FALSE ;
|
wr_cycle <= `FALSE ;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(posedge c_int)
|
always @(posedge c_int)
|
begin
|
begin
|
if (wrsr && (!only_rdsr) && (!only_res))
|
if (wrsr && (!only_rdsr) && (!only_res))
|
if (byte_cpt == 2 && !rdsr)
|
if (byte_cpt == 2 && !rdsr)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
inhib_wrsr <= `TRUE ;
|
inhib_wrsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// Bulk_erase
|
// Bulk_erase
|
//-------------------------------------------
|
//-------------------------------------------
|
always @( c_int or select_ok)
|
always @( c_int or select_ok)
|
begin
|
begin
|
if (!be)
|
if (!be)
|
begin
|
begin
|
inhib_be <= `FALSE ;
|
inhib_be <= `FALSE ;
|
end
|
end
|
if (be && (!only_rdsr) && (!only_res))
|
if (be && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
if ((status_register[1]) == 1'b0)
|
if ((status_register[1]) == 1'b0)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
be_enable <= `FALSE ;
|
be_enable <= `FALSE ;
|
inhib_be <= `TRUE ;
|
inhib_be <= `TRUE ;
|
end
|
end
|
else if (protect && be)
|
else if (protect && be)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because at least one sector is protected");
|
if ($time != 0) $display("WARNING : Instruction canceled because at least one sector is protected");
|
be_enable <= `FALSE ;
|
be_enable <= `FALSE ;
|
inhib_be <= `TRUE ;
|
inhib_be <= `TRUE ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Bulk erase cycle has begun");
|
if ($time != 0) $display("NOTE : Bulk erase cycle has begun");
|
be_enable <= `TRUE ;
|
be_enable <= `TRUE ;
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
// We can't use `TBE since it wider than a 32bits number
|
// We can't use `TBE since it wider than a 32bits number
|
// and the delay instruction can only manage 32bits wide number
|
// and the delay instruction can only manage 32bits wide number
|
#`TSE ;
|
#`TSE ;
|
#`TSE ;
|
#`TSE ;
|
if ($time != 0) $display("NOTE : Bulk erase cycle is finished");
|
if ($time != 0) $display("NOTE : Bulk erase cycle is finished");
|
be_enable <= `FALSE ;
|
be_enable <= `FALSE ;
|
inhib_be <= `TRUE ;
|
inhib_be <= `TRUE ;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
reset_wel <= 1'b1 ;
|
reset_wel <= 1'b1 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(posedge c_int)
|
always @(posedge c_int)
|
begin
|
begin
|
if (be && (!only_rdsr) && (!only_res))
|
if (be && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
inhib_be <= `TRUE ;
|
inhib_be <= `TRUE ;
|
end
|
end
|
end
|
end
|
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// Sector_erase
|
// Sector_erase
|
//-------------------------------------------
|
//-------------------------------------------
|
always @( c_int or select_ok)
|
always @( c_int or select_ok)
|
begin
|
begin
|
if (!se)
|
if (!se)
|
begin
|
begin
|
inhib_se <= `FALSE ;
|
inhib_se <= `FALSE ;
|
end
|
end
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && ((cpt != 7) || !byte_ok))) && se && (!only_rdsr) && (!only_res))
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && ((cpt != 7) || !byte_ok))) && se && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_se <= `TRUE ;
|
inhib_se <= `TRUE ;
|
end
|
end
|
end
|
end
|
if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
|
if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (!select_ok)
|
if (!select_ok)
|
begin
|
begin
|
if ((status_register[1]) == 1'b0)
|
if ((status_register[1]) == 1'b0)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
se_enable <= `FALSE ;
|
se_enable <= `FALSE ;
|
inhib_se <= `TRUE ;
|
inhib_se <= `TRUE ;
|
end
|
end
|
else if (protect && se)
|
else if (protect && se)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the SE sector is protected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the SE sector is protected");
|
se_enable <= `FALSE ;
|
se_enable <= `FALSE ;
|
inhib_se <= `TRUE ;
|
inhib_se <= `TRUE ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Sector erase cycle has begun");
|
if ($time != 0) $display("NOTE : Sector erase cycle has begun");
|
se_enable <= `TRUE ;
|
se_enable <= `TRUE ;
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
#`TSE ;
|
#`TSE ;
|
if ($time != 0) $display("NOTE : Sector erase cycle is finished");
|
if ($time != 0) $display("NOTE : Sector erase cycle is finished");
|
se_enable <= `FALSE ;
|
se_enable <= `FALSE ;
|
inhib_se <= `TRUE ;
|
inhib_se <= `TRUE ;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
reset_wel <= 1'b1 ;
|
reset_wel <= 1'b1 ;
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(posedge c_int)
|
always @(posedge c_int)
|
begin
|
begin
|
if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
|
if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
if (byte_cpt == 4 && select_ok)
|
if (byte_cpt == 4 && select_ok)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
inhib_se <= `TRUE ;
|
inhib_se <= `TRUE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//-------------------------------------------
|
//-------------------------------------------
|
// Page_Program
|
// Page_Program
|
//-------------------------------------------
|
//-------------------------------------------
|
always @(c_int or select_ok)
|
always @(c_int or select_ok)
|
begin
|
begin
|
if (!pp)
|
if (!pp)
|
begin
|
begin
|
inhib_pp <= `FALSE ;
|
inhib_pp <= `FALSE ;
|
add_pp_enable <= `FALSE ;
|
add_pp_enable <= `FALSE ;
|
pp_enable <= `FALSE ;
|
pp_enable <= `FALSE ;
|
end
|
end
|
|
|
if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
|
if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
add_pp_enable <= `TRUE ;
|
add_pp_enable <= `TRUE ;
|
if ((status_register[1]) == 1'b0)
|
if ((status_register[1]) == 1'b0)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset");
|
pp_enable <= `FALSE ;
|
pp_enable <= `FALSE ;
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
end
|
end
|
else if (protect && pp)
|
else if (protect && pp)
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the PP sector is protected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the PP sector is protected");
|
pp_enable <= `FALSE ;
|
pp_enable <= `FALSE ;
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always @(negedge select_ok)
|
always @(negedge select_ok)
|
begin
|
begin
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt != 7) || !byte_ok))) && pp && (!only_rdsr) && (!only_res) && (!select_ok))
|
if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt != 7) || !byte_ok))) && pp && (!only_rdsr) && (!only_res) && (!select_ok))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
end
|
end
|
if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
|
if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res))
|
begin
|
begin
|
add_pp_enable <= `TRUE ;
|
add_pp_enable <= `TRUE ;
|
if (pp)
|
if (pp)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Page program cycle is started");
|
if ($time != 0) $display("NOTE : Page program cycle is started");
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
#`TPP;
|
#`TPP;
|
if ($time != 0) $display("NOTE : Page program cycle is finished");
|
if ($time != 0) $display("NOTE : Page program cycle is finished");
|
pp_enable <= `TRUE ;
|
pp_enable <= `TRUE ;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
reset_wel <= 1'b1 ;
|
reset_wel <= 1'b1 ;
|
end
|
end
|
end
|
end
|
if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && byte_ok)
|
if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && byte_ok)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Page program cycle is started");
|
if ($time != 0) $display("NOTE : Page program cycle is started");
|
wip <= 1'b1 ;
|
wip <= 1'b1 ;
|
#`TPP;
|
#`TPP;
|
if ($time != 0) $display("NOTE : Page program cycle is finished");
|
if ($time != 0) $display("NOTE : Page program cycle is finished");
|
pp_enable <= `TRUE ;
|
pp_enable <= `TRUE ;
|
wip <= 1'b0 ;
|
wip <= 1'b0 ;
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
reset_wel <= 1'b1 ;
|
reset_wel <= 1'b1 ;
|
end
|
end
|
if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && (!byte_ok))
|
if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && (!byte_ok))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected");
|
inhib_pp <= `TRUE ;
|
inhib_pp <= `TRUE ;
|
pp_enable <= `FALSE ;
|
pp_enable <= `FALSE ;
|
end
|
end
|
end
|
end
|
|
|
//-----------------------------------------
|
//-----------------------------------------
|
// Deep Power Down
|
// Deep Power Down
|
//-----------------------------------------
|
//-----------------------------------------
|
always @(c_int or select_ok)
|
always @(c_int or select_ok)
|
begin
|
begin
|
if (!dp)
|
if (!dp)
|
begin
|
begin
|
inhib_dp <= `FALSE ;
|
inhib_dp <= `FALSE ;
|
only_res <= `FALSE ;
|
only_res <= `FALSE ;
|
t_only_res = 0;
|
t_only_res = 0;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge c_int)
|
always @(posedge c_int)
|
begin
|
begin
|
if (dp && (!only_rdsr) && (!only_res) && (!res))
|
if (dp && (!only_rdsr) && (!only_res) && (!res))
|
begin
|
begin
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected");
|
inhib_dp <= `TRUE ;
|
inhib_dp <= `TRUE ;
|
only_res <= `FALSE ;
|
only_res <= `FALSE ;
|
t_only_res = 0;
|
t_only_res = 0;
|
end
|
end
|
end
|
end
|
|
|
always @(negedge select_ok)
|
always @(negedge select_ok)
|
begin
|
begin
|
if (dp && (!only_rdsr) && (!only_res) && (!res))
|
if (dp && (!only_rdsr) && (!only_res) && (!res))
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Chip is entering deep power down mode");
|
if ($time != 0) $display("NOTE : Chip is entering deep power down mode");
|
// useful when chip is selected again to inhib every op_code except RES
|
// useful when chip is selected again to inhib every op_code except RES
|
// and to check tDP
|
// and to check tDP
|
t_only_res = $time;
|
t_only_res = $time;
|
only_res <= `TRUE ;
|
only_res <= `TRUE ;
|
|
|
end
|
end
|
end
|
end
|
|
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
// Release from Deep Power Down Mode and Read Electronic Signature
|
// Release from Deep Power Down Mode and Read Electronic Signature
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
always @(select_ok or c_int)
|
always @(select_ok or c_int)
|
begin
|
begin
|
if (!res)
|
if (!res)
|
begin
|
begin
|
inhib_res <= `FALSE ;
|
inhib_res <= `FALSE ;
|
bit_res <= 0;
|
bit_res <= 0;
|
end
|
end
|
|
|
if (res && ((byte_cpt == 1) && (cpt == 0)) && (!only_rdsr) && (!select_ok))
|
if (res && ((byte_cpt == 1) && (cpt == 0)) && (!only_rdsr) && (!select_ok))
|
begin
|
begin
|
if (only_res)
|
if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : The chip is releasing from DEEP POWER DOWN");
|
if ($time != 0) $display("NOTE : The chip is releasing from DEEP POWER DOWN");
|
end
|
end
|
inhib_res <= `FALSE;
|
inhib_res <= `FALSE;
|
inhib_dp <= `FALSE;
|
inhib_dp <= `FALSE;
|
#`TRES1;
|
#`TRES1;
|
inhib_res <= `TRUE;
|
inhib_res <= `TRUE;
|
inhib_dp <= `TRUE;
|
inhib_dp <= `TRUE;
|
end
|
end
|
else if ((((byte_cpt == 1) && (cpt > 0)) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt < 7) || (!byte_ok)))) && res && (!only_rdsr) && (!select_ok))
|
else if ((((byte_cpt == 1) && (cpt > 0)) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt < 7) || (!byte_ok)))) && res && (!only_rdsr) && (!select_ok))
|
begin
|
begin
|
if ($time != 0) $display("ERROR : Electronic Signature must be read at least once. Instruction not valid");
|
if ($time != 0) $display("ERROR : Electronic Signature must be read at least once. Instruction not valid");
|
end
|
end
|
else if ((((byte_cpt == 4) && (cpt == 7) && byte_ok) || (byte_cpt > 4)) && res && (!only_rdsr) && (!select_ok))
|
else if ((((byte_cpt == 4) && (cpt == 7) && byte_ok) || (byte_cpt > 4)) && res && (!only_rdsr) && (!select_ok))
|
begin
|
begin
|
#`TRES2;
|
#`TRES2;
|
inhib_res <= `TRUE ;
|
inhib_res <= `TRUE ;
|
inhib_dp <= `TRUE ;
|
inhib_dp <= `TRUE ;
|
if (only_res)
|
if (only_res)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : The Chip is releasing from DEEP POWER DOWN");
|
if ($time != 0) $display("NOTE : The Chip is releasing from DEEP POWER DOWN");
|
end
|
end
|
q_bis <= 1'bz ;
|
q_bis <= 1'bz ;
|
end
|
end
|
end
|
end
|
|
|
always @(negedge c_int)
|
always @(negedge c_int)
|
begin
|
begin
|
if ((((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)) && res && (!only_rdsr) )
|
if ((((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)) && res && (!only_rdsr) )
|
begin
|
begin
|
q_bis <= #`TCLQV signature[7 - bit_res] ;
|
q_bis <= #`TCLQV signature[7 - bit_res] ;
|
bit_res = bit_res + 1;
|
bit_res = bit_res + 1;
|
end
|
end
|
end
|
end
|
|
|
//-------------------------------------------------------
|
//-------------------------------------------------------
|
// This process shifts out status register on data output
|
// This process shifts out status register on data output
|
always
|
always
|
@(c_int or select_ok or rdsr)
|
@(c_int or select_ok or rdsr)
|
begin
|
begin
|
if (!rdsr)
|
if (!rdsr)
|
begin
|
begin
|
inhib_rdsr <= `FALSE ;
|
inhib_rdsr <= `FALSE ;
|
end
|
end
|
if (rdsr && (!select_ok))
|
if (rdsr && (!select_ok))
|
begin
|
begin
|
bit_register <= 0;
|
bit_register <= 0;
|
q_bis <= #`TSHQZ 1'bz ;
|
q_bis <= #`TSHQZ 1'bz ;
|
inhib_rdsr <= `TRUE ;
|
inhib_rdsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
|
|
always
|
always
|
@(negedge c_int)
|
@(negedge c_int)
|
begin
|
begin
|
if (rdsr && (select_ok))
|
if (rdsr && (select_ok))
|
begin
|
begin
|
q_bis <= #`TCLQV status_register[7 - bit_register] ;
|
q_bis <= #`TCLQV status_register[7 - bit_register] ;
|
bit_register = bit_register + 1;
|
bit_register = bit_register + 1;
|
end
|
end
|
end
|
end
|
//--------------------------------------------------------------------------------------
|
//--------------------------------------------------------------------------------------
|
// This process checks select and deselect conditions. Some other conditions are tested:
|
// This process checks select and deselect conditions. Some other conditions are tested:
|
// prog cycle, deep power down mode and read electronic signature.
|
// prog cycle, deep power down mode and read electronic signature.
|
always
|
always
|
begin : pin_s
|
begin : pin_s
|
@(s);
|
@(s);
|
begin
|
begin
|
if (s == 1'b0)
|
if (s == 1'b0)
|
begin
|
begin
|
if (res && only_res)
|
if (res && only_res)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : The chip must not be selected until tRES");
|
if ($time != 0) $display("ERROR : The chip must not be selected until tRES");
|
end
|
end
|
else if (dp)
|
else if (dp)
|
begin
|
begin
|
if (($time - t_only_res) < `TDP)
|
if (($time - t_only_res) < `TDP)
|
begin
|
begin
|
if ($time != 0) $display("ERROR : The chip must not be selected until tDP");
|
if ($time != 0) $display("ERROR : The chip must not be selected until tDP");
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Only a Read Electronic Signature instruction will be valid");
|
if ($time != 0) $display("NOTE : Only a Read Electronic Signature instruction will be valid");
|
end
|
end
|
end
|
end
|
select_ok <= `TRUE ;
|
select_ok <= `TRUE ;
|
if (pp || wrsr || be || se)
|
if (pp || wrsr || be || se)
|
begin
|
begin
|
if ($time != 0) $display("NOTE : Only a Read Status Register instruction will be valid");
|
if ($time != 0) $display("NOTE : Only a Read Status Register instruction will be valid");
|
only_rdsr <= `TRUE ;
|
only_rdsr <= `TRUE ;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
select_ok <= `FALSE ;
|
select_ok <= `FALSE ;
|
only_rdsr <= `FALSE ;
|
only_rdsr <= `FALSE ;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
// This Process detects the hardware protection mode
|
// This Process detects the hardware protection mode
|
always
|
always
|
@(w or c_int)
|
@(w or c_int)
|
begin
|
begin
|
if ((w == 1'b0) && ((status_register[7]) == 1'b1))
|
if ((w == 1'b0) && ((status_register[7]) == 1'b1))
|
begin
|
begin
|
write_protect <= `TRUE ;
|
write_protect <= `TRUE ;
|
end
|
end
|
if (w == 1'b1)
|
if (w == 1'b1)
|
begin
|
begin
|
write_protect <= `FALSE ;
|
write_protect <= `FALSE ;
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
|
|