Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
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Reading D:/Actel/Libero_v9.1/Model/tcl/vsim/pref.tcl
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# 6.6d
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# 6.6d
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# vsim +uart_test_1 -do run.do -c tb_top
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# vsim +uart_test_1 -do run.do -c tb_top
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# // ModelSim ACTEL 6.6d Nov 2 2010
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# // ModelSim ACTEL 6.6d Nov 2 2010
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# //
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# //
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# // Copyright 1991-2010 Mentor Graphics Corporation
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# // Copyright 1991-2010 Mentor Graphics Corporation
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# // All Rights Reserved.
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# // All Rights Reserved.
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# //
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# //
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# // THIS WORK CONTAINS TRADE SECRET AND
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# // THIS WORK CONTAINS TRADE SECRET AND
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# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
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# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
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# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
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# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
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# // AND IS SUBJECT TO LICENSE TERMS.
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# // AND IS SUBJECT TO LICENSE TERMS.
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# //
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# //
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# Loading sv_std.std
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# Loading sv_std.std
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# Loading work.tb_top
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# Loading work.tb_top
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# Loading work.turbo8051
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# Loading work.turbo8051
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# Loading work.clkgen
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# Loading work.clkgen
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# Loading work.clk_ctl
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# Loading work.clk_ctl
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# Loading work.wb_crossbar
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# Loading work.wb_crossbar
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# Loading work.g_mac_top
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# Loading work.g_mac_top
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# Loading work.g_dpath_ctrl
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# Loading work.g_dpath_ctrl
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# Loading work.g_eth_parser
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# Loading work.g_eth_parser
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# Loading work.g_mac_core
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# Loading work.g_mac_core
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# Loading work.g_rx_top
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# Loading work.g_rx_top
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# Loading work.g_rx_fsm
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# Loading work.g_rx_fsm
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# Loading work.half_dup_dble_reg
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# Loading work.half_dup_dble_reg
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# Loading work.g_rx_crc32
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# Loading work.g_rx_crc32
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# Loading work.g_deferral_rx
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# Loading work.g_deferral_rx
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# Loading work.g_md_intf
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# Loading work.g_md_intf
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# Loading work.g_tx_top
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# Loading work.g_tx_top
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# Loading work.g_deferral
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# Loading work.g_deferral
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# Loading work.g_tx_fsm
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# Loading work.g_tx_fsm
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# Loading work.g_tx_crc32
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# Loading work.g_tx_crc32
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# Loading work.toggle_sync
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# Loading work.toggle_sync
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# Loading work.g_cfg_mgmt
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# Loading work.g_cfg_mgmt
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# Loading work.s2f_sync
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# Loading work.s2f_sync
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# Loading work.generic_register
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# Loading work.generic_register
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# Loading work.req_register
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# Loading work.req_register
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# Loading work.stat_counter
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# Loading work.stat_counter
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# Loading work.generic_intr_stat_reg
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# Loading work.generic_intr_stat_reg
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# Loading work.g_mii_intf
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# Loading work.g_mii_intf
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# Loading work.async_fifo
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# Loading work.async_fifo
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# Loading work.wb_rd_mem2mem
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# Loading work.wb_rd_mem2mem
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# Loading work.wb_wr_mem2mem
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# Loading work.wb_wr_mem2mem
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# Loading work.uart_core
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# Loading work.uart_core
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# Loading work.uart_cfg
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# Loading work.uart_cfg
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# Loading work.stat_register
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# Loading work.stat_register
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# Loading work.uart_txfsm
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# Loading work.uart_txfsm
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# Loading work.uart_rxfsm
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# Loading work.uart_rxfsm
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# Loading work.double_sync_low
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# Loading work.double_sync_low
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# Loading work.spi_core
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# Loading work.spi_core
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# Loading work.spi_if
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# Loading work.spi_if
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# Loading work.spi_ctl
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# Loading work.spi_ctl
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# Loading work.spi_cfg
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# Loading work.spi_cfg
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# Loading work.oc8051_top
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# Loading work.oc8051_top
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# Loading work.oc8051_decoder
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# Loading work.oc8051_decoder
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# Loading work.oc8051_alu
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# Loading work.oc8051_alu
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# Loading work.oc8051_multiply
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# Loading work.oc8051_multiply
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# Loading work.oc8051_divide
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# Loading work.oc8051_divide
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# Loading work.oc8051_ram_top
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# Loading work.oc8051_ram_top
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# Loading work.oc8051_ram_256x8_two_bist
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# Loading work.oc8051_ram_256x8_two_bist
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# Loading work.oc8051_alu_src_sel
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# Loading work.oc8051_alu_src_sel
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# Loading work.oc8051_comp
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# Loading work.oc8051_comp
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# Loading work.oc8051_rom
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# Loading work.oc8051_cy_select
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# Loading work.oc8051_cy_select
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# Loading work.oc8051_indi_addr
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# Loading work.oc8051_indi_addr
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# Loading work.oc8051_memory_interface
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# Loading work.oc8051_memory_interface
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# Loading work.oc8051_sfr
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# Loading work.oc8051_sfr
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# Loading work.oc8051_acc
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# Loading work.oc8051_acc
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# Loading work.oc8051_b_register
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# Loading work.oc8051_b_register
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# Loading work.oc8051_sp
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# Loading work.oc8051_sp
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# Loading work.oc8051_dptr
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# Loading work.oc8051_dptr
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# Loading work.oc8051_psw
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# Loading work.oc8051_psw
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# Loading work.oc8051_ports
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# Loading work.oc8051_ports
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# Loading work.oc8051_int
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# Loading work.oc8051_int
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# Loading work.oc8051_tc
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# Loading work.oc8051_tc
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# Loading work.oc8051_tc2
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# Loading work.oc8051_tc2
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# Loading work.oc8051_xrom
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# Loading work.oc8051_xrom
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# Loading work.oc8051_xram
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# Loading work.oc8051_xram
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# Loading work.tb_eth_top
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# Loading work.tb_eth_top
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# Loading work.tb_mii
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# Loading work.tb_mii
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# Loading work.tb_rmii
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# Loading work.tb_rmii
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# Loading work.uart_agent
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# Loading work.uart_agent
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# Loading work.m25p20
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# Loading work.m25p20
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# Loading work.memory_access
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# Loading work.memory_access
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# Loading work.acdc_check
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# Loading work.acdc_check
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# Loading work.internal_logic
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# Loading work.internal_logic
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# Loading work.AT45DB321
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# Loading work.AT45DB321
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# Loading work.tb_glbl
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# Loading work.tb_glbl
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# Loading work.bit_register
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# Loading work.bit_register
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# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf
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# File in use by: Hostname: ProcessID: 14
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# Attempting to use alternate WLF file "./wlft22nc1m".
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# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf
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# Using alternate file: ./wlft22nc1m
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(211): [TFMPC] - Too few port connections. Expected 14, found 12.
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# Region: /tb_top/u_core/u_uart_core/u_rxfifo
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# Region: /tb_top/u_core/u_uart_core/u_rxfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'afull'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(211): [TFMPC] - Missing connection for port 'aempty'.
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
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# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(227): [TFMPC] - Too few port connections. Expected 14, found 12.
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# Region: /tb_top/u_core/u_uart_core/u_txfifo
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# Region: /tb_top/u_core/u_uart_core/u_txfifo
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'afull'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
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# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(227): [TFMPC] - Missing connection for port 'aempty'.
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# do run.do
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# do run.do
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# i : 00
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# NOTE : Load memory with Initial delivery content
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# NOTE : Load memory with Initial delivery content
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# NOTE : Initial Load End
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# NOTE : Initial Load End
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# NOTE: COMMUNICATION (RE)STARTED
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# NOTE: COMMUNICATION (RE)STARTED
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# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000017
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# Config-Write: Id: 3 Addr = 0000, Cfg. Data = 00000017
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#
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#
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# ... Writing char 36 ...
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# ... Writing char 36 ...
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# ... Write data 24 to UART done cnt : 1 ...
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# ... Write data 24 to UART done cnt : 1 ...
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#
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#
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#
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#
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# ... Writing char 129 ...
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# ... Writing char 129 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 24
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 24
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# ... Read Data from UART done cnt : 1...
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# ... Read Data from UART done cnt : 1...
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# ... Write data 81 to UART done cnt : 2 ...
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# ... Write data 81 to UART done cnt : 2 ...
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#
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#
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#
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#
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# ... Writing char 9 ...
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# ... Writing char 9 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 81
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 81
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# ... Read Data from UART done cnt : 2...
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# ... Read Data from UART done cnt : 2...
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# ... Write data 09 to UART done cnt : 3 ...
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# ... Write data 09 to UART done cnt : 3 ...
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#
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#
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#
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#
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# ... Writing char 99 ...
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# ... Writing char 99 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 09
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 09
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# ... Read Data from UART done cnt : 3...
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# ... Read Data from UART done cnt : 3...
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# ... Write data 63 to UART done cnt : 4 ...
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# ... Write data 63 to UART done cnt : 4 ...
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#
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#
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#
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#
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# ... Writing char 13 ...
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# ... Writing char 13 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
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# ... Read Data from UART done cnt : 4...
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# ... Read Data from UART done cnt : 4...
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# ... Write data 0d to UART done cnt : 5 ...
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# ... Write data 0d to UART done cnt : 5 ...
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#
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#
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#
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#
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# ... Writing char 141 ...
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# ... Writing char 141 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
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# ... Read Data from UART done cnt : 5...
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# ... Read Data from UART done cnt : 5...
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# ... Write data 8d to UART done cnt : 6 ...
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# ... Write data 8d to UART done cnt : 6 ...
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#
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#
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#
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#
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# ... Writing char 101 ...
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# ... Writing char 101 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8d
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8d
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# ... Read Data from UART done cnt : 6...
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# ... Read Data from UART done cnt : 6...
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# ... Write data 65 to UART done cnt : 7 ...
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# ... Write data 65 to UART done cnt : 7 ...
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#
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#
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#
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#
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# ... Writing char 18 ...
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# ... Writing char 18 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
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# ... Read Data from UART done cnt : 7...
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# ... Read Data from UART done cnt : 7...
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# ... Write data 12 to UART done cnt : 8 ...
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# ... Write data 12 to UART done cnt : 8 ...
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#
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#
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#
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#
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# ... Writing char 1 ...
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# ... Writing char 1 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
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# ... Read Data from UART done cnt : 8...
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# ... Read Data from UART done cnt : 8...
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# ... Write data 01 to UART done cnt : 9 ...
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# ... Write data 01 to UART done cnt : 9 ...
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#
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#
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#
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#
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# ... Writing char 13 ...
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# ... Writing char 13 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 01
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 01
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# ... Read Data from UART done cnt : 9...
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# ... Read Data from UART done cnt : 9...
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# ... Write data 0d to UART done cnt : 10 ...
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# ... Write data 0d to UART done cnt : 10 ...
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#
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#
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#
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#
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# ... Writing char 118 ...
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# ... Writing char 118 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
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# ... Read Data from UART done cnt : 10...
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# ... Read Data from UART done cnt : 10...
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# ... Write data 76 to UART done cnt : 11 ...
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# ... Write data 76 to UART done cnt : 11 ...
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#
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#
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#
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#
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# ... Writing char 61 ...
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# ... Writing char 61 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 76
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 76
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# ... Read Data from UART done cnt : 11...
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# ... Read Data from UART done cnt : 11...
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# ... Write data 3d to UART done cnt : 12 ...
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# ... Write data 3d to UART done cnt : 12 ...
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#
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#
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#
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#
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# ... Writing char 237 ...
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# ... Writing char 237 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 3d
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 3d
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# ... Read Data from UART done cnt : 12...
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# ... Read Data from UART done cnt : 12...
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# ... Write data ed to UART done cnt : 13 ...
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# ... Write data ed to UART done cnt : 13 ...
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#
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#
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#
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#
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# ... Writing char 140 ...
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# ... Writing char 140 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match ed
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match ed
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# ... Read Data from UART done cnt : 13...
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# ... Read Data from UART done cnt : 13...
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# ... Write data 8c to UART done cnt : 14 ...
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# ... Write data 8c to UART done cnt : 14 ...
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#
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#
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#
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#
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# ... Writing char 249 ...
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# ... Writing char 249 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8c
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8c
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# ... Read Data from UART done cnt : 14...
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# ... Read Data from UART done cnt : 14...
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# ... Write data f9 to UART done cnt : 15 ...
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# ... Write data f9 to UART done cnt : 15 ...
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#
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#
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#
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#
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# ... Writing char 198 ...
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# ... Writing char 198 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match f9
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match f9
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# ... Read Data from UART done cnt : 15...
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# ... Read Data from UART done cnt : 15...
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# ... Write data c6 to UART done cnt : 16 ...
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# ... Write data c6 to UART done cnt : 16 ...
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#
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#
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#
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#
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# ... Writing char 197 ...
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# ... Writing char 197 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match c6
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match c6
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# ... Read Data from UART done cnt : 16...
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# ... Read Data from UART done cnt : 16...
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# ... Write data c5 to UART done cnt : 17 ...
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# ... Write data c5 to UART done cnt : 17 ...
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#
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#
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#
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#
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# ... Writing char 170 ...
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# ... Writing char 170 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
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# ... Read Data from UART done cnt : 17...
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# ... Read Data from UART done cnt : 17...
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# ... Write data aa to UART done cnt : 18 ...
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# ... Write data aa to UART done cnt : 18 ...
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#
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#
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#
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#
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# ... Writing char 229 ...
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# ... Writing char 229 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
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# ... Read Data from UART done cnt : 18...
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# ... Read Data from UART done cnt : 18...
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# ... Write data e5 to UART done cnt : 19 ...
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# ... Write data e5 to UART done cnt : 19 ...
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#
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#
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#
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#
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# ... Writing char 119 ...
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# ... Writing char 119 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match e5
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match e5
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# ... Read Data from UART done cnt : 19...
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# ... Read Data from UART done cnt : 19...
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# ... Write data 77 to UART done cnt : 20 ...
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# ... Write data 77 to UART done cnt : 20 ...
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#
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#
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#
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#
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# ... Writing char 18 ...
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# ... Writing char 18 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 77
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 77
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# ... Read Data from UART done cnt : 20...
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# ... Read Data from UART done cnt : 20...
|
# ... Write data 12 to UART done cnt : 21 ...
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# ... Write data 12 to UART done cnt : 21 ...
|
#
|
#
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#
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#
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# ... Writing char 143 ...
|
# ... Writing char 143 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 12
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# ... Read Data from UART done cnt : 21...
|
# ... Read Data from UART done cnt : 21...
|
# ... Write data 8f to UART done cnt : 22 ...
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# ... Write data 8f to UART done cnt : 22 ...
|
#
|
#
|
#
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#
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# ... Writing char 242 ...
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# ... Writing char 242 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8f
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match 8f
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# ... Read Data from UART done cnt : 22...
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# ... Read Data from UART done cnt : 22...
|
# ... Write data f2 to UART done cnt : 23 ...
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# ... Write data f2 to UART done cnt : 23 ...
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#
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#
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#
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#
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# ... Writing char 206 ...
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# ... Writing char 206 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match f2
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match f2
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# ... Read Data from UART done cnt : 23...
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# ... Read Data from UART done cnt : 23...
|
# ... Write data ce to UART done cnt : 24 ...
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# ... Write data ce to UART done cnt : 24 ...
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#
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#
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#
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#
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# ... Writing char 232 ...
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# ... Writing char 232 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match ce
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match ce
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# ... Read Data from UART done cnt : 24...
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# ... Read Data from UART done cnt : 24...
|
# ... Write data e8 to UART done cnt : 25 ...
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# ... Write data e8 to UART done cnt : 25 ...
|
#
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#
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#
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#
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# ... Writing char 197 ...
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# ... Writing char 197 ...
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match e8
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# (tb_top.tb_uart.read_char_chk.loop_2) Data match e8
|
# ... Read Data from UART done cnt : 25...
|
# ... Read Data from UART done cnt : 25...
|
# ... Write data c5 to UART done cnt : 26 ...
|
# ... Write data c5 to UART done cnt : 26 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 92 ...
|
# ... Writing char 92 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match c5
|
# ... Read Data from UART done cnt : 26...
|
# ... Read Data from UART done cnt : 26...
|
# ... Write data 5c to UART done cnt : 27 ...
|
# ... Write data 5c to UART done cnt : 27 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 189 ...
|
# ... Writing char 189 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 5c
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 5c
|
# ... Read Data from UART done cnt : 27...
|
# ... Read Data from UART done cnt : 27...
|
# ... Write data bd to UART done cnt : 28 ...
|
# ... Write data bd to UART done cnt : 28 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 45 ...
|
# ... Writing char 45 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match bd
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match bd
|
# ... Read Data from UART done cnt : 28...
|
# ... Read Data from UART done cnt : 28...
|
# ... Write data 2d to UART done cnt : 29 ...
|
# ... Write data 2d to UART done cnt : 29 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 101 ...
|
# ... Writing char 101 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 2d
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 2d
|
# ... Read Data from UART done cnt : 29...
|
# ... Read Data from UART done cnt : 29...
|
# ... Write data 65 to UART done cnt : 30 ...
|
# ... Write data 65 to UART done cnt : 30 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 99 ...
|
# ... Writing char 99 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 65
|
# ... Read Data from UART done cnt : 30...
|
# ... Read Data from UART done cnt : 30...
|
# ... Write data 63 to UART done cnt : 31 ...
|
# ... Write data 63 to UART done cnt : 31 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 10 ...
|
# ... Writing char 10 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 63
|
# ... Read Data from UART done cnt : 31...
|
# ... Read Data from UART done cnt : 31...
|
# ... Write data 0a to UART done cnt : 32 ...
|
# ... Write data 0a to UART done cnt : 32 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 128 ...
|
# ... Writing char 128 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0a
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0a
|
# ... Read Data from UART done cnt : 32...
|
# ... Read Data from UART done cnt : 32...
|
# ... Write data 80 to UART done cnt : 33 ...
|
# ... Write data 80 to UART done cnt : 33 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 32 ...
|
# ... Writing char 32 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 80
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 80
|
# ... Read Data from UART done cnt : 33...
|
# ... Read Data from UART done cnt : 33...
|
# ... Write data 20 to UART done cnt : 34 ...
|
# ... Write data 20 to UART done cnt : 34 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 170 ...
|
# ... Writing char 170 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 20
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 20
|
# ... Read Data from UART done cnt : 34...
|
# ... Read Data from UART done cnt : 34...
|
# ... Write data aa to UART done cnt : 35 ...
|
# ... Write data aa to UART done cnt : 35 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 157 ...
|
# ... Writing char 157 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match aa
|
# ... Read Data from UART done cnt : 35...
|
# ... Read Data from UART done cnt : 35...
|
# ... Write data 9d to UART done cnt : 36 ...
|
# ... Write data 9d to UART done cnt : 36 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 150 ...
|
# ... Writing char 150 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 9d
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 9d
|
# ... Read Data from UART done cnt : 36...
|
# ... Read Data from UART done cnt : 36...
|
# ... Write data 96 to UART done cnt : 37 ...
|
# ... Write data 96 to UART done cnt : 37 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 19 ...
|
# ... Writing char 19 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 96
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 96
|
# ... Read Data from UART done cnt : 37...
|
# ... Read Data from UART done cnt : 37...
|
# ... Write data 13 to UART done cnt : 38 ...
|
# ... Write data 13 to UART done cnt : 38 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 13 ...
|
# ... Writing char 13 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 13
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 13
|
# ... Read Data from UART done cnt : 38...
|
# ... Read Data from UART done cnt : 38...
|
# ... Write data 0d to UART done cnt : 39 ...
|
# ... Write data 0d to UART done cnt : 39 ...
|
#
|
#
|
#
|
#
|
# ... Writing char 83 ...
|
# ... Writing char 83 ...
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 0d
|
# ... Read Data from UART done cnt : 39...
|
# ... Read Data from UART done cnt : 39...
|
# ... Write data 53 to UART done cnt : 40 ...
|
# ... Write data 53 to UART done cnt : 40 ...
|
#
|
#
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 53
|
# (tb_top.tb_uart.read_char_chk.loop_2) Data match 53
|
# ... Read Data from UART done cnt : 40...
|
# ... Read Data from UART done cnt : 40...
|
# -------------------- Reporting Configuration --------------------
|
# -------------------- Reporting Configuration --------------------
|
# Data bit number setting is : 8
|
# Data bit number setting is : 8
|
# Stop bit number setting is : 1
|
# Stop bit number setting is : 1
|
# Divisor of Uart clock is : 3
|
# Divisor of Uart clock is : 3
|
# Parity is enable
|
# Parity is enable
|
# Even parity setting
|
# Even parity setting
|
# FIFO mode is disable
|
# FIFO mode is disable
|
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
# -------------------- Reporting Status --------------------
|
# -------------------- Reporting Status --------------------
|
#
|
#
|
# Number of character received is : 40
|
# Number of character received is : 40
|
# Number of character sent is : 40
|
# Number of character sent is : 40
|
# Number of parity error rxd is : 0
|
# Number of parity error rxd is : 0
|
# Number of stop1 error rxd is : 0
|
# Number of stop1 error rxd is : 0
|
# Number of stop2 error rxd is : 0
|
# Number of stop2 error rxd is : 0
|
# Number of timeout error is : 0
|
# Number of timeout error is : 0
|
# Number of error is : 0
|
# Number of error is : 0
|
# -----------------------------------------------------------------
|
# -----------------------------------------------------------------
|
#
|
#
|
# -------------------------------------------------
|
# -------------------------------------------------
|
# Test Status
|
# Test Status
|
# warnings: 0, errors: 0
|
# warnings: 0, errors: 0
|
#
|
#
|
# -------------------------------------------------
|
# -------------------------------------------------
|
# Test Status
|
# Test Status
|
# warnings: 0, errors: 0
|
# warnings: 0, errors: 0
|
#
|
#
|
# =========
|
# =========
|
# Test Status: TEST PASSED
|
# Test Status: TEST PASSED
|
# =========
|
# =========
|
#
|
#
|
# ** Note: $finish : ../../verif/lib/tb_glbl.v(64)
|
# ** Note: $finish : ../../verif/lib/tb_glbl.v(64)
|
# Time: 157871 ns Iteration: 0 Instance: /tb_top
|
# Time: 157871 ns Iteration: 0 Instance: /tb_top
|
|
|