//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the Turbo 8051 cores project ////
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//// This file is part of the Turbo 8051 cores project ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// http://www.opencores.org/cores/turbo8051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Turbo 8051 definitions. ////
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//// Turbo 8051 definitions. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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`include "tb_defines.v"
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`include "tb_defines.v"
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module tb_top;
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module tb_top;
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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// Target ID Mapping
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// Target ID Mapping
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// 4'b0100 -- MAC core
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// 4'b0100 -- MAC core
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// 4'b0011 -- UART
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// 4'b0011 -- UART
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// 4'b0010 -- SPI core
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// 4'b0010 -- SPI core
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// 4'b0001 -- External RAM
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// 4'b0001 -- External RAM
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// 4'b0000 -- External ROM
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// 4'b0000 -- External ROM
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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`define ADDR_SPACE_MAC 4'b0100
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`define ADDR_SPACE_MAC 4'b0100
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`define ADDR_SPACE_UART 4'b0011
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`define ADDR_SPACE_UART 4'b0011
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`define ADDR_SPACE_SPI 4'b0010
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`define ADDR_SPACE_SPI 4'b0010
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`define ADDR_SPACE_RAM 4'b0001
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`define ADDR_SPACE_RAM 4'b0001
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`define ADDR_SPACE_ROM 4'b0000
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`define ADDR_SPACE_ROM 4'b0000
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reg reset_n;
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reg reset_n;
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reg reset;
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reg reset;
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reg xtal_clk;
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reg xtal_clk;
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reg ref_clk_125;
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reg ref_clk_125;
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wire app_clk;
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wire app_clk;
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reg ref_clk_50;
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reg ref_clk_50;
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reg uart_clk_16x;
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reg uart_clk_16x;
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parameter XTAL_CLK_PERIOD = 40; // 25Mhz
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parameter XTAL_CLK_PERIOD = 40; // 25Mhz
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parameter APP_CLK_PERIOD = 10;
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parameter APP_CLK_PERIOD = 10;
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parameter REF_CLK_125_PERIOD = 8;
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parameter REF_CLK_125_PERIOD = 8;
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parameter REF_CLK_50_PERIOD = 20;
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parameter REF_CLK_50_PERIOD = 20;
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parameter UART_REF_CLK_PERIOD = 20;
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parameter UART_REF_CLK_PERIOD = 20;
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reg[31:0] events_log;
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reg[31:0] events_log;
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initial
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initial
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begin
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begin
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reset_n = 1;
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reset_n = 1;
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#100 reset_n = 0;
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#100 reset_n = 0;
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#100 reset_n = 1;
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#100 reset_n = 1;
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end
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end
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initial begin
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initial begin
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xtal_clk = 1'b0;
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xtal_clk = 1'b0;
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forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
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forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk;
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end
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end
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//initial begin
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//initial begin
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// app_clk = 1'b0;
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// app_clk = 1'b0;
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// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
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// forever #(APP_CLK_PERIOD/2.0) app_clk = ~app_clk;
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//end
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//end
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initial begin
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initial begin
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ref_clk_125 = 1'b0;
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ref_clk_125 = 1'b0;
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forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
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forever #(REF_CLK_125_PERIOD/2.0) ref_clk_125 = ~ref_clk_125;
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end
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end
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initial begin
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initial begin
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ref_clk_50 = 1'b0;
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ref_clk_50 = 1'b0;
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forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
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forever #(REF_CLK_50_PERIOD/2.0) ref_clk_50 = ~ref_clk_50;
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end
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end
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initial begin
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initial begin
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uart_clk_16x = 1'b0;
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uart_clk_16x = 1'b0;
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forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
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forever #(UART_REF_CLK_PERIOD/2.0) uart_clk_16x = ~uart_clk_16x;
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end
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end
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wire [7:0] phy_txd ;
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wire [7:0] phy_txd ;
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wire [7:0] phy_rxd ;
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wire [7:0] phy_rxd ;
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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reg reg_cs ;
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reg reg_cs ;
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reg [3:0] reg_id ;
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reg [3:0] reg_id ;
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reg reg_wr ;
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reg reg_wr ;
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reg [12:0] reg_addr ;
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reg [12:0] reg_addr ;
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reg [31:0] reg_wdata ;
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reg [31:0] reg_wdata ;
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reg [3:0] reg_be ;
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reg [3:0] reg_be ;
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// Outputs
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// Outputs
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wire [31:0] reg_rdata ;
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wire [31:0] reg_rdata ;
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wire reg_ack ;
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wire reg_ack ;
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reg master_mode ;
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reg ea_in ; // 1--> Internal Memory
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wire spi_sck ;
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wire spi_sck ;
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wire spi_so ;
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wire spi_so ;
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wire spi_si ;
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wire spi_si ;
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wire [3:0] spi_cs_n ;
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wire [3:0] spi_cs_n ;
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wire clkout ;
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wire clkout ;
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wire reset_out_n ;
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wire reset_out_n ;
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//----------------------------------------
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//----------------------------------------
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// 8051 core ROM related signals
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// 8051 core ROM related signals
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//---------------------------------------
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//---------------------------------------
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wire [15:0] wb_xrom_adr ; // instruction address
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wire [15:0] wb_xrom_adr ; // instruction address
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wire wb_xrom_ack ; // instruction acknowlage
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wire wb_xrom_ack ; // instruction acknowlage
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wire wb_xrom_err ; // instruction error
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wire wb_xrom_err ; // instruction error
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wire wb_xrom_wr ; // instruction error
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wire wb_xrom_wr ; // instruction error
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wire [31:0] wb_xrom_rdata ; // rom data input
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wire [31:0] wb_xrom_rdata ; // rom data input
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wire [31:0] wb_xrom_wdata ; // rom data input
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wire [31:0] wb_xrom_wdata ; // rom data input
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wire wb_xrom_stb ; // instruction strobe
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wire wb_xrom_stb ; // instruction strobe
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wire wb_xrom_cyc ; // instruction cycle
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wire wb_xrom_cyc ; // instruction cycle
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//----------------------------------------
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//----------------------------------------
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// 8051 core RAM related signals
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// 8051 core RAM related signals
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//---------------------------------------
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//---------------------------------------
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wire [15:0] wb_xram_adr ; // data-ram address
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wire [15:0] wb_xram_adr ; // data-ram address
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wire wb_xram_ack ; // data-ram acknowlage
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wire wb_xram_ack ; // data-ram acknowlage
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wire wb_xram_err ; // data-ram error
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wire wb_xram_err ; // data-ram error
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wire wb_xram_wr ; // data-ram error
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wire wb_xram_wr ; // data-ram error
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wire [7:0] wb_xram_rdata ; // ram data input
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wire [7:0] wb_xram_rdata ; // ram data input
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wire [7:0] wb_xram_wdata ; // ram data input
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wire [7:0] wb_xram_wdata ; // ram data input
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wire wb_xram_stb ; // data-ram strobe
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wire wb_xram_stb ; // data-ram strobe
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wire wb_xram_cyc ; // data-ram cycle
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wire wb_xram_cyc ; // data-ram cycle
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//----------------------------------------
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//----------------------------------------
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core u_core (
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core u_core (
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. reset_n (reset_n ),
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. reset_n (reset_n ),
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. fastsim_mode (1'b1 ),
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. fastsim_mode (1'b1 ),
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. mastermode (master_mode ),
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`ifdef INTERNAL_ROM
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. mastermode (1'b1 ),
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`elsif EXTERNAL_ROM
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. mastermode (1'b1 ),
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`else
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. mastermode (1'b0 ),
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`endif
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. xtal_clk (xtal_clk ),
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. xtal_clk (xtal_clk ),
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. clkout (app_clk ),
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. clkout (app_clk ),
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. reset_out_n (reset_out_n ),
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. reset_out_n (reset_out_n ),
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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. ext_reg_cs (reg_cs ),
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. ext_reg_cs (reg_cs ),
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. ext_reg_tid (reg_id ),
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. ext_reg_tid (reg_id ),
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. ext_reg_wr (reg_wr ),
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. ext_reg_wr (reg_wr ),
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. ext_reg_addr (reg_addr[12:0] ),
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. ext_reg_addr (reg_addr[12:0] ),
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. ext_reg_wdata (reg_wdata ),
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. ext_reg_wdata (reg_wdata ),
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. ext_reg_be (reg_be ),
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. ext_reg_be (reg_be ),
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// Outputs
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// Outputs
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. ext_reg_rdata (reg_rdata ),
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. ext_reg_rdata (reg_rdata ),
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. ext_reg_ack (reg_ack ),
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. ext_reg_ack (reg_ack ),
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// Line Side Interface TX Path
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// Line Side Interface TX Path
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.phy_tx_en (phy_tx_en ),
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.phy_tx_en (phy_tx_en ),
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.phy_txd (phy_txd ),
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.phy_txd (phy_txd ),
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.phy_tx_clk (phy_tx_clk ),
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.phy_tx_clk (phy_tx_clk ),
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// Line Side Interface RX Path
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// Line Side Interface RX Path
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.phy_rx_clk (phy_rx_clk ),
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.phy_rx_clk (phy_rx_clk ),
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.phy_rx_dv (phy_rx_dv ),
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.phy_rx_dv (phy_rx_dv ),
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.phy_rxd (phy_rxd ),
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.phy_rxd (phy_rxd ),
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//MDIO interface
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//MDIO interface
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.MDC (MDC ),
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.MDC (MDC ),
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.MDIO (MDIO ),
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.MDIO (MDIO ),
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// UART Line Interface
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// UART Line Interface
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.si (si ),
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.si (si ),
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.so (so ),
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.so (so ),
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.spi_sck (spi_sck ),
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.spi_sck (spi_sck ),
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.spi_so (spi_so ),
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.spi_so (spi_so ),
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.spi_si (spi_si ),
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.spi_si (spi_si ),
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.spi_cs_n (spi_cs_n ),
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.spi_cs_n (spi_cs_n ),
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// External ROM interface
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// External ROM interface
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.wb_xrom_adr (wb_xrom_adr ),
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.wb_xrom_adr (wb_xrom_adr ),
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.wb_xrom_ack (wb_xrom_ack ),
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.wb_xrom_ack (wb_xrom_ack ),
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.wb_xrom_err (wb_xrom_err ),
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.wb_xrom_err (wb_xrom_err ),
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.wb_xrom_wr (wb_xrom_wr ),
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.wb_xrom_wr (wb_xrom_wr ),
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.wb_xrom_rdata (wb_xrom_rdata ),
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.wb_xrom_rdata (wb_xrom_rdata ),
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.wb_xrom_wdata (wb_xrom_wdata ),
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.wb_xrom_wdata (wb_xrom_wdata ),
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.wb_xrom_stb (wb_xrom_stb ),
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.wb_xrom_stb (wb_xrom_stb ),
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.wb_xrom_cyc (wb_xrom_cyc ),
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.wb_xrom_cyc (wb_xrom_cyc ),
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// External RAM interface
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// External RAM interface
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.wb_xram_adr (wb_xram_adr ),
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.wb_xram_adr (wb_xram_adr ),
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.wb_xram_ack (wb_xram_ack ),
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.wb_xram_ack (wb_xram_ack ),
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.wb_xram_err (wb_xram_err ),
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.wb_xram_err (wb_xram_err ),
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.wb_xram_wr (wb_xram_wr ),
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.wb_xram_wr (wb_xram_wr ),
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.wb_xram_rdata (wb_xram_rdata ),
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.wb_xram_rdata (wb_xram_rdata ),
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.wb_xram_wdata (wb_xram_wdata ),
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.wb_xram_wdata (wb_xram_wdata ),
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.wb_xram_stb (wb_xram_stb ),
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.wb_xram_stb (wb_xram_stb ),
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.wb_xram_cyc (wb_xram_cyc ),
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.wb_xram_cyc (wb_xram_cyc ),
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`ifdef INTERNAL_ROM
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.ea_in (ea_in ) // internal ROM
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.ea_in (1'b1 ) // internal ROM
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`else
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.ea_in (1'b0 ) // external ROM
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`endif
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);
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);
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oc8051_xrom oc8051_xrom1
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oc8051_xrom oc8051_xrom1
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(
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(
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.rst ( !reset_n ),
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.rst ( !reset_n ),
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.clk ( app_clk ),
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.clk ( app_clk ),
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.addr ( wb_xrom_adr ),
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.addr ( wb_xrom_adr ),
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.data ( wb_xrom_rdata ),
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.data ( wb_xrom_rdata ),
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.stb_i ( wb_xrom_stb ),
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.stb_i ( wb_xrom_stb ),
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.cyc_i ( wb_xrom_cyc ),
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.cyc_i ( wb_xrom_cyc ),
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.ack_o ( wb_xrom_ack )
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.ack_o ( wb_xrom_ack )
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);
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);
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defparam oc8051_xrom1.DELAY = 0;
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defparam oc8051_xrom1.DELAY = 0;
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//
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//
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// external data ram
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// external data ram
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//
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//
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oc8051_xram oc8051_xram1 (
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oc8051_xram oc8051_xram1 (
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.clk (app_clk ),
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.clk (app_clk ),
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.rst (!reset_n ),
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.rst (!reset_n ),
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.wr (wb_xram_wr ),
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.wr (wb_xram_wr ),
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.addr (wb_xram_adr ),
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.addr (wb_xram_adr ),
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.data_in (wb_xram_wdata ),
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.data_in (wb_xram_wdata ),
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.data_out (wb_xram_rdata ),
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.data_out (wb_xram_rdata ),
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.ack (wb_xram_ack ),
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.ack (wb_xram_ack ),
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.stb (wb_xram_stb )
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.stb (wb_xram_stb )
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);
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);
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defparam oc8051_xram1.DELAY = 2;
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defparam oc8051_xram1.DELAY = 2;
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tb_eth_top u_tb_eth (
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tb_eth_top u_tb_eth (
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|
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. REFCLK_50_MHz (ref_clk_50 ), // 50 MHz Reference clock input
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. REFCLK_50_MHz (ref_clk_50 ), // 50 MHz Reference clock input
|
. REFCLK_125_MHz (ref_clk_125 ), // 125 MHz reference clock
|
. REFCLK_125_MHz (ref_clk_125 ), // 125 MHz reference clock
|
. transmit_enable (1'b1 ), // transmit enable for testbench
|
. transmit_enable (1'b1 ), // transmit enable for testbench
|
|
|
// Separate interfaces for each MII port type
|
// Separate interfaces for each MII port type
|
|
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// Full MII, 4-bit interface
|
// Full MII, 4-bit interface
|
// Transmit interface
|
// Transmit interface
|
. MII_RXD (phy_rxd[3:0] ), // Receive data (output)
|
. MII_RXD (phy_rxd[3:0] ), // Receive data (output)
|
. MII_RX_CLK (phy_rx_clk ), // Receive clock for MII (output)
|
. MII_RX_CLK (phy_rx_clk ), // Receive clock for MII (output)
|
. MII_CRS (phy_crs ), // carrier sense (output)
|
. MII_CRS (phy_crs ), // carrier sense (output)
|
. MII_COL ( ), // Collision signal for MII (output)
|
. MII_COL ( ), // Collision signal for MII (output)
|
. MII_RX_DV (phy_rx_dv ), // Receive data valid for MII (output)
|
. MII_RX_DV (phy_rx_dv ), // Receive data valid for MII (output)
|
|
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// Receive interface
|
// Receive interface
|
. MII_TXD (phy_txd[3:0] ), // Transmit data (input)
|
. MII_TXD (phy_txd[3:0] ), // Transmit data (input)
|
. MII_TX_EN (phy_tx_en ), // Tx enable (input)
|
. MII_TX_EN (phy_tx_en ), // Tx enable (input)
|
. MII_TX_CLK (phy_tx_clk ), // Transmit clock (output)
|
. MII_TX_CLK (phy_tx_clk ), // Transmit clock (output)
|
|
|
// Reduced MII, 2-bit interface
|
// Reduced MII, 2-bit interface
|
// Transmit interface
|
// Transmit interface
|
. RMII_RXD ( ), // Receive data (output)
|
. RMII_RXD ( ), // Receive data (output)
|
. RMII_CRS_DV ( ), // carrier sense (output)
|
. RMII_CRS_DV ( ), // carrier sense (output)
|
// Receive interface
|
// Receive interface
|
. RMII_TXD ( ), // Transmit data (input)
|
. RMII_TXD ( ), // Transmit data (input)
|
. RMII_TX_EN ( ), // Tx enable (input)
|
. RMII_TX_EN ( ), // Tx enable (input)
|
|
|
// Serial MII interface
|
// Serial MII interface
|
. SMII_RXD ( ), // Receive data (output)
|
. SMII_RXD ( ), // Receive data (output)
|
. SMII_TXD ( ), // Transmit data (input)
|
. SMII_TXD ( ), // Transmit data (input)
|
. SMII_SYNC ( ), // SMII SYNC signal (input)
|
. SMII_SYNC ( ), // SMII SYNC signal (input)
|
|
|
// GMII, 8-bit/10-bit interface
|
// GMII, 8-bit/10-bit interface
|
// Transmit interface
|
// Transmit interface
|
. GMII_RXD ( ), // Receive data (output)
|
. GMII_RXD ( ), // Receive data (output)
|
. GMII_RX_CLK ( ), // Receive clock for MII (output)
|
. GMII_RX_CLK ( ), // Receive clock for MII (output)
|
. GMII_CRS ( ), // carrier sense (output)
|
. GMII_CRS ( ), // carrier sense (output)
|
. GMII_COL ( ), // Collision signal for MII (output)
|
. GMII_COL ( ), // Collision signal for MII (output)
|
. GMII_RX_DV ( ), // Receive data valid for MII (output)
|
. GMII_RX_DV ( ), // Receive data valid for MII (output)
|
|
|
// Receive interface
|
// Receive interface
|
. GMII_TXD ( ), // Transmit data (input)
|
. GMII_TXD ( ), // Transmit data (input)
|
. GMII_TX_EN ( ), // Tx enable (input)
|
. GMII_TX_EN ( ), // Tx enable (input)
|
. GMII_TX_CLK ( ), // Transmit clock (output)
|
. GMII_TX_CLK ( ), // Transmit clock (output)
|
. GMII_GTX_CLK ( ), // Gigabit Tx clock (input), 125 MHz
|
. GMII_GTX_CLK ( ), // Gigabit Tx clock (input), 125 MHz
|
|
|
// MII management interface
|
// MII management interface
|
.MDIO (MDC ), // serial I/O data
|
.MDIO (MDC ), // serial I/O data
|
.MDC (MDC ) // clock
|
.MDC (MDC ) // clock
|
|
|
|
|
|
|
|
|
);
|
);
|
|
|
uart_agent tb_uart (
|
uart_agent tb_uart (
|
. test_clk (uart_clk_16x ),
|
. test_clk (uart_clk_16x ),
|
. sin (si ),
|
. sin (si ),
|
. dsr_n ( ),
|
. dsr_n ( ),
|
. cts_n ( ),
|
. cts_n ( ),
|
. dcd_n ( ),
|
. dcd_n ( ),
|
|
|
. sout (so ),
|
. sout (so ),
|
. dtr_n (1'b0 ),
|
. dtr_n (1'b0 ),
|
. rts_n (1'b0 ),
|
. rts_n (1'b0 ),
|
. out1_n (1'b0 ),
|
. out1_n (1'b0 ),
|
. out2_n (1'b0 )
|
. out2_n (1'b0 )
|
);
|
);
|
|
|
|
|
//----------------------- SPI Agents
|
//----------------------- SPI Agents
|
|
|
m25p20 i_m25p20_0 (
|
m25p20 i_m25p20_0 (
|
.c (spi_sck ),
|
.c (spi_sck ),
|
.s (spi_cs_n[0] ), // Include selection logic
|
.s (spi_cs_n[0] ), // Include selection logic
|
.w (1'b1 ), // Write protect is always disabled
|
.w (1'b1 ), // Write protect is always disabled
|
.hold (1'b1 ), // Hold support not used
|
.hold (1'b1 ), // Hold support not used
|
.data_in (spi_so ),
|
.data_in (spi_so ),
|
.data_out (spi_si )
|
.data_out (spi_si )
|
);
|
);
|
|
|
|
|
AT45DB321 i_AT45DB321_0 (
|
AT45DB321 i_AT45DB321_0 (
|
.CSB (spi_cs_n[1] ),
|
.CSB (spi_cs_n[1] ),
|
.SCK (spi_sck ),
|
.SCK (spi_sck ),
|
.SI (spi_so ),
|
.SI (spi_so ),
|
.WPB (1'b1 ),
|
.WPB (1'b1 ),
|
.RESETB (1'b1 ),
|
.RESETB (1'b1 ),
|
.RDY_BUSYB ( ),
|
.RDY_BUSYB ( ),
|
.SO (spi_si )
|
.SO (spi_si )
|
);
|
);
|
/***************
|
/***************
|
spi_agent_3120 spi_agent_3120_0 (
|
spi_agent_3120 spi_agent_3120_0 (
|
.cs_b (spi_cs_n[2] ),
|
.cs_b (spi_cs_n[2] ),
|
.spi_din (spi_si ),
|
.spi_din (spi_si ),
|
.spi_dout (spi_so ),
|
.spi_dout (spi_so ),
|
.spi_clk (spi_sck )
|
.spi_clk (spi_sck )
|
);
|
);
|
|
|
spi_agent_3120 spi_agent_3120_1 (
|
spi_agent_3120 spi_agent_3120_1 (
|
.cs_b (spi_cs_n[3] ),
|
.cs_b (spi_cs_n[3] ),
|
.spi_din (spi_si ),
|
.spi_din (spi_si ),
|
.spi_dout (spi_so ),
|
.spi_dout (spi_so ),
|
.spi_clk (spi_sck )
|
.spi_clk (spi_sck )
|
);
|
);
|
*****************/
|
*****************/
|
|
|
tb_glbl tb_glbl ();
|
tb_glbl tb_glbl ();
|
|
|
|
|
initial begin
|
initial begin
|
if ( $test$plusargs("DUMP") ) begin
|
if ( $test$plusargs("DUMP") ) begin
|
$fsdbDumpfile("../dump/test_1.fsdb");
|
$fsdbDumpfile("../dump/test_1.fsdb");
|
$fsdbDumpvars;
|
$fsdbDumpvars;
|
$fsdbDumpon;
|
$fsdbDumpon;
|
end
|
end
|
end
|
end
|
|
|
initial begin
|
initial begin
|
|
|
|
if ( $test$plusargs("INTERNAL_ROM") ) begin
|
|
ea_in = 1;
|
|
master_mode = 1;
|
|
end else if ( $test$plusargs("EXTERNAL_ROM") ) begin
|
|
ea_in = 0;
|
|
master_mode = 1;
|
|
end else begin
|
|
ea_in = 0;
|
|
master_mode = 0;
|
|
end
|
|
|
`TB_GLBL.init;
|
`TB_GLBL.init;
|
#1000 wait(reset_out_n == 1);
|
#1000 wait(reset_out_n == 1);
|
|
|
if ( $test$plusargs("gmac_test_1") )
|
if ( $test$plusargs("gmac_test_1") )
|
gmac_test1();
|
gmac_test1();
|
else if ( $test$plusargs("uart_test_1") )
|
else if ( $test$plusargs("uart_test_1") )
|
uart_test1();
|
uart_test1();
|
else if ( $test$plusargs("spi_test_1") )
|
else if ( $test$plusargs("spi_test_1") )
|
spi_test1();
|
spi_test1();
|
else begin
|
else begin
|
// 8051 Test Cases
|
// 8051 Test Cases
|
#80000000
|
#80000000
|
$display("time ",$time, "\n faulire: end of time\n \n");
|
$display("time ",$time, "\n faulire: end of time\n \n");
|
end
|
end
|
|
|
`TB_GLBL.test_stats;
|
`TB_GLBL.test_stats;
|
`TB_GLBL.test_finish;
|
`TB_GLBL.test_finish;
|
#1000 $finish;
|
#1000 $finish;
|
end
|
end
|
|
|
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
|
wire [7:0] p2_out = u_core.u_8051_core.p2_o;
|
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
|
wire [7:0] p3_out = u_core.u_8051_core.p3_o;
|
always @(p2_out or p3_out)
|
always @(p2_out or p3_out)
|
begin
|
begin
|
if((p2_out == 8'haa) && // fib.c
|
if((p2_out == 8'haa) && // fib.c
|
(p3_out == 8'haa )) begin
|
(p3_out == 8'haa )) begin
|
$display("################################");
|
$display("################################");
|
$display("time ",$time, " Passed");
|
$display("time ",$time, " Passed");
|
$display("################################");
|
$display("################################");
|
#100
|
#100
|
$finish;
|
$finish;
|
end else if(p2_out == 8'h55) begin // fib.c
|
end else if(p2_out == 8'h55) begin // fib.c
|
$display("");
|
$display("");
|
$display("time ",$time," Error: %h", p3_out);
|
$display("time ",$time," Error: %h", p3_out);
|
$display("");
|
$display("");
|
#100
|
#100
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
`include "gmac_test1.v"
|
`include "gmac_test1.v"
|
`include "uart_test1.v"
|
`include "uart_test1.v"
|
`include "spi_test1.v"
|
`include "spi_test1.v"
|
`include "tb_tasks.v"
|
`include "tb_tasks.v"
|
`include "spi_tasks.v"
|
`include "spi_tasks.v"
|
|
|
|
|
endmodule
|
endmodule
|
`include "tb_glbl.v"
|
`include "tb_glbl.v"
|
|
|