`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
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`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
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module tb_top;
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module tb_top;
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reg clk;
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reg clk;
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reg reset_n;
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reg reset_n;
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reg wait_n;
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reg wait_n;
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reg int_n;
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reg int_n;
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reg nmi_n;
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reg nmi_n;
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reg busrq_n;
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reg busrq_n;
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wire m1_n;
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wire m1_n;
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wire mreq_n;
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wire mreq_n;
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wire iorq_n;
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wire iorq_n;
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wire rd_n;
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wire rd_n;
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wire wr_n;
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wire wr_n;
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wire rfsh_n;
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wire rfsh_n;
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wire halt_n;
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wire halt_n;
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wire busak_n;
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wire busak_n;
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wire [15:0] A;
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wire [15:0] A;
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wire [7:0] di;
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wire [7:0] di;
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wire [7:0] do;
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wire [7:0] do;
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wire ram_rd_cs, ram_wr_cs, rom_rd_cs;
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wire ram_rd_cs, ram_wr_cs, rom_rd_cs;
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always
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always
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begin
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begin
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clk = 1;
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clk = 1;
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#5;
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#5;
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clk = 0;
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clk = 0;
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#5;
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#5;
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end
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end
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assign rom_rd_cs = !mreq_n & !rd_n & !A[15];
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assign rom_rd_cs = !mreq_n & !rd_n & !A[15];
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assign ram_rd_cs = !mreq_n & !rd_n & A[15];
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assign ram_rd_cs = !mreq_n & !rd_n & A[15];
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assign ram_wr_cs = !mreq_n & !wr_n & A[15];
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assign ram_wr_cs = !mreq_n & !wr_n & A[15];
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tv80s tv80s_inst
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tv80s tv80s_inst
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(
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(
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// Outputs
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// Outputs
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.m1_n (m1_n),
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.m1_n (m1_n),
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.mreq_n (mreq_n),
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.mreq_n (mreq_n),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.rfsh_n (rfsh_n),
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.rfsh_n (rfsh_n),
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.halt_n (halt_n),
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.halt_n (halt_n),
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.busak_n (busak_n),
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.busak_n (busak_n),
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.A (A[15:0]),
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.A (A[15:0]),
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.do (do[7:0]),
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.do (do[7:0]),
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// Inputs
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// Inputs
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.reset_n (reset_n),
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.reset_n (reset_n),
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.clk (clk),
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.clk (clk),
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.wait_n (wait_n),
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.wait_n (wait_n),
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.int_n (int_n),
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.int_n (int_n),
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.nmi_n (nmi_n),
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.nmi_n (nmi_n),
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.busrq_n (busrq_n),
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.busrq_n (busrq_n),
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.di (di[7:0]));
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.di (di[7:0]));
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async_mem ram
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async_mem ram
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(
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(
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// Outputs
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// Outputs
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.rd_data (di),
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.rd_data (di),
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// Inputs
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// Inputs
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.wr_clk (clk),
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.wr_clk (clk),
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.wr_data (do),
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.wr_data (do),
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.wr_cs (ram_wr_cs),
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.wr_cs (ram_wr_cs),
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.addr (A[14:0]),
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.addr (A[14:0]),
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.rd_cs (ram_rd_cs));
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.rd_cs (ram_rd_cs));
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async_mem rom
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async_mem rom
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(
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(
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// Outputs
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// Outputs
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.rd_data (di),
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.rd_data (di),
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// Inputs
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// Inputs
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.wr_clk (),
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.wr_clk (),
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.wr_data (),
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.wr_data (),
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.wr_cs (1'b0),
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.wr_cs (1'b0),
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.addr (A[14:0]),
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.addr (A[14:0]),
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.rd_cs (rom_rd_cs));
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.rd_cs (rom_rd_cs));
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env_io env_io_inst
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env_io env_io_inst
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(
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(
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// Outputs
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// Outputs
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.DI (di[7:0]),
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.DI (di[7:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.addr (A[7:0]),
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.addr (A[7:0]),
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.DO (do[7:0]));
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.DO (do[7:0]));
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initial
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initial
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begin
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begin
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clear_ram;
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clear_ram;
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reset_n = 0;
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reset_n = 0;
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wait_n = 1;
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wait_n = 1;
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int_n = 1;
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int_n = 1;
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nmi_n = 1;
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nmi_n = 1;
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busrq_n = 1;
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busrq_n = 1;
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$readmemh (`PROGRAM_FILE, tb_top.rom.mem);
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$readmemh (`PROGRAM_FILE, tb_top.rom.mem);
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repeat (20) @(negedge clk);
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repeat (20) @(negedge clk);
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reset_n = 1;
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reset_n = 1;
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end // initial begin
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end // initial begin
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`ifdef DUMP_START
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`ifdef DUMP_START
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always
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always
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begin
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begin
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if ($time > `DUMP_START)
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if ($time > `DUMP_START)
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dumpon;
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dumpon;
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#100;
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#100;
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end
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end
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`endif
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`endif
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/*
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/*
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always
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always
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begin
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begin
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while (mreq_n) @(posedge clk);
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while (mreq_n) @(posedge clk);
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wait_n <= #1 0;
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wait_n <= #1 0;
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@(posedge clk);
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@(posedge clk);
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wait_n <= #1 1;
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wait_n <= #1 1;
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while (!mreq_n) @(posedge clk);
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while (!mreq_n) @(posedge clk);
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end
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end
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*/
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*/
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`ifdef TV80_INSTRUCTION_DECODE
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`ifdef TV80_INSTRUCTION_DECODE
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reg [7:0] state;
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reg [7:0] state;
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initial
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initial
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state = 0;
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state = 0;
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always @(posedge clk)
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always @(posedge clk)
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begin : inst_decode
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begin : inst_decode
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if ((`TV80_CORE_PATH.mcycle[6:0] == 1) &&
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if ((`TV80_CORE_PATH.mcycle[6:0] == 1) &&
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(`TV80_CORE_PATH.tstate[6:0] == 8))
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(`TV80_CORE_PATH.tstate[6:0] == 8))
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begin
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begin
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op_decode.decode (`TV80_CORE_PATH.IR[7:0], state);
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op_decode.decode (`TV80_CORE_PATH.IR[7:0], state);
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end
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end
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else if (`TV80_CORE_PATH.mcycle[6:0] != 1)
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else if (`TV80_CORE_PATH.mcycle[6:0] != 1)
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state = 0;
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state = 0;
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end
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end
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`endif
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`endif
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`include "env_tasks.v"
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`include "env_tasks.v"
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endmodule // tb_top
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endmodule // tb_top
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