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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
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<table summary="layout" width="66%" border="0" cellpadding="0" cellspacing="0"><tr><td><table summary="layout" width="100%" border="0" cellpadding="2" cellspacing="1">
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<tr><td class="header">$Revision: 1.3 $</td><td class="header">G. Hutchison</td></tr>
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<tr><td class="header">$Revision: 1.3 $</td><td class="header">G. Hutchison</td></tr>
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<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
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<tr><td class="header"> </td><td class="header">OpenCores.org</td></tr>
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<tr><td class="header"> </td><td class="header">October 2004</td></tr>
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<tr><td class="header"> </td><td class="header">October 2004</td></tr>
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</table></td></tr></table>
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</table></td></tr></table>
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<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
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<div align="right"><span class="title"><br />tv80 Core Documentation</span></div>
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<h3>Abstract</h3>
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<h3>Abstract</h3>
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|
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<p>
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<p>
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A synthesizable 8-bit microprocessor which is instruction-set compatable
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A synthesizable 8-bit microprocessor which is instruction-set compatable
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with the Z80, targetted at embedded and system-on-a-chip designs.
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with the Z80, targetted at embedded and system-on-a-chip designs.
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</p><a name="toc"></a><br /><hr />
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</p><a name="toc"></a><br /><hr />
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<h3>Table of Contents</h3>
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<h3>Table of Contents</h3>
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<p class="toc">
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<p class="toc">
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<a href="#anchor1">1.</a>
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<a href="#anchor1">1.</a>
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Background<br />
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Background<br />
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<a href="#anchor2">2.</a>
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<a href="#anchor2">2.</a>
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Core Area and Technology Mapping<br />
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Core Area and Technology Mapping<br />
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<a href="#anchor3">3.</a>
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<a href="#anchor3">3.</a>
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TV80 Peripherals<br />
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TV80 Peripherals<br />
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<a href="#anchor4">3.1</a>
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<a href="#anchor4">3.1</a>
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Simple GMII Interface<br />
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Simple GMII Interface<br />
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<a href="#anchor5">3.1.1</a>
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<a href="#anchor5">3.1.1</a>
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Register Interface<br />
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Register Interface<br />
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<a href="#anchor12">4.</a>
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<a href="#anchor12">4.</a>
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Verification Environment<br />
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Verification Environment<br />
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<a href="#anchor13">4.1</a>
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<a href="#anchor13">4.1</a>
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Memory Map<br />
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Memory Map<br />
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<a href="#anchor14">4.2</a>
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<a href="#anchor14">4.2</a>
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Control Registers<br />
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Control Registers<br />
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<a href="#anchor15">4.2.1</a>
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<a href="#anchor15">4.2.1</a>
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Simulation control (0x80)<br />
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Simulation control (0x80)<br />
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<a href="#anchor16">4.2.2</a>
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<a href="#anchor16">4.2.2</a>
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Message output (0x81)<br />
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Message output (0x81)<br />
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<a href="#anchor17">4.2.3</a>
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<a href="#anchor17">4.2.3</a>
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Timeout control (0x82)<br />
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Timeout control (0x82)<br />
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<a href="#anchor18">4.2.4</a>
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<a href="#anchor18">4.2.4</a>
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Max timeout (0x84, 0x83)<br />
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Max timeout (0x84, 0x83)<br />
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<a href="#anchor19">4.2.5</a>
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<a href="#anchor19">4.2.5</a>
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Interrupt countdown (0x90)<br />
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Interrupt countdown (0x90)<br />
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<a href="#anchor20">4.2.6</a>
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<a href="#anchor20">4.2.6</a>
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Checksum value (0x91)<br />
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Checksum value (0x91)<br />
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<a href="#anchor21">4.2.7</a>
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<a href="#anchor21">4.2.7</a>
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Checksum accumulate (0x92)<br />
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Checksum accumulate (0x92)<br />
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<a href="#anchor22">4.2.8</a>
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<a href="#anchor22">4.2.8</a>
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Increment on read (0x93)<br />
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Increment on read (0x93)<br />
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<a href="#anchor23">4.3</a>
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<a href="#anchor23">4.3</a>
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Tool Chain<br />
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Tool Chain<br />
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<a href="#anchor24">4.4</a>
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<a href="#anchor24">4.4</a>
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Tests<br />
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Tests<br />
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<a href="#tvs80">4.4.1</a>
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<a href="#tvs80">4.4.1</a>
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tvs80 test<br />
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tvs80 test<br />
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<a href="#rfc.references1">5.</a>
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<a href="#rfc.references1">5.</a>
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References<br />
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References<br />
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<a href="#rfc.authors">§</a>
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<a href="#rfc.authors">§</a>
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Author's Address<br />
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Author's Address<br />
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</p>
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</p>
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<br clear="all" />
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<br clear="all" />
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<a name="anchor1"></a><br /><hr />
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<a name="anchor1"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<a name="rfc.section.1"></a><h3>1. Background</h3>
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<a name="rfc.section.1"></a><h3>1. Background</h3>
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<p>The tv80 core was created as a Verilog port of the <a class="info" href="#t80">VHDL T80 core<span>Wallner, D., VHDL T80 Core, .</span></a>[1], for use as a maintenence processor inside an ASIC.
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<p>The tv80 core was created as a Verilog port of the <a class="info" href="#t80">VHDL T80 core<span>Wallner, D., VHDL T80 Core, .</span></a>[1], for use as a maintenence processor inside an ASIC.
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The tv80 has been modified since then for better synthesis
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The tv80 has been modified since then for better synthesis
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timing/area results, and to incorporate several bug-fixes.
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timing/area results, and to incorporate several bug-fixes.
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</p>
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</p>
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<p>The T80, and the tv80 derived from it, attempt to maintain the
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<p>The T80, and the tv80 derived from it, attempt to maintain the
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original cycle timings of the Z80, but have radically different
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original cycle timings of the Z80, but have radically different
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internal designs and timings. With its target being ASIC and
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internal designs and timings. With its target being ASIC and
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embedded applications, the tv80 does not attempt to maintain
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embedded applications, the tv80 does not attempt to maintain
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the original pinout of the Z80.
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the original pinout of the Z80.
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</p>
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</p>
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<a name="anchor2"></a><br /><hr />
|
<a name="anchor2"></a><br /><hr />
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<a name="rfc.section.2"></a><h3>2. Core Area and Technology Mapping</h3>
|
<a name="rfc.section.2"></a><h3>2. Core Area and Technology Mapping</h3>
|
|
|
<p> This section tracks synthesis results in various technologies. LSI 10K technology is
|
<p> This section tracks synthesis results in various technologies. LSI 10K technology is
|
used as a baseline because the library ships with Design Compiler.
|
used as a baseline because the library ships with Design Compiler.
|
</p><pre>
|
</p><pre>
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Component Clock Speed Area Technology (units)
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Component Clock Speed Area Technology (units)
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================ =========== ======== =====================
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================ =========== ======== =====================
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tv80 33 Mhz 10733 lsi_10k (gates)
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tv80 33 Mhz 10733 lsi_10k (gates)
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simple_gmii 33 Mhz 1247 lsi_10k (gates)
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simple_gmii 33 Mhz 1247 lsi_10k (gates)
|
</pre>
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</pre>
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|
|
<a name="anchor3"></a><br /><hr />
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<a name="anchor3"></a><br /><hr />
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
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<a name="rfc.section.3"></a><h3>3. TV80 Peripherals</h3>
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<a name="rfc.section.3"></a><h3>3. TV80 Peripherals</h3>
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|
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<p>The TV80 design includes a number (one, at this point) of peripherals. These peripherals
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<p>The TV80 design includes a number (one, at this point) of peripherals. These peripherals
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are hardware-synthesizable, but may not be fully tested or functional.
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are hardware-synthesizable, but may not be fully tested or functional.
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</p>
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</p>
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<a name="rfc.section.3.1"></a><h4><a name="anchor4">3.1</a> Simple GMII Interface</h4>
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<a name="rfc.section.3.1"></a><h4><a name="anchor4">3.1</a> Simple GMII Interface</h4>
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|
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<p>This block presents a GMII interface on one side and a TV80 processor interface on
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<p>This block presents a GMII interface on one side and a TV80 processor interface on
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the other. The processor-side controls are all mapped into I/O-space. The block
|
the other. The processor-side controls are all mapped into I/O-space. The block
|
can only process a single packet in each direction at one time. This is only really
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can only process a single packet in each direction at one time. This is only really
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a limitation on the RX side, where any incoming packets will be dropped until the
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a limitation on the RX side, where any incoming packets will be dropped until the
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processor removes the first packet from the RX buffer.
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processor removes the first packet from the RX buffer.
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</p>
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</p>
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<p>The GMII interface is signalling only, and does not support 10/100 operation, half duplex
|
<p>The GMII interface is signalling only, and does not support 10/100 operation, half duplex
|
mode, flow control, or any other aspects of 802.3.
|
mode, flow control, or any other aspects of 802.3.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1"></a><h4><a name="anchor5">3.1.1</a> Register Interface</h4>
|
<a name="rfc.section.3.1.1"></a><h4><a name="anchor5">3.1.1</a> Register Interface</h4>
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|
|
<p>This block consumes 3 bits of I/O address space. The register addresses below are
|
<p>This block consumes 3 bits of I/O address space. The register addresses below are
|
relative to the configurable base address of the block, which must be aligned to an
|
relative to the configurable base address of the block, which must be aligned to an
|
8-byte boundary. Registers 0x6 and 0x7 are reserved.
|
8-byte boundary. Registers 0x6 and 0x7 are reserved.
|
</p>
|
</p>
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<a name="rfc.section.3.1.1.1"></a><h4><a name="anchor6">3.1.1.1</a> Status Register (0x0)</h4>
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<a name="rfc.section.3.1.1.1"></a><h4><a name="anchor6">3.1.1.1</a> Status Register (0x0)</h4>
|
|
|
<p>Bit 0 of the status register indicates that a packet is available in the RX buffer.
|
<p>Bit 0 of the status register indicates that a packet is available in the RX buffer.
|
This bit will be cleared when the last byte of data is read out of the RX buffer.
|
This bit will be cleared when the last byte of data is read out of the RX buffer.
|
</p>
|
</p>
|
<p>Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit
|
<p>Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit
|
will be cleared when the first byte of data of the next packet is written into the
|
will be cleared when the first byte of data of the next packet is written into the
|
TX buffer.
|
TX buffer.
|
</p>
|
</p>
|
<p>This register is read-only.
|
<p>This register is read-only.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1.2"></a><h4><a name="anchor7">3.1.1.2</a> Control Register (0x1)</h4>
|
<a name="rfc.section.3.1.1.2"></a><h4><a name="anchor7">3.1.1.2</a> Control Register (0x1)</h4>
|
|
|
<p>Bit 0 controls sending packets. When a 1 is written to this bit, the data in
|
<p>Bit 0 controls sending packets. When a 1 is written to this bit, the data in
|
the TX buffer will be sent as a single packet.
|
the TX buffer will be sent as a single packet.
|
</p>
|
</p>
|
<p>This register is write-only.
|
<p>This register is write-only.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1.3"></a><h4><a name="anchor8">3.1.1.3</a> RX Length Register (Low, 0x2)</h4>
|
<a name="rfc.section.3.1.1.3"></a><h4><a name="anchor8">3.1.1.3</a> RX Length Register (Low, 0x2)</h4>
|
|
|
<p>This register contains the low 8 bits of the length of the packet currently
|
<p>This register contains the low 8 bits of the length of the packet currently
|
residing in the RX buffer.
|
residing in the RX buffer.
|
</p>
|
</p>
|
<p>This register is read-only.
|
<p>This register is read-only.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1.4"></a><h4><a name="anchor9">3.1.1.4</a> RX Length Register (High, 0x3)</h4>
|
<a name="rfc.section.3.1.1.4"></a><h4><a name="anchor9">3.1.1.4</a> RX Length Register (High, 0x3)</h4>
|
|
|
<p>This register contains the high 8 bits of the length of the packet currently
|
<p>This register contains the high 8 bits of the length of the packet currently
|
residing in the RX buffer.
|
residing in the RX buffer.
|
</p>
|
</p>
|
<p>This register is read-only.
|
<p>This register is read-only.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1.5"></a><h4><a name="anchor10">3.1.1.5</a> RX Data Register (0x4)</h4>
|
<a name="rfc.section.3.1.1.5"></a><h4><a name="anchor10">3.1.1.5</a> RX Data Register (0x4)</h4>
|
|
|
<p>This register contains the next byte of data in the RX packet buffer.
|
<p>This register contains the next byte of data in the RX packet buffer.
|
</p>
|
</p>
|
<p>This register is read-only.
|
<p>This register is read-only.
|
</p>
|
</p>
|
<a name="rfc.section.3.1.1.6"></a><h4><a name="anchor11">3.1.1.6</a> TX Data Register (0x5)</h4>
|
<a name="rfc.section.3.1.1.6"></a><h4><a name="anchor11">3.1.1.6</a> TX Data Register (0x5)</h4>
|
|
|
<p>Writing to this register puts data in the TX packet buffer. This register does
|
<p>Writing to this register puts data in the TX packet buffer. This register does
|
not perform bounds checking; it is the program's responsibility not to write more
|
not perform bounds checking; it is the program's responsibility not to write more
|
data than the size of the TX buffer.
|
data than the size of the TX buffer.
|
</p>
|
</p>
|
<p>This register is write-only.
|
<p>This register is write-only.
|
</p>
|
</p>
|
<a name="anchor12"></a><br /><hr />
|
<a name="anchor12"></a><br /><hr />
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<a name="rfc.section.4"></a><h3>4. Verification Environment</h3>
|
<a name="rfc.section.4"></a><h3>4. Verification Environment</h3>
|
|
|
<a name="rfc.section.4.1"></a><h4><a name="anchor13">4.1</a> Memory Map</h4>
|
<a name="rfc.section.4.1"></a><h4><a name="anchor13">4.1</a> Memory Map</h4>
|
|
|
<p>
|
<p>
|
Environment memory space is divided into a 32k ROM region and a 32k RAM
|
Environment memory space is divided into a 32k ROM region and a 32k RAM
|
region, as follows:
|
region, as follows:
|
|
|
</p>
|
</p>
|
<pre>
|
<pre>
|
0000-7FFF: ROM
|
0000-7FFF: ROM
|
8000-FFFF: RAM
|
8000-FFFF: RAM
|
</pre>
|
</pre>
|
<p>
|
<p>
|
|
|
<p>Environment I/O space is allocated as follows:
|
<p>Environment I/O space is allocated as follows:
|
</p><pre>
|
</p><pre>
|
00-0F: Unused
|
00-0F: Unused
|
10-1F: Test devices
|
10-1F: Test devices
|
20-7F: Unused
|
20-7F: Unused
|
80-9F: Environment control
|
80-9F: Environment control
|
A0-FF: Unused
|
A0-FF: Unused
|
</pre>
|
</pre>
|
|
|
|
|
<a name="rfc.section.4.2"></a><h4><a name="anchor14">4.2</a> Control Registers</h4>
|
<a name="rfc.section.4.2"></a><h4><a name="anchor14">4.2</a> Control Registers</h4>
|
|
|
<a name="rfc.section.4.2.1"></a><h4><a name="anchor15">4.2.1</a> Simulation control (0x80)</h4>
|
<a name="rfc.section.4.2.1"></a><h4><a name="anchor15">4.2.1</a> Simulation control (0x80)</h4>
|
|
|
<ul class="text">
|
<ul class="text">
|
<li> Write '01' to end simulation with test passed
|
<li> Write '01' to end simulation with test passed
|
</li>
|
</li>
|
<li> Write '02' to end with test failed
|
<li> Write '02' to end with test failed
|
</li>
|
</li>
|
<li> Write '03' to turn on dumping
|
<li> Write '03' to turn on dumping
|
</li>
|
</li>
|
<li> Write '04' to turn off dumping
|
<li> Write '04' to turn off dumping
|
</li>
|
</li>
|
</ul>
|
</ul>
|
<a name="rfc.section.4.2.2"></a><h4><a name="anchor16">4.2.2</a> Message output (0x81)</h4>
|
<a name="rfc.section.4.2.2"></a><h4><a name="anchor16">4.2.2</a> Message output (0x81)</h4>
|
|
|
<p>
|
<p>
|
Write characters to this port one at a time. When the
|
Write characters to this port one at a time. When the
|
newline ('\n', ASCII 0x0A) character is written, the
|
newline ('\n', ASCII 0x0A) character is written, the
|
environment will print out the collected string.
|
environment will print out the collected string.
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.2.3"></a><h4><a name="anchor17">4.2.3</a> Timeout control (0x82)</h4>
|
<a name="rfc.section.4.2.3"></a><h4><a name="anchor17">4.2.3</a> Timeout control (0x82)</h4>
|
|
|
<p>
|
<p>
|
Bit[0] enables the timeout counter,
|
Bit[0] enables the timeout counter,
|
Bit[1] resets the counter to 0.
|
Bit[1] resets the counter to 0.
|
Timeout counter defaults to enabled at simulation start.
|
Timeout counter defaults to enabled at simulation start.
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.2.4"></a><h4><a name="anchor18">4.2.4</a> Max timeout (0x84, 0x83)</h4>
|
<a name="rfc.section.4.2.4"></a><h4><a name="anchor18">4.2.4</a> Max timeout (0x84, 0x83)</h4>
|
|
|
<p>
|
<p>
|
Holds 16-bit timeout value (amount of time in clocks before
|
Holds 16-bit timeout value (amount of time in clocks before
|
timeout error occurs).
|
timeout error occurs).
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.2.5"></a><h4><a name="anchor19">4.2.5</a> Interrupt countdown (0x90)</h4>
|
<a name="rfc.section.4.2.5"></a><h4><a name="anchor19">4.2.5</a> Interrupt countdown (0x90)</h4>
|
|
|
<p>
|
<p>
|
When set, starts a countdown (in clocks) until assertion of
|
When set, starts a countdown (in clocks) until assertion of
|
the INT_N signal.
|
the INT_N signal.
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.2.6"></a><h4><a name="anchor20">4.2.6</a> Checksum value (0x91)</h4>
|
<a name="rfc.section.4.2.6"></a><h4><a name="anchor20">4.2.6</a> Checksum value (0x91)</h4>
|
|
|
<p>This register holds the checksum value of all data
|
<p>This register holds the checksum value of all data
|
written to the accumulate register. The checksum is a simple
|
written to the accumulate register. The checksum is a simple
|
twos-complement checksum, so it can be compared with a CPU-generated
|
twos-complement checksum, so it can be compared with a CPU-generated
|
checksum.
|
checksum.
|
</p>
|
</p>
|
<p>This register is readable and writeable. Writing the register sets
|
<p>This register is readable and writeable. Writing the register sets
|
the current checksum value.
|
the current checksum value.
|
</p>
|
</p>
|
<a name="rfc.section.4.2.7"></a><h4><a name="anchor21">4.2.7</a> Checksum accumulate (0x92)</h4>
|
<a name="rfc.section.4.2.7"></a><h4><a name="anchor21">4.2.7</a> Checksum accumulate (0x92)</h4>
|
|
|
<p>This write-only register adds the written value to the value
|
<p>This write-only register adds the written value to the value
|
contained in the Checksum Value register.
|
contained in the Checksum Value register.
|
</p>
|
</p>
|
<a name="rfc.section.4.2.8"></a><h4><a name="anchor22">4.2.8</a> Increment on read (0x93)</h4>
|
<a name="rfc.section.4.2.8"></a><h4><a name="anchor22">4.2.8</a> Increment on read (0x93)</h4>
|
|
|
<p>This register increments every time it is read, so reading it
|
<p>This register increments every time it is read, so reading it
|
repeatedly generates an incrementing sequence. It can be reset
|
repeatedly generates an incrementing sequence. It can be reset
|
by writing it to a new starting value.
|
by writing it to a new starting value.
|
</p>
|
</p>
|
<a name="rfc.section.4.3"></a><h4><a name="anchor23">4.3</a> Tool Chain</h4>
|
<a name="rfc.section.4.3"></a><h4><a name="anchor23">4.3</a> Tool Chain</h4>
|
|
|
<p>The minimum toolchain required to simulate the tv80 is the
|
<p>The minimum toolchain required to simulate the tv80 is the
|
<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
|
<a class="info" href="#cver">CVer<span>Vanvick, A., GPL Cver Simulator, .</span></a>[3] Verilog simulator, and the
|
<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
|
<a class="info" href="#sdcc">SDCC<span>, Small Device C Compiler, .</span></a>[2] compiler/assembler/linker. In
|
addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
|
addition, to run the <a class="info" href="#tvs80">tvs80<span>tvs80 test</span></a> instruction
|
test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
|
test suite, the <a class="info" href="#dosbox">DOSBox<span>, DOSBox, .</span></a>[4] DOS emulator
|
is required.
|
is required.
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.4"></a><h4><a name="anchor24">4.4</a> Tests</h4>
|
<a name="rfc.section.4.4"></a><h4><a name="anchor24">4.4</a> Tests</h4>
|
|
|
<p>Most of the tests in the tv80 environment are written in C, and should
|
<p>Most of the tests in the tv80 environment are written in C, and should
|
be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
|
be compiled with the <a class="info" href="#sdcc">sdcc<span>, Small Device C Compiler, .</span></a>[2] compiler.
|
|
|
</p>
|
</p>
|
<a name="rfc.section.4.4.1"></a><h4><a name="tvs80">4.4.1</a> tvs80 test</h4>
|
<a name="rfc.section.4.4.1"></a><h4><a name="tvs80">4.4.1</a> tvs80 test</h4>
|
|
|
<p>The tvs80 test is different than the rest of the tests, and is
|
<p>The tvs80 test is different than the rest of the tests, and is
|
written in its own flavor of assembly language. This test provides
|
written in its own flavor of assembly language. This test provides
|
a fairly comprehensive Z80 instruction test.
|
a fairly comprehensive Z80 instruction test.
|
</p>
|
</p>
|
<p>The assembler for this test only runs under DOS. To assemble
|
<p>The assembler for this test only runs under DOS. To assemble
|
under Unix/Linux, the <a class="info" href="#dosbox">"dosbox" DOS emulator<span>, DOSBox, .</span></a>[4] is required. A script
|
under Unix/Linux, the <a class="info" href="#dosbox">"dosbox" DOS emulator<span>, DOSBox, .</span></a>[4] is required. A script
|
to run the assembler under dosbox, as well as the tvs80.asm source,
|
to run the assembler under dosbox, as well as the tvs80.asm source,
|
is checked in under the "tests/tvs80" directory.
|
is checked in under the "tests/tvs80" directory.
|
</p>
|
</p>
|
<a name="rfc.references1"></a><br /><hr />
|
<a name="rfc.references1"></a><br /><hr />
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<h3>5 References</h3>
|
<h3>5 References</h3>
|
<table width="99%" border="0">
|
<table width="99%" border="0">
|
<tr><td class="author-text" valign="top"><a name="t80">[1]</a></td>
|
<tr><td class="author-text" valign="top"><a name="t80">[1]</a></td>
|
<td class="author-text">Wallner, D., "<a href="http://www.opencores.org/projects.cgi/web/t80/overview">VHDL T80 Core</a>".</td></tr>
|
<td class="author-text">Wallner, D., "<a href="http://www.opencores.org/projects.cgi/web/t80/overview">VHDL T80 Core</a>".</td></tr>
|
<tr><td class="author-text" valign="top"><a name="sdcc">[2]</a></td>
|
<tr><td class="author-text" valign="top"><a name="sdcc">[2]</a></td>
|
<td class="author-text">"<a href="http://sdcc.sourceforge.net">Small Device C Compiler</a>".</td></tr>
|
<td class="author-text">"<a href="http://sdcc.sourceforge.net">Small Device C Compiler</a>".</td></tr>
|
<tr><td class="author-text" valign="top"><a name="cver">[3]</a></td>
|
<tr><td class="author-text" valign="top"><a name="cver">[3]</a></td>
|
<td class="author-text">Vanvick, A., "<a href="http://www.pragmatic-c.com/gpl-cver">GPL Cver Simulator</a>".</td></tr>
|
<td class="author-text">Vanvick, A., "<a href="http://www.pragmatic-c.com/gpl-cver">GPL Cver Simulator</a>".</td></tr>
|
<tr><td class="author-text" valign="top"><a name="dosbox">[4]</a></td>
|
<tr><td class="author-text" valign="top"><a name="dosbox">[4]</a></td>
|
<td class="author-text">"<a href="http://dosbox.sourceforge.net">DOSBox</a>".</td></tr>
|
<td class="author-text">"<a href="http://dosbox.sourceforge.net">DOSBox</a>".</td></tr>
|
</table>
|
</table>
|
|
|
<a name="rfc.authors"></a><br /><hr />
|
<a name="rfc.authors"></a><br /><hr />
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<table summary="layout" cellpadding="0" cellspacing="2" class="bug" align="right"><tr><td class="bug"><a href="#toc" class="link2"> TOC </a></td></tr></table>
|
<h3>Author's Address</h3>
|
<h3>Author's Address</h3>
|
<table width="99%" border="0" cellpadding="0" cellspacing="0">
|
<table width="99%" border="0" cellpadding="0" cellspacing="0">
|
<tr><td class="author-text"> </td>
|
<tr><td class="author-text"> </td>
|
<td class="author-text">Guy Hutchison</td></tr>
|
<td class="author-text">Guy Hutchison</td></tr>
|
<tr><td class="author-text"> </td>
|
<tr><td class="author-text"> </td>
|
<td class="author-text">OpenCores.org</td></tr>
|
<td class="author-text">OpenCores.org</td></tr>
|
<tr><td class="author" align="right">EMail: </td>
|
<tr><td class="author" align="right">EMail: </td>
|
<td class="author-text"><a href="mailto:ghutchis@opencores.org">ghutchis@opencores.org</a></td></tr>
|
<td class="author-text"><a href="mailto:ghutchis@opencores.org">ghutchis@opencores.org</a></td></tr>
|
</table>
|
</table>
|
</body></html>
|
</body></html>
|
|
|
