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TV80 Microprocessor Core Environment Documentation
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TV80 Microprocessor Core Environment Documentation
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Environment Memory Map:
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Environment Memory Map:
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Environment memory space is divided into a 32k ROM region and a 32k RAM
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Environment memory space is divided into a 32k ROM region and a 32k RAM
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region, as follows:
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region, as follows:
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0000-7FFF: ROM
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0000-7FFF: ROM
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8000-FFFF: RAM
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8000-FFFF: RAM
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Environment I/O space is allocated as follows:
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Environment I/O space is allocated as follows:
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00-0F: Unused
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00-0F: Unused
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10-1F: Test devices
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10-1F: Test devices
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20-7F: Unused
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20-7F: Unused
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80-8F: Environment control
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80-8F: Environment control
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A0-FF: Unused
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A0-FF: Unused
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The Environment control registers are:
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The Environment control registers are:
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80 : Simulation control
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80 : Simulation control
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Write '01' to end simulation with test passed
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Write '01' to end simulation with test passed
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Write '02' to end with test failed
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Write '02' to end with test failed
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Write '03' to turn on dumping
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Write '03' to turn on dumping
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Write '04' to turn off dumping
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Write '04' to turn off dumping
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81 : Message output
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81 : Message output
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Write characters to this port one at a time. When the
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Write characters to this port one at a time. When the
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newline ('\n', ASCII 0x0A) character is written, the
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newline ('\n', ASCII 0x0A) character is written, the
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environment will print out the collected string.
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environment will print out the collected string.
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82 : Timeout control
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82 : Timeout control
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Bit[0] enables the timeout counter
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Bit[0] enables the timeout counter
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Bit[1] resets the counter to 0
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Bit[1] resets the counter to 0
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Timeout counter defaults to enabled at simulation start
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Timeout counter defaults to enabled at simulation start
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83 : Max timeout [low]
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83 : Max timeout [low]
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84 : Max timeout [high]
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84 : Max timeout [high]
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Holds 16-bit timeout value (amount of time in clocks before
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Holds 16-bit timeout value (amount of time in clocks before
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timeout error occurs).
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timeout error occurs).
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90 : Interrupt countdown
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90 : Interrupt countdown
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When set, starts a countdown (in clocks) until assertion of
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When set, starts a countdown (in clocks) until assertion of
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the INT_N signal.
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the INT_N signal.
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