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tv80 Core Documentation
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tv80 Core Documentation
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OpenCores.org
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OpenCores.org
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ghutchis@opencores.org
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ghutchis@opencores.org
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General
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General
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private
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private
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XML
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XML
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Extensible Markup Language
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Extensible Markup Language
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A synthesizable 8-bit microprocessor which is instruction-set compatable
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A synthesizable 8-bit microprocessor which is instruction-set compatable
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with the Z80, targetted at embedded and system-on-a-chip designs.
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with the Z80, targetted at embedded and system-on-a-chip designs.
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The tv80 core was created as a Verilog port of the VHDL T80 core, for use as a maintenence processor inside an ASIC.
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The tv80 core was created as a Verilog port of the VHDL T80 core, for use as a maintenence processor inside an ASIC.
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The tv80 has been modified since then for better synthesis
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The tv80 has been modified since then for better synthesis
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timing/area results, and to incorporate several bug-fixes.
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timing/area results, and to incorporate several bug-fixes.
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The T80, and the tv80 derived from it, attempt to maintain the
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The T80, and the tv80 derived from it, attempt to maintain the
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original cycle timings of the Z80, but have radically different
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original cycle timings of the Z80, but have radically different
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internal designs and timings. With its target being ASIC and
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internal designs and timings. With its target being ASIC and
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embedded applications, the tv80 does not attempt to maintain
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embedded applications, the tv80 does not attempt to maintain
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the original pinout of the Z80.
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the original pinout of the Z80.
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This section tracks synthesis results in various technologies. LSI 10K technology is
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This section tracks synthesis results in various technologies. LSI 10K technology is
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used as a baseline because the library ships with Design Compiler.
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used as a baseline because the library ships with Design Compiler.
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Component Clock Speed Area Technology (units)
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Component Clock Speed Area Technology (units)
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================ =========== ======== =====================
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================ =========== ======== =====================
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tv80 33 Mhz 10733 lsi_10k (gates)
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tv80 33 Mhz 10733 lsi_10k (gates)
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simple_gmii 33 Mhz 1247 lsi_10k (gates)
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simple_gmii 33 Mhz 1247 lsi_10k (gates)
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The TV80 design includes a number (one, at this point) of peripherals. These peripherals
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The TV80 design includes a number (one, at this point) of peripherals. These peripherals
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are hardware-synthesizable, but may not be fully tested or functional.
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are hardware-synthesizable, but may not be fully tested or functional.
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This block presents a GMII interface on one side and a TV80 processor interface on
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This block presents a GMII interface on one side and a TV80 processor interface on
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the other. The processor-side controls are all mapped into I/O-space. The block
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the other. The processor-side controls are all mapped into I/O-space. The block
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can only process a single packet in each direction at one time. This is only really
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can only process a single packet in each direction at one time. This is only really
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a limitation on the RX side, where any incoming packets will be dropped until the
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a limitation on the RX side, where any incoming packets will be dropped until the
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processor removes the first packet from the RX buffer.
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processor removes the first packet from the RX buffer.
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The GMII interface is signalling only, and does not support 10/100 operation, half duplex
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The GMII interface is signalling only, and does not support 10/100 operation, half duplex
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mode, flow control, or any other aspects of 802.3.
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mode, flow control, or any other aspects of 802.3.
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This block consumes 3 bits of I/O address space. The register addresses below are
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This block consumes 3 bits of I/O address space. The register addresses below are
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relative to the configurable base address of the block, which must be aligned to an
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relative to the configurable base address of the block, which must be aligned to an
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8-byte boundary. Registers 0x6 and 0x7 are reserved.
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8-byte boundary. Registers 0x6 and 0x7 are reserved.
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Bit 0 of the status register indicates that a packet is available in the RX buffer.
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Bit 0 of the status register indicates that a packet is available in the RX buffer.
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This bit will be cleared when the last byte of data is read out of the RX buffer.
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This bit will be cleared when the last byte of data is read out of the RX buffer.
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Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit
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Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit
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will be cleared when the first byte of data of the next packet is written into the
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will be cleared when the first byte of data of the next packet is written into the
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TX buffer.
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TX buffer.
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This register is read-only.
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This register is read-only.
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Bit 0 controls sending packets. When a 1 is written to this bit, the data in
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Bit 0 controls sending packets. When a 1 is written to this bit, the data in
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the TX buffer will be sent as a single packet.
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the TX buffer will be sent as a single packet.
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This register is write-only.
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This register is write-only.
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This register contains the low 8 bits of the length of the packet currently
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This register contains the low 8 bits of the length of the packet currently
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residing in the RX buffer.
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residing in the RX buffer.
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This register is read-only.
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This register is read-only.
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This register contains the high 8 bits of the length of the packet currently
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This register contains the high 8 bits of the length of the packet currently
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residing in the RX buffer.
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residing in the RX buffer.
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This register is read-only.
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This register is read-only.
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This register contains the next byte of data in the RX packet buffer.
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This register contains the next byte of data in the RX packet buffer.
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This register is read-only.
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This register is read-only.
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Writing to this register puts data in the TX packet buffer. This register does
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Writing to this register puts data in the TX packet buffer. This register does
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not perform bounds checking; it is the program's responsibility not to write more
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not perform bounds checking; it is the program's responsibility not to write more
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data than the size of the TX buffer.
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data than the size of the TX buffer.
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This register is write-only.
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This register is write-only.
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Environment memory space is divided into a 32k ROM region and a 32k RAM
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Environment memory space is divided into a 32k ROM region and a 32k RAM
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region, as follows:
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region, as follows:
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0000-7FFF: ROM
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0000-7FFF: ROM
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8000-FFFF: RAM
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8000-FFFF: RAM
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Environment I/O space is allocated as follows:
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Environment I/O space is allocated as follows:
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00-0F: Unused
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00-0F: Unused
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10-1F: Test devices
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10-1F: Test devices
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20-7F: Unused
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20-7F: Unused
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80-9F: Environment control
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80-9F: Environment control
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A0-FF: Unused
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A0-FF: Unused
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The tv80 environment is controlled by the program under simulation. The
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The tv80 environment is controlled by the program under simulation. The
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program can affect the environment through a set of control registers,
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program can affect the environment through a set of control registers,
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which are mapped into I/O space.
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which are mapped into I/O space.
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Write '01' to end simulation with test passed
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Write '01' to end simulation with test passed
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Write '02' to end with test failed
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Write '02' to end with test failed
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Write '03' to turn on dumping
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Write '03' to turn on dumping
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Write '04' to turn off dumping
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Write '04' to turn off dumping
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Write characters to this port one at a time. When the
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Write characters to this port one at a time. When the
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newline ('\n', ASCII 0x0A) character is written, the
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newline ('\n', ASCII 0x0A) character is written, the
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environment will print out the collected string.
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environment will print out the collected string.
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Bit[0] enables the timeout counter,
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Bit[0] enables the timeout counter,
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Bit[1] resets the counter to 0.
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Bit[1] resets the counter to 0.
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Timeout counter defaults to enabled at simulation start.
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Timeout counter defaults to enabled at simulation start.
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Holds 16-bit timeout value (amount of time in clocks before
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Holds 16-bit timeout value (amount of time in clocks before
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timeout error occurs).
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timeout error occurs).
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When set, starts a countdown (in clocks) until assertion of
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When set, starts a countdown (in clocks) until assertion of
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the INT_N signal.
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the INT_N signal.
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This register holds the checksum value of all data
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This register holds the checksum value of all data
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written to the accumulate register. The checksum is a simple
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written to the accumulate register. The checksum is a simple
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twos-complement checksum, so it can be compared with a CPU-generated
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twos-complement checksum, so it can be compared with a CPU-generated
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checksum.
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checksum.
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This register is readable and writeable. Writing the register sets
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This register is readable and writeable. Writing the register sets
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the current checksum value.
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the current checksum value.
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This write-only register adds the written value to the value
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This write-only register adds the written value to the value
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contained in the Checksum Value register.
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contained in the Checksum Value register.
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This register increments every time it is read, so reading it
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This register increments every time it is read, so reading it
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repeatedly generates an incrementing sequence. It can be reset
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repeatedly generates an incrementing sequence. It can be reset
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by writing it to a new starting value.
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by writing it to a new starting value.
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The minimum toolchain required to simulate the tv80 is the
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The minimum toolchain required to simulate the tv80 is the
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CVer Verilog simulator, and the
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CVer Verilog simulator, and the
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SDCC compiler/assembler/linker. In
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SDCC compiler/assembler/linker. In
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addition, to run the tvs80 instruction
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addition, to run the tvs80 instruction
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test suite, the DOSBox DOS emulator
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test suite, the DOSBox DOS emulator
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is required.
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is required.
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Most of the tests in the tv80 environment are written in C, and should
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Most of the tests in the tv80 environment are written in C, and should
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be compiled with the sdcc compiler.
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be compiled with the sdcc compiler.
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The tvs80 test is different than the rest of the tests, and is
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The tvs80 test is different than the rest of the tests, and is
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written in its own flavor of assembly language. This test provides
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written in its own flavor of assembly language. This test provides
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a fairly comprehensive Z80 instruction test.
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a fairly comprehensive Z80 instruction test.
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The assembler for this test only runs under DOS. To assemble
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The assembler for this test only runs under DOS. To assemble
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under Unix/Linux, the "dosbox" DOS emulator is required. A script
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under Unix/Linux, the "dosbox" DOS emulator is required. A script
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to run the assembler under dosbox, as well as the tvs80.asm source,
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to run the assembler under dosbox, as well as the tvs80.asm source,
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is checked in under the "tests/tvs80" directory.
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is checked in under the "tests/tvs80" directory.
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VHDL T80 Core
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VHDL T80 Core
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OpenCores.org
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OpenCores.org
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Small Device C Compiler
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Small Device C Compiler
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GPL Cver Simulator
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GPL Cver Simulator
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Pragmatic C Software
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Pragmatic C Software
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DOSBox
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DOSBox
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