URL
https://opencores.org/ocsvn/tv80/tv80/trunk
[/] [tv80/] [trunk/] [env/] [async_mem.v] - Diff between revs 2 and 84
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 2 |
Rev 84 |
module async_mem (/*AUTOARG*/
|
module async_mem (/*AUTOARG*/
|
// Outputs
|
// Outputs
|
rd_data,
|
rd_data,
|
// Inputs
|
// Inputs
|
wr_clk, wr_data, wr_cs, addr, rd_cs
|
wr_clk, wr_data, wr_cs, addr, rd_cs
|
);
|
);
|
|
|
parameter asz = 15,
|
parameter asz = 15,
|
depth = 32768;
|
depth = 32768;
|
|
|
input wr_clk;
|
input wr_clk;
|
input [7:0] wr_data;
|
input [7:0] wr_data;
|
input wr_cs;
|
input wr_cs;
|
|
|
input [asz-1:0] addr;
|
input [asz-1:0] addr;
|
inout [7:0] rd_data;
|
inout [7:0] rd_data;
|
input rd_cs;
|
input rd_cs;
|
|
|
reg [7:0] mem [0:depth-1];
|
reg [7:0] mem [0:depth-1];
|
|
|
always @(posedge wr_clk)
|
always @(posedge wr_clk)
|
begin
|
begin
|
if (wr_cs)
|
if (wr_cs)
|
mem[addr] <= #1 wr_data;
|
mem[addr] <= #1 wr_data;
|
end
|
end
|
|
|
assign rd_data = (rd_cs) ? mem[addr] : {8{1'bz}};
|
assign rd_data = (rd_cs) ? mem[addr] : {8{1'bz}};
|
|
|
endmodule // async_mem
|
endmodule // async_mem
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.