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module env_io (/*AUTOARG*/
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module env_io (/*AUTOARG*/
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// Inouts
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// Inouts
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DI,
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DI,
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// Inputs
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// Inputs
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clk, iorq_n, rd_n, wr_n, addr, D_OUT
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clk, iorq_n, rd_n, wr_n, addr, D_OUT
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);
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);
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input clk;
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input clk;
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input iorq_n;
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input iorq_n;
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input rd_n;
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input rd_n;
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input wr_n;
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input wr_n;
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input [7:0] addr;
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input [7:0] addr;
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input [7:0] D_OUT;
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input [7:0] D_OUT;
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inout [7:0] DI;
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inout [7:0] DI;
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reg [7:0] io_data;
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reg [7:0] io_data;
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reg [7:0] str_buf [0:255];
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reg [7:0] str_buf [0:255];
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reg io_cs;
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reg io_cs;
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integer buf_ptr, i;
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integer buf_ptr, i;
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reg [7:0] timeout_ctl;
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reg [7:0] timeout_ctl;
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reg [15:0] cur_timeout;
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reg [15:0] cur_timeout;
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reg [15:0] max_timeout;
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reg [15:0] max_timeout;
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reg [7:0] int_countdown;
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reg [7:0] int_countdown;
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reg [7:0] nmi_countdown;
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reg [7:0] nmi_countdown;
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reg [7:0] checksum;
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reg [7:0] checksum;
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reg [7:0] ior_value; // increment-on-read value
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reg [7:0] ior_value; // increment-on-read value
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reg [7:0] nmi_trigger; // trigger nmi when IR = this value
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reg [7:0] nmi_trigger; // trigger nmi when IR = this value
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assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
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assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
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initial
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initial
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begin
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begin
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io_cs = 0;
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io_cs = 0;
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buf_ptr = 0;
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buf_ptr = 0;
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cur_timeout = 0;
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cur_timeout = 0;
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max_timeout = 10000;
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max_timeout = 10000;
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timeout_ctl = 1;
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timeout_ctl = 1;
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int_countdown = 0;
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int_countdown = 0;
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nmi_countdown = 0;
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nmi_countdown = 0;
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nmi_trigger = 0;
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nmi_trigger = 0;
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end
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end
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always @*
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always @*
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begin
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begin
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if (!iorq_n & !rd_n)
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if (!iorq_n & !rd_n)
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begin
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begin
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io_cs = (addr[7:5] == 3'b100);
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io_cs = (addr[7:5] == 3'b100);
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case (addr)
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case (addr)
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8'h82 : io_data = timeout_ctl;
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8'h82 : io_data = timeout_ctl;
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8'h83 : io_data = max_timeout[7:0];
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8'h83 : io_data = max_timeout[7:0];
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8'h84 : io_data = max_timeout[15:8];
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8'h84 : io_data = max_timeout[15:8];
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8'h90 : io_data = int_countdown;
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8'h90 : io_data = int_countdown;
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8'h91 : io_data = checksum;
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8'h91 : io_data = checksum;
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8'h93 : io_data = ior_value;
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8'h93 : io_data = ior_value;
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8'h94 : io_data = {$random};
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8'h94 : io_data = {$random};
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8'h95 : io_data = nmi_countdown[7:0];
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8'h95 : io_data = nmi_countdown[7:0];
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8'hA0 : io_data = nmi_trigger;
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8'hA0 : io_data = nmi_trigger;
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default : io_data = 8'hzz;
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default : io_data = 8'hzz;
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endcase // case(addr)
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endcase // case(addr)
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end // if (!iorq_n & !rd_n)
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end // if (!iorq_n & !rd_n)
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end // always @ *
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end // always @ *
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wire wr_stb;
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wire wr_stb;
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reg last_iowrite;
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reg last_iowrite;
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assign wr_stb = (!iorq_n & !wr_n);
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assign wr_stb = (!iorq_n & !wr_n);
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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last_iowrite <= #1 wr_stb;
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last_iowrite <= #1 wr_stb;
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if (!wr_stb & last_iowrite)
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if (!wr_stb & last_iowrite)
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case (addr)
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case (addr)
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8'h80 :
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8'h80 :
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begin
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begin
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case (D_OUT)
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case (D_OUT)
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1 :
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1 :
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begin
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begin
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$writememh ("test_output2.hex", tb_top.rom.mem);
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tb_top.test_pass;
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tb_top.test_pass;
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end
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end
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2 :
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2 :
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begin
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begin
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$writememh ("test_output2.hex", tb_top.rom.mem);
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tb_top.test_fail;
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tb_top.test_fail;
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end
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end
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3 : tb_top.dumpon;
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3 : tb_top.dumpon;
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4 : tb_top.dumpoff;
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4 : tb_top.dumpoff;
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default :
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default :
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begin
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begin
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$display ("%t: ERROR : Unknown I/O command %x", $time, D_OUT);
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$display ("%t: ERROR : Unknown I/O command %x", $time, D_OUT);
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end
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end
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endcase // case(D_OUT)
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endcase // case(D_OUT)
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end // case: :...
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end // case: :...
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8'h81 :
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8'h81 :
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begin
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begin
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str_buf[buf_ptr] = D_OUT;
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str_buf[buf_ptr] = D_OUT;
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buf_ptr = buf_ptr + 1;
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buf_ptr = buf_ptr + 1;
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//$display ("%t: DEBUG : Detected write of character %x", $time, D_OUT);
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//$display ("%t: DEBUG : Detected write of character %x", $time, D_OUT);
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if (D_OUT == 8'h0A)
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if (D_OUT == 8'h0A)
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begin
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begin
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$write ("%t: PROGRAM : ", $time);
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$write ("%t: PROGRAM : ", $time);
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for (i=0; i<buf_ptr; i=i+1)
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for (i=0; i<buf_ptr; i=i+1)
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$write ("%s", str_buf[i]);
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$write ("%s", str_buf[i]);
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buf_ptr = 0;
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buf_ptr = 0;
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end
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end
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end // case: 8'h81
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end // case: 8'h81
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8'h82 :
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8'h82 :
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begin
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begin
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timeout_ctl = D_OUT;
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timeout_ctl = D_OUT;
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end
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end
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8'h83 : max_timeout[7:0] = D_OUT;
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8'h83 : max_timeout[7:0] = D_OUT;
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8'h84 : max_timeout[15:8] = D_OUT;
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8'h84 : max_timeout[15:8] = D_OUT;
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8'h90 : int_countdown = D_OUT;
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8'h90 : int_countdown = D_OUT;
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8'h91 : checksum = D_OUT;
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8'h91 : checksum = D_OUT;
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8'h92 : checksum = checksum + D_OUT;
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8'h92 : checksum = checksum + D_OUT;
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8'h93 : ior_value = D_OUT;
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8'h93 : ior_value = D_OUT;
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8'h95 : nmi_countdown[7:0] = D_OUT;
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8'h95 : nmi_countdown[7:0] = D_OUT;
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8'hA0 : nmi_trigger = D_OUT;
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8'hA0 : nmi_trigger = D_OUT;
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endcase // case(addr)
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endcase // case(addr)
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (timeout_ctl[1])
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if (timeout_ctl[1])
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cur_timeout = 0;
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cur_timeout = 0;
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else if (timeout_ctl[0])
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else if (timeout_ctl[0])
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cur_timeout = cur_timeout + 1;
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cur_timeout = cur_timeout + 1;
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if (cur_timeout >= max_timeout)
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if (cur_timeout >= max_timeout)
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begin
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begin
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$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
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$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
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tb_top.test_fail;
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tb_top.test_fail;
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end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (int_countdown == 0)
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if (int_countdown == 0)
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begin
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begin
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tb_top.int_n <= #1 1'b1;
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tb_top.int_n <= #1 1'b1;
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end
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end
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else if (int_countdown == 1)
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else if (int_countdown == 1)
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begin
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begin
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tb_top.int_n <= #1 1'b0;
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tb_top.int_n <= #1 1'b0;
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//int_countdown = 0;
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//int_countdown = 0;
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end
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end
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else if (int_countdown > 1)
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else if (int_countdown > 1)
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begin
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begin
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int_countdown = int_countdown - 1;
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int_countdown = int_countdown - 1;
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tb_top.int_n <= #1 1'b1;
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tb_top.int_n <= #1 1'b1;
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end
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end
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// when nmi countdown reaches 1, an NMI will be issued.
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// when nmi countdown reaches 1, an NMI will be issued.
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// to clear the interrupt, write nmi_countdown to 0.
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// to clear the interrupt, write nmi_countdown to 0.
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if ((nmi_countdown == 0) && (nmi_trigger == 0))
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if ((nmi_countdown == 0) && (nmi_trigger == 0))
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begin
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begin
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tb_top.nmi_n <= #1 1'b1;
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tb_top.nmi_n <= #1 1'b1;
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end
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end
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else if (nmi_countdown == 1)
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else if (nmi_countdown == 1)
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begin
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begin
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tb_top.nmi_n <= #1 1'b0;
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tb_top.nmi_n <= #1 1'b0;
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end
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end
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else if (nmi_countdown > 1)
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else if (nmi_countdown > 1)
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begin
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begin
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nmi_countdown = nmi_countdown - 1;
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nmi_countdown = nmi_countdown - 1;
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tb_top.nmi_n <= #1 1'b1;
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tb_top.nmi_n <= #1 1'b1;
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end
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end
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// when IR equals the target instruction, an NMI will be
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// when IR equals the target instruction, an NMI will be
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// issued. To clear the interrupt, write nmi_trigger to
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// issued. To clear the interrupt, write nmi_trigger to
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// zero.
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// zero.
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if (nmi_trigger != 0)
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if (nmi_trigger != 0)
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begin
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begin
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if (nmi_trigger === tb_top.tv80s_inst.i_tv80_core.IR[7:0])
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if (nmi_trigger === tb_top.tv80s_inst.i_tv80_core.IR[7:0])
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begin
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begin
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tb_top.nmi_n <= #80 0;
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tb_top.nmi_n <= #80 0;
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tb_top.nmi_n <= #160 1;
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tb_top.nmi_n <= #160 1;
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end
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end
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end
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end
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else if (nmi_countdown == 0)
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else if (nmi_countdown == 0)
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tb_top.nmi_n <= #1 1;
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tb_top.nmi_n <= #1 1;
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end
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end
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endmodule // env_io
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endmodule // env_io
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