/* Copyright (c) 2011, Guy Hutchison
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/* Copyright (c) 2011, Guy Hutchison
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// Local Configuration Processor Application
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// Local Configuration Processor Application
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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module lcfg
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module lcfg
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(input clk,
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(input clk,
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input reset_n,
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input reset_n,
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input lcfg_init, // initialize memory to all 0
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input lcfg_proc_reset,
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input lcfg_proc_reset,
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input scan_mode,
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input scan_enable,
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// incoming config interface to
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// incoming config interface to
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// read/write processor memory
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// read/write processor memory
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input cfgi_irdy,
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input cfgi_irdy,
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output cfgi_trdy,
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output cfgi_trdy,
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input [14:0] cfgi_addr,
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input [14:0] cfgi_addr,
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input cfgi_write,
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input cfgi_write,
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input [31:0] cfgi_wr_data,
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input [31:0] cfgi_wr_data,
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output [31:0] cfgi_rd_data,
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output [31:0] cfgi_rd_data,
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// outgoing config interface to system
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// outgoing config interface to system
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// configuration bus
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// configuration bus
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output cfgo_irdy,
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output cfgo_irdy,
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input cfgo_trdy,
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input cfgo_trdy,
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output [15:0] cfgo_addr,
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output [15:0] cfgo_addr,
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output cfgo_write,
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output cfgo_write,
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output [31:0] cfgo_wr_data,
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output [31:0] cfgo_wr_data,
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input [31:0] cfgo_rd_data
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input [31:0] cfgo_rd_data
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);
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);
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wire [15:0] addr;
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wire [15:0] addr;
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wire [7:0] dout;
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wire [7:0] dout;
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reg [7:0] di;
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reg [7:0] di;
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wire mreq_n;
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wire mreq_n;
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wire rd_n, wr_n;
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wire rd_n, wr_n;
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wire iorq_n;
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wire iorq_n;
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reg fw_mode;
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reg fw_mode;
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wire ram_wait_n;
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wire ram_wait_n;
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wire fw_en = (addr[15:13] == {1'b0, !fw_mode, 1'b0}) && !mreq_n;
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wire fw_en = (addr[15:13] == {1'b0, !fw_mode, 1'b0}) && !mreq_n;
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wire fw_we = !wr_n;
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wire fw_we = !wr_n;
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wire [7:0] ram_rd_data;
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wire [7:0] ram_rd_data;
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reg last_wait;
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reg last_wait;
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reg wait_n;
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reg wait_n;
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wire [7:0] reg_addr1, reg_addr0;
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wire [7:0] reg_addr1, reg_addr0;
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wire [7:0] reg_wr_data3;
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wire [7:0] reg_wr_data3;
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wire [7:0] reg_wr_data2;
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wire [7:0] reg_wr_data2;
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wire [7:0] reg_wr_data1;
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wire [7:0] reg_wr_data1;
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wire [7:0] reg_wr_data0;
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wire [7:0] reg_wr_data0;
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wire [7:0] cb_rd_data;
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wire [7:0] cb_rd_data;
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wire [1:0] cb_control;
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wire [1:0] cb_control;
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reg [1:0] cb_control_clr;
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reg [1:0] cb_control_clr;
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wire [7:0] tim_rd_data;
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wire [7:0] tim_rd_data;
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wire [1:0] fw_up_ctrl;
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wire [1:0] fw_up_ctrl;
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wire dma_iorq_n;
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wire dma_iorq_n;
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wire [7:0] dma_rd_data;
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wire [7:0] dma_rd_data;
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reg [31:0] read_hold;
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reg [31:0] read_hold;
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reg read_latch;
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reg read_latch;
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wire dma_int_n; // From dma of mx_lcfg_dma.v
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wire dma_int_n; // From dma of mx_lcfg_dma.v
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wire proc_reset_n;
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wire proc_reset_n;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
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wire [7:0] cd_rdata; // From cfgo_driver of lcfg_cfgo_driver.v
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wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
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wire cfgo_wait_n; // From cfgo_driver of lcfg_cfgo_driver.v
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// End of automatics
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// End of automatics
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wire ram_mreq_n;
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wire ram_mreq_n;
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assign ram_mreq_n = ~ (~mreq_n & ~addr[15]);
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assign ram_mreq_n = ~ (~mreq_n & ~addr[15]);
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assign proc_reset_n = (scan_mode) ? 1'b1 : ~lcfg_proc_reset;
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assign proc_reset_n = ~lcfg_proc_reset;
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tv80s tv80 (
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tv80s tv80 (
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// Outputs
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// Outputs
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.dout (dout),
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.dout (dout),
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.m1_n (),
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.m1_n (),
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.mreq_n (mreq_n),
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.mreq_n (mreq_n),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.rfsh_n (),
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.rfsh_n (),
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.halt_n (),
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.halt_n (),
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.busak_n (),
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.busak_n (),
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.A (addr),
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.A (addr),
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// Inputs
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// Inputs
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.reset_n (proc_reset_n),
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.reset_n (proc_reset_n),
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.clk (clk),
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.clk (clk),
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.wait_n (wait_n),
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.wait_n (wait_n),
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.int_n (dma_int_n),
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.int_n (dma_int_n),
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.nmi_n (1'b1),
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.nmi_n (1'b1),
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.busrq_n (1'b1),
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.busrq_n (1'b1),
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.di (di));
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.di (di));
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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last_wait <= #1 wait_n;
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last_wait <= #1 wait_n;
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end
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end
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always @*
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always @*
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begin
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begin
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wait_n = 1;
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wait_n = 1;
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if (!mreq_n)
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if (!mreq_n)
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begin
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begin
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if (~ram_mreq_n)
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if (~ram_mreq_n)
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begin
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begin
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di = ram_rd_data[7:0];
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di = ram_rd_data[7:0];
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wait_n = ram_wait_n;
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wait_n = ram_wait_n;
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end
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end
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else
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else
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begin
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begin
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di = 8'h0;
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di = 8'h0;
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end
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end
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end
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end
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else if (!iorq_n)
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else if (!iorq_n)
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begin
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begin
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if (addr[7:3] == 0)
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if (addr[7:3] == 0)
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begin
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begin
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di = cd_rdata;
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di = cd_rdata;
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wait_n = cfgo_wait_n;
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wait_n = cfgo_wait_n;
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end
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end
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else
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else
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di = 8'h0;
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di = 8'h0;
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end
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end
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else
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else
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di = 8'h0;
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di = 8'h0;
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end // always @ *
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end // always @ *
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/* lcfg_memctl AUTO_TEMPLATE
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/* lcfg_memctl AUTO_TEMPLATE
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(
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(
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// Outputs
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// Outputs
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.a_mreq_n (ram_mreq_n),
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.a_mreq_n (ram_mreq_n),
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.a_rd_n (rd_n),
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.a_rd_n (rd_n),
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.a_wr_n (wr_n),
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.a_wr_n (wr_n),
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.a_addr (addr[14:0]),
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.a_addr (addr[14:0]),
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.a_wdata (dout),
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.a_wdata (dout),
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.a_wait_n (ram_wait_n),
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.a_wait_n (ram_wait_n),
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.a_rdata (ram_rd_data),
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.a_rdata (ram_rd_data),
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.b_wait_n (),
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.b_wait_n (),
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.b_rdata (),
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.b_rdata (),
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.b_mreq_n (1'b1),
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.b_mreq_n (1'b1),
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.b_wr_n (1'b1),
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.b_wr_n (1'b1),
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.b_addr (13'h0),
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.b_addr (13'h0),
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.b_wdata (32'h0),
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.b_wdata (32'h0),
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);
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);
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*/
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*/
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lcfg_memctl memctl
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lcfg_memctl memctl
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.a_wait_n (ram_wait_n), // Templated
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.a_wait_n (ram_wait_n), // Templated
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.a_rdata (ram_rd_data), // Templated
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.a_rdata (ram_rd_data), // Templated
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.b_wait_n (), // Templated
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.b_wait_n (), // Templated
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.b_rdata (), // Templated
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.b_rdata (), // Templated
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.cfgi_trdy (cfgi_trdy),
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.cfgi_trdy (cfgi_trdy),
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.cfgi_rd_data (cfgi_rd_data[31:0]),
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.cfgi_rd_data (cfgi_rd_data[31:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.a_mreq_n (ram_mreq_n), // Templated
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.a_mreq_n (ram_mreq_n), // Templated
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.a_rd_n (rd_n), // Templated
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.a_rd_n (rd_n), // Templated
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.a_wr_n (wr_n), // Templated
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.a_wr_n (wr_n), // Templated
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.a_addr (addr[14:0]), // Templated
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.a_addr (addr[14:0]), // Templated
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.a_wdata (dout), // Templated
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.a_wdata (dout), // Templated
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.b_mreq_n (1'b1), // Templated
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.b_mreq_n (1'b1), // Templated
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.b_wr_n (1'b1), // Templated
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.b_wr_n (1'b1), // Templated
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.b_addr (13'h0), // Templated
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.b_addr (13'h0), // Templated
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.b_wdata (32'h0), // Templated
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.b_wdata (32'h0), // Templated
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.lcfg_init (lcfg_init),
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.lcfg_init (lcfg_init),
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.cfgi_irdy (cfgi_irdy),
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.cfgi_irdy (cfgi_irdy),
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.cfgi_addr (cfgi_addr[14:0]),
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.cfgi_addr (cfgi_addr[14:0]),
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.cfgi_write (cfgi_write),
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.cfgi_write (cfgi_write),
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.cfgi_wr_data (cfgi_wr_data[31:0]),
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.cfgi_wr_data (cfgi_wr_data[31:0]),
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.test_resume_h (test_resume_h));
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.test_resume_h (test_resume_h));
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// DMA not needed
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// DMA not needed
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// Need GP interrupt register for timer
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// Need GP interrupt register for timer
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assign cfg_addr = { reg_addr1, reg_addr0 };
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assign cfg_addr = { reg_addr1, reg_addr0 };
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assign cfg_wr_data = { reg_wr_data3, reg_wr_data2, reg_wr_data1, reg_wr_data0 };
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assign cfg_wr_data = { reg_wr_data3, reg_wr_data2, reg_wr_data1, reg_wr_data0 };
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/* lcfg_cfgo_driver AUTO_TEMPLATE
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/* lcfg_cfgo_driver AUTO_TEMPLATE
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(
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(
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.cd_wdata (dout[7:0]),
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.cd_wdata (dout[7:0]),
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);
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);
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*/
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*/
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lcfg_cfgo_driver #(.io_base_addr(8'h0)) cfgo_driver
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lcfg_cfgo_driver #(.io_base_addr(8'h0)) cfgo_driver
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.cd_rdata (cd_rdata[7:0]),
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.cd_rdata (cd_rdata[7:0]),
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.cfgo_wait_n (cfgo_wait_n),
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.cfgo_wait_n (cfgo_wait_n),
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.cfgo_irdy (cfgo_irdy),
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.cfgo_irdy (cfgo_irdy),
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.cfgo_addr (cfgo_addr[15:0]),
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.cfgo_addr (cfgo_addr[15:0]),
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.cfgo_write (cfgo_write),
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.cfgo_write (cfgo_write),
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.cfgo_wr_data (cfgo_wr_data[31:0]),
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.cfgo_wr_data (cfgo_wr_data[31:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.addr (addr[15:0]),
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.addr (addr[15:0]),
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.cd_wdata (dout[7:0]), // Templated
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.cd_wdata (dout[7:0]), // Templated
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.mreq_n (mreq_n),
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.mreq_n (mreq_n),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.cfgo_trdy (cfgo_trdy),
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.cfgo_trdy (cfgo_trdy),
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.cfgo_rd_data (cfgo_rd_data[31:0]));
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.cfgo_rd_data (cfgo_rd_data[31:0]));
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endmodule
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endmodule
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