/* Copyright (c) 2011, Guy Hutchison
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/* Copyright (c) 2011, Guy Hutchison
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All rights reserved.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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* Neither the name of the author nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// Memory Controller/Arbiter
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// Memory Controller/Arbiter
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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module lcfg_memctl
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module lcfg_memctl
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(/*AUTOARG*/
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(/*AUTOARG*/
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// Outputs
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// Outputs
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a_wait_n, a_rdata, b_wait_n, b_rdata, cfgi_trdy, cfgi_rd_data,
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a_wait_n, a_rdata, b_wait_n, b_rdata, cfgi_trdy, cfgi_rd_data,
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// Inputs
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// Inputs
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clk, reset_n, a_mreq_n, a_rd_n, a_wr_n, a_addr, a_wdata, b_mreq_n,
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clk, reset_n, a_mreq_n, a_rd_n, a_wr_n, a_addr, a_wdata, b_mreq_n,
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b_wr_n, b_addr, b_wdata, lcfg_init, cfgi_irdy, cfgi_addr,
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b_wr_n, b_addr, b_wdata, lcfg_init, cfgi_irdy, cfgi_addr,
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cfgi_write, cfgi_wr_data
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cfgi_write, cfgi_wr_data
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);
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);
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// address size of memory
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// address size of memory
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parameter mem_asz = 13, mem_depth = 8192;
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parameter mem_asz = 13, mem_depth = 8192;
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input clk;
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input clk;
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input reset_n;
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input reset_n;
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// read port A (uP)
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// read port A (uP)
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input a_mreq_n;
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input a_mreq_n;
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input a_rd_n;
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input a_rd_n;
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input a_wr_n;
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input a_wr_n;
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input [mem_asz+1:0] a_addr;
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input [mem_asz+1:0] a_addr;
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output a_wait_n;
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output a_wait_n;
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input [7:0] a_wdata;
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input [7:0] a_wdata;
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output [7:0] a_rdata;
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output [7:0] a_rdata;
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reg a_wait_n;
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reg a_wait_n;
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// read port B
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// read port B
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input b_mreq_n;
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input b_mreq_n;
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input b_wr_n;
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input b_wr_n;
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input [mem_asz-1:0] b_addr;
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input [mem_asz-1:0] b_addr;
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output b_wait_n;
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output b_wait_n;
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input [31:0] b_wdata;
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input [31:0] b_wdata;
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output [31:0] b_rdata;
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output [31:0] b_rdata;
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reg b_wait_n;
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reg b_wait_n;
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input lcfg_init;
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input lcfg_init;
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// incoming config interface to
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// incoming config interface to
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// read/write processor memory
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// read/write processor memory
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input cfgi_irdy;
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input cfgi_irdy;
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output cfgi_trdy;
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output cfgi_trdy;
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input [mem_asz-1:0] cfgi_addr;
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input [mem_asz-1:0] cfgi_addr;
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input cfgi_write;
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input cfgi_write;
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input [31:0] cfgi_wr_data;
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input [31:0] cfgi_wr_data;
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output [31:0] cfgi_rd_data;
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output [31:0] cfgi_rd_data;
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reg cfgi_trdy, nxt_cfgi_trdy;
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reg cfgi_trdy, nxt_cfgi_trdy;
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reg ram_nwrt;
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reg ram_nwrt;
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reg ram_nce;
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reg ram_nce;
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reg [31:0] ram_din;
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reg [31:0] ram_din;
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reg [mem_asz-1:0] ram_addr;
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reg [mem_asz-1:0] ram_addr;
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wire [31:0] dout;
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wire [31:0] dout;
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reg [7:0] a_rdata;
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reg [7:0] a_rdata;
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reg [mem_asz-1:0] ca_addr, nxt_ca_addr;
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reg [mem_asz-1:0] ca_addr, nxt_ca_addr;
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reg [31:0] ca_data, nxt_ca_data;
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reg [31:0] ca_data, nxt_ca_data;
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reg [mem_asz-1:0] wc_addr, nxt_wc_addr;
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reg [mem_asz-1:0] wc_addr, nxt_wc_addr;
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reg [31:0] wc_data, nxt_wc_data;
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reg [31:0] wc_data, nxt_wc_data;
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reg cvld, nxt_cvld;
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reg cvld, nxt_cvld;
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reg wcvld, nxt_wcvld;
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reg wcvld, nxt_wcvld;
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reg a_prio, nxt_a_prio;
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reg a_prio, nxt_a_prio;
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reg a_rip, nxt_a_rip; // read in progress by A
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reg a_rip, nxt_a_rip; // read in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg a_wip, nxt_a_wip; // write (read-cache-fill) in progress by A
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reg b_rip, nxt_b_rip; // read in progress by B
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reg b_rip, nxt_b_rip; // read in progress by B
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wire c_rip = cfgi_trdy;
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wire c_rip = cfgi_trdy;
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wire c_rip = cfgi_trdy;
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wire a_cache_hit, b_cache_hit;
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wire a_cache_hit, b_cache_hit;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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/* -----\/----- EXCLUDED -----\/-----
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assign #1 t_ram_nwrt = ram_nwrt;
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assign #1 t_ram_nce = ram_nce;
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assign #1 t_ram_addr = ram_addr;
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assign #1 t_ram_din = ram_din;
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-----/\----- EXCLUDED -----/\----- */
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assign cfgi_rd_data = dout;
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assign cfgi_rd_data = dout;
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assign b_rdata = dout;
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assign b_rdata = dout;
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assign a_cache_hit = cvld & (ca_addr == a_addr[mem_asz+1:2]);
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assign a_cache_hit = cvld & (ca_addr == a_addr[mem_asz+1:2]);
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assign b_cache_hit = wcvld & (wc_addr == a_addr[mem_asz+1:2]);
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assign b_cache_hit = wcvld & (wc_addr == a_addr[mem_asz+1:2]);
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/* behave1p_mem AUTO_TEMPLATE
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/* behave1p_mem AUTO_TEMPLATE
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(
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(
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// Outputs
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// Outputs
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.d_out (dout),
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.d_out (dout),
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// Inputs
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// Inputs
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.wr_en (!ram_nce & !ram_nwrt),
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.wr_en (!ram_nce & !ram_nwrt),
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.rd_en (!ram_nce & ram_nwrt),
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.rd_en (!ram_nce & ram_nwrt),
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.clk (clk),
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.clk (clk),
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.d_in (ram_din[]),
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.d_in (ram_din[]),
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.addr (ram_addr[]),
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.addr (ram_addr[]),
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);
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);
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*/
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*/
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behave1p_mem #(.width(32),
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behave1p_mem #(.width(32),
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.depth (mem_depth),
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.depth (mem_depth),
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.addr_sz (mem_asz)) mem
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.addr_sz (mem_asz)) mem
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.d_out (dout), // Templated
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.d_out (dout), // Templated
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// Inputs
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// Inputs
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.wr_en (!ram_nce & !ram_nwrt), // Templated
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.wr_en (!ram_nce & !ram_nwrt), // Templated
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.rd_en (!ram_nce & ram_nwrt), // Templated
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.rd_en (!ram_nce & ram_nwrt), // Templated
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.clk (clk), // Templated
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.clk (clk), // Templated
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.d_in (ram_din[31:0]), // Templated
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.d_in (ram_din[31:0]), // Templated
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.addr (ram_addr[(mem_asz)-1:0])); // Templated
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.addr (ram_addr[(mem_asz)-1:0])); // Templated
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always @*
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always @*
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begin
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begin
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nxt_ca_addr = ca_addr;
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nxt_ca_addr = ca_addr;
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ram_nwrt = 1;
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ram_nwrt = 1;
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ram_nce = 1;
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ram_nce = 1;
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ram_din = 32'h0;
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ram_din = 32'h0;
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ram_addr = a_addr[mem_asz+1:2];
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ram_addr = a_addr[mem_asz+1:2];
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a_wait_n = 1;
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a_wait_n = 1;
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b_wait_n = 1;
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b_wait_n = 1;
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nxt_a_prio = a_prio;
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nxt_a_prio = a_prio;
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nxt_a_rip = 0;
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nxt_a_rip = 0;
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nxt_b_rip = 0;
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nxt_b_rip = 0;
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nxt_a_wip = a_wip;
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nxt_a_wip = a_wip;
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nxt_ca_data = ca_data;
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nxt_ca_data = ca_data;
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nxt_cvld = cvld;
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nxt_cvld = cvld;
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nxt_wcvld = wcvld;
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nxt_wcvld = wcvld;
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nxt_wc_data = wc_data;
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nxt_wc_data = wc_data;
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nxt_wc_addr = wc_addr;
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nxt_wc_addr = wc_addr;
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nxt_cfgi_trdy = 0;
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nxt_cfgi_trdy = 0;
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if (a_cache_hit)
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if (a_cache_hit)
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begin
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begin
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case (a_addr[1:0])
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case (a_addr[1:0])
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0 : a_rdata = ca_data[7:0];
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0 : a_rdata = ca_data[7:0];
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1 : a_rdata = ca_data[15:8];
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1 : a_rdata = ca_data[15:8];
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2 : a_rdata = ca_data[23:16];
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2 : a_rdata = ca_data[23:16];
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3 : a_rdata = ca_data[31:24];
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3 : a_rdata = ca_data[31:24];
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endcase // case(a_addr[1:0])
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endcase // case(a_addr[1:0])
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end
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end
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else if (b_cache_hit)
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else if (b_cache_hit)
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begin
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begin
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case (a_addr[1:0])
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case (a_addr[1:0])
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0 : a_rdata = wc_data[7:0];
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0 : a_rdata = wc_data[7:0];
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1 : a_rdata = wc_data[15:8];
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1 : a_rdata = wc_data[15:8];
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2 : a_rdata = wc_data[23:16];
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2 : a_rdata = wc_data[23:16];
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3 : a_rdata = wc_data[31:24];
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3 : a_rdata = wc_data[31:24];
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endcase // case(a_addr[1:0])
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endcase // case(a_addr[1:0])
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end
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end
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else
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else
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a_rdata = 0;
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a_rdata = 0;
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if (lcfg_init)
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if (lcfg_init)
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begin
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begin
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// repurpose the cache bits as FSM status bits
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// repurpose the cache bits as FSM status bits
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// cvld == done
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// cvld == done
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if (!cvld)
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if (!cvld)
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begin
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begin
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ram_nce = 0;
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ram_nce = 0;
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ram_addr = ca_addr;
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ram_addr = ca_addr;
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ram_nwrt = 0;
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ram_nwrt = 0;
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ram_din = 32'h0;
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ram_din = 32'h0;
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if (ca_addr == 8191)
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if (ca_addr == 8191)
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begin
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begin
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nxt_ca_addr = ca_addr;
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nxt_ca_addr = ca_addr;
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nxt_cvld = 1;
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nxt_cvld = 1;
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nxt_ca_data = 32'h0;
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nxt_ca_data = 32'h0;
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end
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end
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else
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else
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nxt_ca_addr = ca_addr + 1;
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nxt_ca_addr = ca_addr + 1;
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end
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end
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end
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end
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else
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else
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begin
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begin
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if (!a_mreq_n)
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if (!a_mreq_n)
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begin
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begin
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if (!a_rd_n)
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if (!a_rd_n)
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begin
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begin
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// check for cache hit
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// check for cache hit
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if (!a_cache_hit & !b_cache_hit)
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if (!a_cache_hit & !b_cache_hit)
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begin
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begin
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a_wait_n = 0;
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a_wait_n = 0;
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if (a_rip)
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if (a_rip)
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begin
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begin
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nxt_ca_addr = a_addr[mem_asz+1:2];
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nxt_ca_addr = a_addr[mem_asz+1:2];
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nxt_ca_data = dout;
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nxt_ca_data = dout;
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nxt_cvld = 1;
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nxt_cvld = 1;
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end
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end
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else if (a_prio | b_mreq_n)
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else if (a_prio | b_mreq_n)
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begin
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begin
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ram_addr = a_addr[mem_asz+1:2];
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ram_addr = a_addr[mem_asz+1:2];
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nxt_a_prio = 0;
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nxt_a_prio = 0;
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ram_nce = 0;
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ram_nce = 0;
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nxt_a_rip = 1;
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nxt_a_rip = 1;
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end
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end
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end // if (ca_addr != a_addr[14:2])
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end // if (ca_addr != a_addr[14:2])
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end // if (!rd_n)
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end // if (!rd_n)
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else if (!a_wr_n)
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else if (!a_wr_n)
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begin
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begin
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if (a_prio | b_mreq_n)
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if (a_prio | b_mreq_n)
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begin
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begin
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// if data is in our read cache, transfer it to the
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// if data is in our read cache, transfer it to the
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// write cache, invalidate the read cache, update the
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// write cache, invalidate the read cache, update the
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// appropriate data byte, and start the B cache
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// appropriate data byte, and start the B cache
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// write-back
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// write-back
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if (a_cache_hit)
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if (a_cache_hit)
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begin
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begin
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nxt_cvld = 0;
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nxt_cvld = 0;
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case (a_addr[1:0])
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case (a_addr[1:0])
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0 : nxt_wc_data = { ca_data[31:8], a_wdata };
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0 : nxt_wc_data = { ca_data[31:8], a_wdata };
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1 : nxt_wc_data = { ca_data[31:16], a_wdata, ca_data[7:0] };
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1 : nxt_wc_data = { ca_data[31:16], a_wdata, ca_data[7:0] };
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2 : nxt_wc_data = { ca_data[31:24], a_wdata, ca_data[15:0] };
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2 : nxt_wc_data = { ca_data[31:24], a_wdata, ca_data[15:0] };
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3 : nxt_wc_data = { a_wdata, ca_data[23:0] };
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3 : nxt_wc_data = { a_wdata, ca_data[23:0] };
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endcase // case(a_addr[1:0])
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endcase // case(a_addr[1:0])
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nxt_wc_addr = ca_addr;
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nxt_wc_addr = ca_addr;
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nxt_a_wip = 1;
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nxt_a_wip = 1;
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nxt_a_prio = 1;
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nxt_a_prio = 1;
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end
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end
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// if read is in progress, we have the results of our
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// if read is in progress, we have the results of our
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// cache fill. Store this in the write cache so next
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// cache fill. Store this in the write cache so next
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// cycle we will get a cache hit.
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// cycle we will get a cache hit.
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else if (a_rip)
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else if (a_rip)
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begin
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begin
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a_wait_n = 0;
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a_wait_n = 0;
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nxt_wc_data = dout;
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nxt_wc_data = dout;
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nxt_wc_addr = a_addr[mem_asz+1:2];
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nxt_wc_addr = a_addr[mem_asz+1:2];
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nxt_wcvld = 1;
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nxt_wcvld = 1;
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end
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end
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// if we get a write cache hit, we have the data we
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// if we get a write cache hit, we have the data we
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// need. Change the data in the write cache and trigger
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// need. Change the data in the write cache and trigger
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// a write-back next cycle.
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// a write-back next cycle.
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else if (b_cache_hit)
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else if (b_cache_hit)
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begin
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begin
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case (a_addr[1:0])
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case (a_addr[1:0])
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0 : nxt_wc_data[7:0] = a_wdata;
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0 : nxt_wc_data[7:0] = a_wdata;
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1 : nxt_wc_data[15:8] = a_wdata;
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1 : nxt_wc_data[15:8] = a_wdata;
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2 : nxt_wc_data[23:16] = a_wdata;
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2 : nxt_wc_data[23:16] = a_wdata;
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3 : nxt_wc_data[31:24] = a_wdata;
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3 : nxt_wc_data[31:24] = a_wdata;
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endcase // case(a_addr[1:0])
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endcase // case(a_addr[1:0])
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nxt_a_wip = 1;
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nxt_a_wip = 1;
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nxt_a_prio = 1;
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nxt_a_prio = 1;
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end
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end
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// otherwise we do not have the data in our write cache
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// otherwise we do not have the data in our write cache
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// yet. Trigger a read to fill the write cache.
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// yet. Trigger a read to fill the write cache.
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else if (a_prio | b_mreq_n)
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else if (a_prio | b_mreq_n)
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begin
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begin
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a_wait_n = 0;
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a_wait_n = 0;
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ram_addr = a_addr[mem_asz+1:2];
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ram_addr = a_addr[mem_asz+1:2];
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nxt_a_prio = 0;
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nxt_a_prio = 0;
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ram_nce = 0;
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ram_nce = 0;
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nxt_a_rip = 1;
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nxt_a_rip = 1;
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end
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end
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end
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end
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else
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else
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a_wait_n = 0;
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a_wait_n = 0;
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end
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end
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end // if (!a_mreq_n)
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end // if (!a_mreq_n)
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else
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else
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begin
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begin
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if (a_wip & (a_prio|b_mreq_n))
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if (a_wip & (a_prio|b_mreq_n))
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begin
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begin
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ram_addr = wc_addr;
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ram_addr = wc_addr;
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nxt_a_prio = 0;
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nxt_a_prio = 0;
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ram_nce = 0;
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ram_nce = 0;
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ram_nwrt = 0;
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ram_nwrt = 0;
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nxt_a_wip = 0;
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nxt_a_wip = 0;
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ram_din = wc_data;
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ram_din = wc_data;
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end
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end
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end
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end
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if (!b_mreq_n)
|
if (!b_mreq_n)
|
begin
|
begin
|
if (!b_wr_n)
|
if (!b_wr_n)
|
begin
|
begin
|
if (!a_prio | a_mreq_n)
|
if (!a_prio | a_mreq_n)
|
begin
|
begin
|
ram_addr = b_addr;
|
ram_addr = b_addr;
|
nxt_a_prio = 1;
|
nxt_a_prio = 1;
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_nwrt = 0;
|
ram_nwrt = 0;
|
ram_din = b_wdata;
|
ram_din = b_wdata;
|
if (b_addr == ca_addr)
|
if (b_addr == ca_addr)
|
nxt_cvld = 0;
|
nxt_cvld = 0;
|
if (wc_addr == ca_addr)
|
if (wc_addr == ca_addr)
|
nxt_wcvld = 0;
|
nxt_wcvld = 0;
|
end
|
end
|
else
|
else
|
b_wait_n = 0;
|
b_wait_n = 0;
|
end // if (!b_wr_n)
|
end // if (!b_wr_n)
|
else
|
else
|
begin
|
begin
|
if (b_rip)
|
if (b_rip)
|
begin
|
begin
|
b_wait_n = 1;
|
b_wait_n = 1;
|
end
|
end
|
else if (!a_prio | a_mreq_n)
|
else if (!a_prio | a_mreq_n)
|
begin
|
begin
|
ram_addr = b_addr;
|
ram_addr = b_addr;
|
nxt_b_rip = 1;
|
nxt_b_rip = 1;
|
nxt_a_prio = 1;
|
nxt_a_prio = 1;
|
ram_nce = 0;
|
ram_nce = 0;
|
b_wait_n = 0;
|
b_wait_n = 0;
|
end
|
end
|
end
|
end
|
end // if (!b_mreq_n)
|
end // if (!b_mreq_n)
|
|
|
if (cfgi_irdy)
|
if (cfgi_irdy)
|
begin
|
begin
|
if ((!a_mreq_n | !b_mreq_n) & !c_rip)
|
if ((a_mreq_n & b_mreq_n) & !c_rip & !a_wip)
|
begin
|
|
// access by A or B ports, stall until memory is free
|
|
end
|
|
else
|
|
begin
|
begin
|
if (cfgi_write & !cfgi_trdy)
|
if (cfgi_write & !cfgi_trdy)
|
begin
|
begin
|
nxt_cfgi_trdy = 1;
|
nxt_cfgi_trdy = 1;
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_nwrt = 0;
|
ram_nwrt = 0;
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
ram_din = cfgi_wr_data;
|
ram_din = cfgi_wr_data;
|
// invalidate caches as precaution
|
// invalidate caches as precaution
|
nxt_cvld = 0;
|
nxt_cvld = 0;
|
nxt_wcvld = 0;
|
nxt_wcvld = 0;
|
end
|
end
|
else if (!cfgi_write & !cfgi_trdy)
|
else if (!cfgi_write & !cfgi_trdy)
|
begin
|
begin
|
ram_nce = 0;
|
ram_nce = 0;
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
ram_addr = cfgi_addr[mem_asz-1:0];
|
nxt_cfgi_trdy = 1;
|
nxt_cfgi_trdy = 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
end // if (lcfg_init)
|
end // if (lcfg_init)
|
end // always @ *
|
end // always @ *
|
|
|
always @(posedge clk or negedge reset_n)
|
always @(posedge clk or negedge reset_n)
|
begin
|
begin
|
if (~reset_n)
|
if (~reset_n)
|
begin
|
begin
|
ca_addr <= 13'h0;
|
ca_addr <= 13'h0;
|
cvld <= #1 0;
|
cvld <= 0;
|
/*AUTORESET*/
|
/*AUTORESET*/
|
// Beginning of autoreset for uninitialized flops
|
// Beginning of autoreset for uninitialized flops
|
a_prio <= 1'h0;
|
a_prio <= 1'h0;
|
a_rip <= 1'h0;
|
a_rip <= 1'h0;
|
a_wip <= 1'h0;
|
a_wip <= 1'h0;
|
b_rip <= 1'h0;
|
b_rip <= 1'h0;
|
ca_data <= 32'h0;
|
ca_data <= 32'h0;
|
cfgi_trdy <= 1'h0;
|
cfgi_trdy <= 1'h0;
|
wc_addr <= {mem_asz{1'b0}};
|
wc_addr <= {mem_asz{1'b0}};
|
wc_data <= 32'h0;
|
wc_data <= 32'h0;
|
wcvld <= 1'h0;
|
wcvld <= 1'h0;
|
// End of automatics
|
// End of automatics
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cvld <= #1 nxt_cvld;
|
cvld <= nxt_cvld;
|
ca_addr <= #1 nxt_ca_addr;
|
ca_addr <= nxt_ca_addr;
|
ca_data <= #1 nxt_ca_data;
|
ca_data <= nxt_ca_data;
|
wcvld <= #1 nxt_wcvld;
|
wcvld <= nxt_wcvld;
|
wc_addr <= #1 nxt_wc_addr;
|
wc_addr <= nxt_wc_addr;
|
wc_data <= #1 nxt_wc_data;
|
wc_data <= nxt_wc_data;
|
a_prio <= #1 nxt_a_prio;
|
a_prio <= nxt_a_prio;
|
a_rip <= #1 nxt_a_rip;
|
a_rip <= nxt_a_rip;
|
b_rip <= #1 nxt_b_rip;
|
b_rip <= nxt_b_rip;
|
a_wip <= #1 nxt_a_wip;
|
a_wip <= nxt_a_wip;
|
cfgi_trdy <= #1 nxt_cfgi_trdy;
|
cfgi_trdy <= nxt_cfgi_trdy;
|
end
|
end
|
end
|
end
|
|
|
endmodule // memcontrol
|
endmodule // memcontrol
|
|
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-files:(".")
|
// verilog-library-files:(".")
|
// End:
|
// End:
|
|
|
|
|
