//
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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// Software is furnished to do so, subject to the following conditions:
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//
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//
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// The above copyright notice and this permission notice shall be included
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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// in all copies or substantial portions of the Software.
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//
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// RAM with 1 synchronous write port and one async read port
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// RAM with 1 synchronous write port and one async read port
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module ram_1r_1w (/*AUTOARG*/
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module ram_1r_1w (/*AUTOARG*/
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// Outputs
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// Outputs
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rd_data,
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rd_data,
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// Inputs
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// Inputs
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clk, wr_addr, wr_en, wr_data, rd_addr
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clk, wr_addr, wr_en, wr_data, rd_addr
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);
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);
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parameter width = 8;
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parameter width = 8;
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parameter depth = 128;
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parameter depth = 128;
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parameter addr_sz = 7;
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parameter addr_sz = 7;
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input clk;
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input clk;
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input [addr_sz-1:0] wr_addr;
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input [addr_sz-1:0] wr_addr;
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input wr_en;
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input wr_en;
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input [width-1:0] wr_data;
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input [width-1:0] wr_data;
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input [addr_sz-1:0] rd_addr;
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input [addr_sz-1:0] rd_addr;
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output [width-1:0] rd_data;
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output [width-1:0] rd_data;
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reg [width-1:0] mem [0:depth-1];
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reg [width-1:0] mem [0:depth-1];
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (wr_en)
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if (wr_en)
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mem[wr_addr] <= #1 wr_data;
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mem[wr_addr] <= #1 wr_data;
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end
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end
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assign rd_data = mem[rd_addr];
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assign rd_data = mem[rd_addr];
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endmodule // ram_1r_1w
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endmodule // ram_1r_1w
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