//
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//
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// Simple GMII-Like Interface for TV80
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// Simple GMII-Like Interface for TV80
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//
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//
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// Copyright (c) 2005 Guy Hutchison (ghutchis@opencores.org)
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// Copyright (c) 2005 Guy Hutchison (ghutchis@opencores.org)
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//
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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// Software is furnished to do so, subject to the following conditions:
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//
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//
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// The above copyright notice and this permission notice shall be included
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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// in all copies or substantial portions of the Software.
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//
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module simple_gmii_top (/*AUTOARG*/
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module simple_gmii_top (/*AUTOARG*/
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// Outputs
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// Outputs
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rd_data, doe, int_n, tx_data, tx_dv, tx_er,
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rd_data, doe, int_n, tx_data, tx_dv, tx_er,
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// Inputs
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// Inputs
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clk, reset, iorq_n, rd_n, addr, wr_data, wr_n, rx_clk, rx_data,
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clk, reset, iorq_n, rd_n, addr, wr_data, wr_n, rx_clk, rx_data,
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rx_dv, rx_er, tx_clk
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rx_dv, rx_er, tx_clk
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);
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);
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parameter txbuf_sz = 512, rxbuf_sz = 512;
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parameter txbuf_sz = 512, rxbuf_sz = 512;
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parameter wr_ptr_sz = 10;
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parameter wr_ptr_sz = 9;
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input clk; // To core0 of simple_gmii_core.v, ...
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input clk; // To core0 of simple_gmii_core.v, ...
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input reset; // To core0 of simple_gmii_core.v, ...
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input reset; // To core0 of simple_gmii_core.v, ...
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// TV80 Controls
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// TV80 Controls
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input iorq_n; // To regs0 of simple_gmii_regs.v
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input iorq_n; // To regs0 of simple_gmii_regs.v
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input rd_n; // To regs0 of simple_gmii_regs.v
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input rd_n; // To regs0 of simple_gmii_regs.v
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input [15:0] addr; // To regs0 of simple_gmii_regs.v
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input [15:0] addr; // To regs0 of simple_gmii_regs.v
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input [7:0] wr_data; // To regs0 of simple_gmii_regs.v
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input [7:0] wr_data; // To regs0 of simple_gmii_regs.v
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output [7:0] rd_data; // From regs0 of simple_gmii_regs.v
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output [7:0] rd_data; // From regs0 of simple_gmii_regs.v
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input wr_n; // To regs0 of simple_gmii_regs.v
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input wr_n; // To regs0 of simple_gmii_regs.v
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output doe; // From regs0 of simple_gmii_regs.v
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output doe; // From regs0 of simple_gmii_regs.v
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output int_n; // From regs0 of simple_gmii_regs.v
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output int_n; // From regs0 of simple_gmii_regs.v
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// GMII RX
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// GMII RX
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input rx_clk; // To core0 of simple_gmii_core.v
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input rx_clk; // To core0 of simple_gmii_core.v
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input [7:0] rx_data; // To core0 of simple_gmii_core.v, ...
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input [7:0] rx_data; // To core0 of simple_gmii_core.v, ...
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input rx_dv; // To core0 of simple_gmii_core.v
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input rx_dv; // To core0 of simple_gmii_core.v
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input rx_er; // To core0 of simple_gmii_core.v
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input rx_er; // To core0 of simple_gmii_core.v
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// GMII TX
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// GMII TX
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input tx_clk; // To core0 of simple_gmii_core.v
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input tx_clk; // To core0 of simple_gmii_core.v
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output [7:0] tx_data;
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output [7:0] tx_data;
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output tx_dv;
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output tx_dv;
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output tx_er;
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output tx_er;
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wire [1:0] status_set;
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wire [1:0] status_set;
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wire [15:0] rx_len;
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wire [15:0] rx_len;
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wire [7:0] rx_rd_data;
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wire [7:0] rx_rd_data;
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wire [7:0] tx_wr_data;
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wire [7:0] tx_wr_data;
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wire tx_wr_stb;
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wire tx_wr_stb;
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wire en_preamble;
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wire en_preamble;
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wire start_transmit;
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wire start_transmit;
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wire rx_rd_stb;
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wire rx_rd_stb;
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// RX Buf RAM
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// RX Buf RAM
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wire rxbuf_we;
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wire rxbuf_we;
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wire [wr_ptr_sz-1:0] rx_wr_ptr;
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wire [wr_ptr_sz-1:0] rx_wr_ptr;
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wire [wr_ptr_sz-1:0] rx_rd_ptr;
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wire [wr_ptr_sz-1:0] rx_rd_ptr;
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wire [7:0] rxbuf_data;
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wire [7:0] rxbuf_data;
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// TX Buf RAM
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// TX Buf RAM
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wire wr_sel_tx_data;
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wire wr_sel_tx_data;
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wire [wr_ptr_sz-1:0] txi_wr_ptr;
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wire [wr_ptr_sz-1:0] txi_wr_ptr;
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wire [7:0] io_data_in;
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wire [7:0] io_data_in;
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wire [wr_ptr_sz-1:0] txo_xm_ptr;
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wire [wr_ptr_sz-1:0] txo_xm_ptr;
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wire [7:0] txbuf_data;
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wire [7:0] txbuf_data;
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simple_gmii_core #(txbuf_sz, rxbuf_sz, wr_ptr_sz) core0
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simple_gmii_core #(txbuf_sz, rxbuf_sz, wr_ptr_sz) core0
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(
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(
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// Outputs
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// Outputs
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.status_set (status_set),
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.status_set (status_set),
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.rx_len (rx_len),
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.rx_len (rx_len),
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.rx_rd_data (rx_rd_data),
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.rx_rd_data (rx_rd_data),
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// GMII TX Interface
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// GMII TX Interface
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.tx_clk (tx_clk),
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.tx_clk (tx_clk),
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.tx_data (tx_data),
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.tx_data (tx_data),
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.tx_dv (tx_dv),
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.tx_dv (tx_dv),
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.tx_er (tx_er),
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.tx_er (tx_er),
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// GMII RX Interface
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// GMII RX Interface
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.rx_data (rx_data),
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.rx_data (rx_data),
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.rx_clk (rx_clk),
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.rx_clk (rx_clk),
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.rx_dv (rx_dv),
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.rx_dv (rx_dv),
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.rx_er (rx_er),
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.rx_er (rx_er),
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// RX Buf RAM
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// RX Buf RAM
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.rxbuf_we (rxbuf_we),
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.rxbuf_we (rxbuf_we),
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.rx_wr_ptr (rx_wr_ptr),
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.rx_wr_ptr (rx_wr_ptr),
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.rx_rd_ptr (rx_rd_ptr),
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.rx_rd_ptr (rx_rd_ptr),
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.rxbuf_data (rxbuf_data),
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.rxbuf_data (rxbuf_data),
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// TX Buf RAM
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// TX Buf RAM
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.wr_sel_tx_data (wr_sel_tx_data),
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.wr_sel_tx_data (wr_sel_tx_data),
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.txi_wr_ptr (txi_wr_ptr),
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.txi_wr_ptr (txi_wr_ptr),
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//.io_data_in (io_data_in),
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//.io_data_in (io_data_in),
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.txo_xm_ptr (txo_xm_ptr),
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.txo_xm_ptr (txo_xm_ptr),
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.txbuf_data (txbuf_data),
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.txbuf_data (txbuf_data),
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// Register Interface
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// Register Interface
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.start_transmit (start_transmit),
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.start_transmit (start_transmit),
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.rx_rd_stb (rx_rd_stb),
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.rx_rd_stb (rx_rd_stb),
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//.tx_wr_data (tx_wr_data),
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//.tx_wr_data (tx_wr_data),
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.tx_wr_stb (tx_wr_stb),
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.tx_wr_stb (tx_wr_stb),
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.en_preamble (en_preamble));
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.en_preamble (en_preamble));
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ram_1r_1w #(8, rxbuf_sz, wr_ptr_sz) rxbuf
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ram_1r_1w #(8, rxbuf_sz, wr_ptr_sz) rxbuf
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(.clk (rx_clk),
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(.clk (rx_clk),
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.wr_en (rxbuf_we),
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.wr_en (rxbuf_we),
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.wr_addr (rx_wr_ptr),
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.wr_addr (rx_wr_ptr),
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.wr_data (rx_data),
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.wr_data (rx_data),
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.rd_addr (rx_rd_ptr),
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.rd_addr (rx_rd_ptr),
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.rd_data (rxbuf_data));
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.rd_data (rxbuf_data));
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ram_1r_1w #(8, txbuf_sz, wr_ptr_sz) txbuf
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ram_1r_1w #(8, txbuf_sz, wr_ptr_sz) txbuf
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(.clk (clk),
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(.clk (clk),
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.wr_en (wr_sel_tx_data),
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.wr_en (wr_sel_tx_data),
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.wr_addr (txi_wr_ptr),
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.wr_addr (txi_wr_ptr),
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.wr_data (tx_wr_data),
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.wr_data (tx_wr_data),
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.rd_addr (txo_xm_ptr),
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.rd_addr (txo_xm_ptr),
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.rd_data (txbuf_data));
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.rd_data (txbuf_data));
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simple_gmii_regs regs0
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simple_gmii_regs regs0
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(
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(
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// Outputs
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// Outputs
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.rd_data (rd_data),
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.rd_data (rd_data),
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.doe (doe),
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.doe (doe),
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.status_msk (),
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.status_msk (),
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.control (start_transmit),
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.control (start_transmit),
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.rx_data_stb (rx_rd_stb),
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.rx_data_stb (rx_rd_stb),
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.tx_data (tx_wr_data),
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.tx_data (tx_wr_data),
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.tx_data_stb (tx_wr_stb),
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.tx_data_stb (tx_wr_stb),
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.config (en_preamble),
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.cfg (en_preamble),
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.int_n (int_n),
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.int_n (int_n),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.addr (addr[15:0]),
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.addr (addr[15:0]),
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.wr_data (wr_data),
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.wr_data (wr_data),
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.rd_n (rd_n),
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.rd_n (rd_n),
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.wr_n (wr_n),
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.wr_n (wr_n),
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.iorq_n (iorq_n),
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.iorq_n (iorq_n),
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.status_set (status_set[1:0]),
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.status_set (status_set[1:0]),
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.control_clr (start_transmit), // auto-clear when set
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.control_clr (start_transmit), // auto-clear when set
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.rx_len0 (rx_len[7:0]),
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.rx_len0 (rx_len[7:0]),
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.rx_len1 (rx_len[15:8]),
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.rx_len1 (rx_len[15:8]),
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.rx_data (rx_rd_data));
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.rx_data (rx_rd_data));
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endmodule // simple_gmii
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endmodule // simple_gmii
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