/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// TV80 to Wishbone Master Interface Wrapper ////
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//// TV80 to Wishbone Master Interface Wrapper ////
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//// ////
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//// ////
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//// $Id: wb_tv80.v,v 1.2 2008-12-17 07:46:29 hharte Exp $ ////
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//// $Id: wb_tv80.v,v 1.2 2008-12-17 07:46:29 hharte Exp $ ////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// hharte@opencores.org ////
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//// hharte@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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`define TAG_MEM 2'b00
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`define TAG_MEM 2'b00
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`define TAG_IO 2'b01
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`define TAG_IO 2'b01
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module wb_tv80 (nrst_i, clk_i,
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module wb_tv80 (nrst_i, clk_i,
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wbm_adr_o, wbm_tga_o, wbm_dat_i, wbm_dat_o, wbm_cyc_o,
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wbm_adr_o, wbm_tga_o, wbm_dat_i, wbm_dat_o, wbm_cyc_o,
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wbm_stb_o, wbm_we_o, wbm_ack_i,
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wbm_stb_o, wbm_we_o, wbm_ack_i,
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nmi_req_i,
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nmi_req_i,
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int_req_i,
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int_req_i,
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busrq_i,
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busrq_i,
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busak_o);
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busak_o);
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input nrst_i;
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input nrst_i;
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input clk_i;
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input clk_i;
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// WISHBONE master interface
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// WISHBONE master interface
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output [15:0] wbm_adr_o;
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output [15:0] wbm_adr_o;
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output [1:0] wbm_tga_o;
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output [1:0] wbm_tga_o;
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input [7:0] wbm_dat_i;
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input [7:0] wbm_dat_i;
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output [7:0] wbm_dat_o;
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output [7:0] wbm_dat_o;
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output wbm_cyc_o;
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output wbm_cyc_o;
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output wbm_stb_o;
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output wbm_stb_o;
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output wbm_we_o;
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output wbm_we_o;
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input wbm_ack_i;
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input wbm_ack_i;
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// Z80-specific interface
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// Z80-specific interface
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input nmi_req_i;
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input nmi_req_i;
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input int_req_i;
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input int_req_i;
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input busrq_i;
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input busrq_i;
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output busak_o;
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output busak_o;
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// TV80 Interface
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// TV80 Interface
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wire m1_n;
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wire m1_n;
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wire mreq_n;
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wire mreq_n;
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wire iorq_n;
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wire iorq_n;
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wire rd_n;
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wire rd_n;
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wire wr_n;
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wire wr_n;
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wire rfsh_n;
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wire rfsh_n;
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wire halt_n;
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wire halt_n;
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wire busak_n;
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wire busak_n;
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wire [15:0] tv80_adr;
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wire [15:0] tv80_adr;
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wire [7:0] tv80_dat_o;
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wire [7:0] tv80_dat_o;
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wire wait_n;
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wire wait_n;
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wire int_n;
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wire int_n;
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wire nmi_n;
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wire nmi_n;
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wire busrq_n;
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wire busrq_n;
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wire [7:0] tv80_dat_i;
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wire [7:0] tv80_dat_i;
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assign wbm_adr_o = tv80_adr;
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assign wbm_adr_o = tv80_adr;
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assign wbm_dat_o = tv80_dat_o;
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assign wbm_dat_o = tv80_dat_o;
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assign wbm_we_o = ~wr_n & (~mreq_n | ~iorq_n);
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assign wbm_we_o = ~wr_n & (~mreq_n | ~iorq_n);
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assign wbm_stb_o = (~wr_n | ~rd_n) & (~mreq_n | ~iorq_n | ~m1_n);
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assign wbm_stb_o = (~wr_n | ~rd_n) & (~mreq_n | ~iorq_n | ~m1_n);
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assign wbm_cyc_o = wbm_stb_o;
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assign wbm_cyc_o = wbm_stb_o;
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assign wbm_tga_o = (~iorq_n ? `TAG_IO : `TAG_MEM);
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assign wbm_tga_o = (~iorq_n ? `TAG_IO : `TAG_MEM);
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assign wait_n = wbm_stb_o == 1'b0 ? 1'b1 : wbm_ack_i;
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assign wait_n = wbm_stb_o == 1'b0 ? 1'b1 : wbm_ack_i;
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assign tv80_dat_i = wbm_dat_i;
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assign tv80_dat_i = wbm_dat_i;
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assign int_n = ~int_req_i;
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assign int_n = ~int_req_i;
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assign nmi_n = ~nmi_req_i;
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assign nmi_n = ~nmi_req_i;
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assign busrq_n = ~busrq_i;
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assign busrq_n = ~busrq_i;
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assign busak_o = ~busak_n;
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assign busak_o = ~busak_n;
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// Instantiate TV80 CPU Core
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// Instantiate TV80 CPU Core
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tv80s z80_core (
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tv80s z80_core (
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.m1_n(m1_n),
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.m1_n(m1_n),
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.mreq_n(mreq_n),
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.mreq_n(mreq_n),
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.iorq_n(iorq_n),
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.iorq_n(iorq_n),
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.rd_n(rd_n),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.wr_n(wr_n),
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.rfsh_n(rfsh_n),
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.rfsh_n(rfsh_n),
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.halt_n(halt_n),
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.halt_n(halt_n),
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.busak_n(busak_n),
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.busak_n(busak_n),
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.A(tv80_adr),
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.A(tv80_adr),
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.do(tv80_dat_o),
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.do(tv80_dat_o),
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.reset_n(nrst_i),
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.reset_n(nrst_i),
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.clk(clk_i),
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.clk(clk_i),
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.wait_n(wait_n),
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.wait_n(wait_n),
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.int_n(int_n),
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.int_n(int_n),
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.nmi_n(nmi_n),
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.nmi_n(nmi_n),
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.busrq_n(busrq_n),
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.busrq_n(busrq_n),
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.di(tv80_dat_i)
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.di(tv80_dat_i)
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);
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);
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endmodule
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endmodule
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