#!/usr/bin/env python
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#!/usr/bin/env python
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# Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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# Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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#
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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# Software is furnished to do so, subject to the following conditions:
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#
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#
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# The above copyright notice and this permission notice shall be included
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# The above copyright notice and this permission notice shall be included
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# in all copies or substantial portions of the Software.
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# in all copies or substantial portions of the Software.
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#
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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import string, math, re
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import string, math, re
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def log2 (num):
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def log2 (num):
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return math.ceil (math.log (num) / math.log (2))
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return math.ceil (math.log (num) / math.log (2))
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# function that tries to interpret a number in Verilog notation
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# function that tries to interpret a number in Verilog notation
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def number (str):
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def number (str):
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try:
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try:
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robj = re.compile ("(\d+)'([dhb])([\da-fA-F]+)")
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robj = re.compile ("(\d+)'([dhb])([\da-fA-F]+)")
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mobj = robj.match (str)
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mobj = robj.match (str)
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if (mobj):
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if (mobj):
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if mobj.group(2) == 'h': radix = 16
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if mobj.group(2) == 'h': radix = 16
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elif mobj.group(2) == 'b': radix = 2
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elif mobj.group(2) == 'b': radix = 2
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else: radix = 10
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else: radix = 10
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return int (mobj.group(3), radix)
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return int (mobj.group(3), radix)
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else:
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else:
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return int(str)
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return int(str)
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except ValueError:
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except ValueError:
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print "ERROR: number conversion of %s failed" % str
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print "ERROR: number conversion of %s failed" % str
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return 0
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return 0
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def int2bin (n):
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bStr = ''
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if (n < 0): raise ValueError, "must be positive integer"
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if (n == 0): return '0'
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while (n > 0):
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bStr = str (n%2) + bStr
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n = n >> 1
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return bStr
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def comb_block (statements):
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def comb_block (statements):
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result = 'always @*\n'
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result = 'always @*\n'
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result += ' begin\n'
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result += ' begin\n'
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for s in statements:
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for s in statements:
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result += ' ' + s + '\n'
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result += ' ' + s + '\n'
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result += ' end\n'
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result += ' end\n'
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return result
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return result
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def seq_block (clock, statements):
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def seq_block (clock, statements):
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result = 'always @(posedge ' + clock + ')\n'
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result = 'always @(posedge ' + clock + ' or negedge reset_n)\n'
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result += ' begin\n'
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result += ' begin\n'
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for s in statements:
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for s in statements:
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result += ' ' + s + '\n'
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result += ' ' + s + '\n'
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result += ' end\n'
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result += ' end\n'
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return result
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return result
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class net:
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class net:
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def __init__ (self, type, name, width=1):
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def __init__ (self, type, name, width=1):
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self.width = width
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self.width = width
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self.name = name
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self.name = name
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self.type = type
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self.type = type
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def declaration (self):
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def declaration (self):
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if (self.width == 1):
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if (self.width == 1):
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return self.type + ' ' + self.name + ';'
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return self.type + ' ' + self.name + ';'
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else:
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else:
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return "%s [%d:0] %s;" % (self.type, self.width-1, self.name)
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return "%s [%d:0] %s;" % (self.type, self.width-1, self.name)
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class port:
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class port:
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def __init__ (self, direction, name, width=1):
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def __init__ (self, direction, name, width=1):
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self.direction = direction
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self.direction = direction
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self.width = width
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self.width = width
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self.name = name
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self.name = name
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def declaration (self):
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def declaration (self):
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if (self.width == 1):
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if (self.width == 1):
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return self.direction + ' ' + self.name + ';'
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return self.direction + ' ' + self.name + ';'
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else:
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else:
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return "%s [%d:0] %s;" % (self.direction, self.width-1, self.name)
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return "%s [%d:0] %s;" % (self.direction, self.width-1, self.name)
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class decoder_range:
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def __init__ (self, name, base, bits):
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self.name = name
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self.base = base
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self.bits = bits
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def check_range(self):
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mask = (1 << self.bits) - 1
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if (self.base & mask):
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return 1
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else: return 0
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def get_base_addr(self):
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return self.base
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class decoder_group:
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def __init__ (self, mem_mapped=0):
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self.addr_size = 16
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self.data_size = 8
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self.name = ''
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self.ranges = []
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self.ports = [port ('input', 'clk'), port('input','reset_n')]
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self.nets = []
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self.blocks = []
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def build (self):
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self.ports.append (port ('input', 'cfgi_irdy'))
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self.ports.append (port ('output', 'cfgi_trdy'))
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self.ports.append (port ('input', 'cfgi_write'))
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self.ports.append (port ('input', 'cfgi_addr', self.addr_size))
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self.ports.append (port ('input', 'cfgi_wr_data', self.data_size))
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self.ports.append (port ('output', 'cfgo_wr_data', self.data_size))
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self.ports.append (port ('output', 'cfgi_rd_data', self.data_size))
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self.ports.append (port ('output', 'cfgo_addr', self.addr_size))
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self.ports.append (port ('output', 'cfgo_write'))
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self.nets.append (net('reg','cfgi_rd_data',self.data_size))
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self.nets.append (net('reg','nxt_rd_data',self.data_size))
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self.nets.append (net('reg', 'nxt_cfgi_trdy'))
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self.nets.append (net('reg', 'irdy_out'))
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self.nets.append (net('reg', 'trdy_out'))
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self.nets.append (net('reg', 'cfgo_wr_data', self.data_size))
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self.nets.append (net('reg', 'cfgo_addr', self.addr_size))
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self.nets.append (net ('reg', 'cfgo_write'))
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self.nets.append (net ('reg', 'cfgi_trdy'))
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self.blocks.append ( """
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always @(posedge clk or negedge reset_n)
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begin
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if (~reset_n)
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begin
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irdy_out <= #1 0;
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cfgo_wr_data <= #1 0;
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cfgo_addr <= #1 0;
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cfgo_write <= #1 0;
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cfgi_trdy <= #1 0;
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end
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else
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begin
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irdy_out <= #1 (irdy_out) ? !trdy_out : cfgi_irdy & ~cfgi_trdy;
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cfgi_trdy <= #1 irdy_out & trdy_out;
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if (cfgi_irdy & !irdy_out)
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begin
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cfgo_wr_data <= #1 cfgi_wr_data;
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cfgo_addr <= #1 cfgi_addr;
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cfgo_write <= #1 cfgi_write;
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end
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if (trdy_out & !cfgo_write)
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cfgi_rd_data <= #1 nxt_rd_data;
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end // else: !if(reset)
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end // always @ (posedge clk)\n""")
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addr_mux = ["casez (cfgo_addr)\n"]
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for r in self.ranges:
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self.ports.append (port ('output', r.name + "_irdy"))
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self.ports.append (port ('input', r.name + "_trdy"))
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self.ports.append (port ('input', r.name + "_rd_data", self.data_size))
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self.nets.append (net('reg', r.name + "_irdy"))
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addr_mux.insert(0, "%s_irdy = 0;" % r.name)
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base_addr = int2bin (r.base)
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#for b in range(-r.bits,0):
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# base_addr[b] = 'z'
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fill = self.addr_size - len(base_addr)
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if (fill > 0):
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base_addr = '0' * fill + base_addr
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base_addr = base_addr[:-r.bits] + 'z'*r.bits
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addr_mux.append ("%d'b%s :" % (self.addr_size, base_addr))
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addr_mux.append ("begin")
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addr_mux.append ("%s_irdy = irdy_out;" % r.name)
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addr_mux.append ("trdy_out = %s_trdy;" % r.name)
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addr_mux.append ("nxt_rd_data = %s_rd_data;" % r.name)
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addr_mux.append ("end")
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addr_mux.append("""
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default :
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begin
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trdy_out = 1'b1;
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nxt_rd_data = 0;
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end
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endcase\n""")
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self.blocks.append (comb_block(addr_mux))
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def verilog (self):
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self.build()
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result = 'module ' + self.name + ' (\n'
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result += string.join (map (lambda x: x.name, self.ports), ',')
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result += ');\n'
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# print port list
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for p in self.ports:
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result += p.declaration() + '\n'
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# print net list
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for n in self.nets:
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result += n.declaration() + '\n'
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# create all blocks in block list
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for b in self.blocks:
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result += b
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result += 'endmodule\n'
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return result
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def add_range (self, r):
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self.ranges.append (r)
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class register_group:
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class register_group:
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def __init__ (self, mem_mapped=0):
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def __init__ (self, mem_mapped=0):
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self.base_addr = 0
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self.base_addr = 0
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self.addr_size = 16
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self.addr_size = 16
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self.data_size = 8
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self.data_size = 8
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self.name = ''
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self.name = ''
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self.local_width = 1
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self.local_width = 1 # number of address bits consumed
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self.registers = []
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self.registers = []
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self.ports = [port ('input', 'clk'), port('input','reset')]
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self.ports = [port ('input', 'clk'), port('input','reset_n')]
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self.nets = []
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self.nets = []
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self.interrupts = 0
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self.interrupts = 0 # if interrupt registers present
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if (mem_mapped):
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self.user = 0 # if user-defined registers present
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self.req_pin = 'mreq_n'
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self.blocks = []
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else:
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self.registered_read = 0
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self.req_pin = 'iorq_n'
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self.hold_regs = 0
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self.tv80_intf()
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self.hold_inputs = []
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def tv80_intf (self):
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def top_intf (self):
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self.ports.append (port ('input', 'addr', self.addr_size))
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self.ports.append (port ('input', 'rf_irdy'))
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self.ports.append (port ('input', 'wr_data', self.data_size))
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self.ports.append (port ('output', 'rf_trdy'))
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self.ports.append (port ('output', 'rd_data', self.data_size))
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self.ports.append (port ('input', 'rf_write'))
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self.ports.append (port ('output', 'doe'))
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self.ports.append (port ('input', 'rf_addr', self.addr_size))
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self.ports.append (port ('input','rd_n'))
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self.ports.append (port ('input', 'rf_wr_data', self.data_size))
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self.ports.append (port ('input', 'wr_n'))
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self.ports.append (port ('output', 'rf_rd_data', self.data_size))
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self.ports.append (port ('input', self.req_pin))
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self.nets.append (net('reg','rf_rd_data',self.data_size))
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self.nets.append (net('reg','rd_data',self.data_size))
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self.nets.append (net('reg', 'nxt_rf_trdy'))
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self.nets.append (net('reg','block_select'))
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if (self.registered_read):
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self.nets.append (net('reg','doe'))
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self.nets.append (net('reg','nxt_rf_rd_data',self.data_size))
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for i in range(0,self.hold_regs):
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self.nets.append (net('reg',"xxhold_%d" % i,self.data_size))
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self.nets.append (net('reg',"nxt_xxhold_%d" % i,self.data_size))
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self.nets.append (net('reg', 'rf_trdy'))
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def build_load_mux (self):
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for i in range(0,self.hold_regs):
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nn = "nxt_xxhold_%d" % i
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txt = []
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for hi,nregs in self.hold_inputs:
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high = (i+1) * self.data_size - 1
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low = i* self.data_size
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if (i < nregs):
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txt.append ("if (%s_rd_stb) %s = %s_in[%d:%d];" % (hi, nn, hi, high, low))
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txt.append ("else if (%s_%d_wr_sel) %s = rf_wr_data; else " % (hi, i, nn))
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txt.append("%s = xxhold_%d;" % (nn, i))
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self.blocks.append (comb_block(txt))
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# create a hook for post-processing to be done after all data has been
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# create a hook for post-processing to be done after all data has been
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# added to the object.
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# added to the object.
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def post (self):
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def post (self):
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self.top_intf()
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for reg in self.registers:
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self.ports.extend (reg.io())
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self.nets.extend (reg.nets())
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#self.local_width = int(math.ceil (log2 (len (self.registers))))
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self.local_width = self.addr_size;
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rnum = 0
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for r in self.registers:
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r.offset = rnum
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rnum += 1
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self.build_load_mux()
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if (self.interrupts):
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if (self.interrupts):
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self.int_ports()
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self.int_ports()
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# create port for interrupt pin, as well as port for data output enable
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# create port for interrupt pin, as well as port for data output enable
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# when interrupt is asserted.
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# when interrupt is asserted.
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# This block should be called after all register data has been read.
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# This block should be called after all register data has been read.
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def int_ports (self):
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def int_ports (self):
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self.ports.append (port ('output','int_n'))
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self.ports.append (port ('output','int_n'))
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self.nets.append (net ('reg','int_n'))
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self.nets.append (net ('reg','int_n'))
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self.nets.append (net ('reg','int_vec',self.data_size))
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#self.nets.append (net ('reg','int_vec',self.data_size))
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def int_logic (self):
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def int_logic (self):
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statements = []
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int_nets = []
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int_nets = []
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for r in self.registers:
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for r in self.registers:
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if r.interrupt: int_nets.append (r.name + "_int")
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if r.interrupt: int_nets.append (r.name + "_int")
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statements.append ("int_n = ~(" + string.join (int_nets, ' | ') + ");")
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self.blocks.append (comb_block (["int_n = ~(" + string.join (int_nets, ' | ') + ");"]))
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return comb_block (statements)
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def wait_logic (self):
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wait_nets = []
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for r in self.registers:
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if r.type() == 'user':
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wait_nets.append (r.name + "_wait_n")
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elif r.type() == 'ext_load':
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if r.eindex == 0:
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wait_nets.append (r.name + "_wait_n")
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if (len(wait_nets) > 0):
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self.blocks.append (comb_block (["if (rf_trdy) nxt_rf_trdy = 0;",
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"else if (rf_irdy) nxt_rf_trdy = " + ' & '.join (wait_nets) + ";",
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"else nxt_rf_trdy = 0;"]))
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else:
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self.blocks.append (comb_block (["if (rf_trdy) nxt_rf_trdy = 0;",
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"else if (rf_irdy) nxt_rf_trdy = 1;",
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"else nxt_rf_trdy = 0;"]))
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self.blocks.append (seq_block ("clk", ["if (~reset_n) rf_trdy <= #1 0;",
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"else rf_trdy <= #1 nxt_rf_trdy;"]))
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#if (len(wait_nets) > 0):
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# self.blocks.append (comb_block (["wait_n = " + string.join (wait_nets, ' & ') + ";"]))
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if (self.registered_read):
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self.blocks.append (seq_block ("clk", ["if (~reset_n) rf_rd_data <= #1 0;", "else if (nxt_rf_trdy) rf_rd_data <= #1 nxt_rf_rd_data;"]))
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for i in range (0,self.hold_regs):
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self.blocks.append (seq_block ("clk", ["if (~reset_n) xxhold_%d <= 0;"%i,"else xxhold_%d <= nxt_xxhold_%d;" % (i, i)]))
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def global_logic (self):
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def global_logic (self):
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# create select pin for this block
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# create select pin for this block
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statements = ["block_select = (addr[%d:%d] == %d) & !%s;" % (self.addr_size-1,self.local_width,self.base_addr >> self.local_width, self.req_pin)]
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statements = []
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# create read and write selects for each register
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# create read and write selects for each register
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for r in self.registers:
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for r in self.registers:
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slogic = "block_select & (addr[%d:%d] == %d) & !rd_n" % (self.local_width-1,0,r.offset)
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slogic = "(rf_addr[%d:%d] == %d) & rf_irdy & !rf_write" % (self.local_width-1,0,r.offset)
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#if r.interrupt:
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#if r.interrupt:
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# slogic = "%s_int | (%s)" % (r.name, slogic)
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# slogic = "%s_int | (%s)" % (r.name, slogic)
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s = "%s_rd_sel = %s;" % (r.name,slogic)
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s = "%s_rd_sel = %s;" % (r.name,slogic)
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statements.append (s)
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statements.append (s)
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if r.write_cap():
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if r.write_cap():
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s = "%s_wr_sel = block_select & (addr[%d:%d] == %d) & !wr_n;" % (r.name,self.local_width-1,0,r.offset)
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s = "%s_wr_sel = (rf_addr[%d:%d] == %d) & rf_irdy & rf_write;\n" % (r.name,self.local_width-1,0,r.offset)
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statements.append (s)
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statements.append (s)
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return comb_block (statements)
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return comb_block (statements)
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def read_mux (self):
|
def read_mux (self):
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s = ''
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s = ''
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sments = []
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sments = []
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rd_sel_list = []
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rd_sel_list = []
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# Old code for simple tri-state interface
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#for r in self.registers:
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# s += "assign rd_data = (%s_rd_sel) ? %s : %d'bz;\n" % (r.name, r.name, self.data_size)
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# create interrupt address mux
|
|
if (self.interrupts):
|
|
sments.append ("case (1'b1)")
|
|
for r in self.registers:
|
|
if r.interrupt:
|
|
sments.append (" %s_int : int_vec = %d;" % (r.name, r.int_value))
|
|
sments.append (" default : int_vec = %d'bx;" % self.data_size)
|
|
sments.append ("endcase")
|
|
|
|
# create data-output mux
|
# create data-output mux
|
sments.append ("case (1'b1)")
|
sments.append ("case (1'b1)")
|
|
if (self.registered_read):
|
|
rd_target = "nxt_rf_rd_data"
|
|
else:
|
|
rd_target = "rf_rd_data"
|
for r in self.registers:
|
for r in self.registers:
|
sments.append (" %s_rd_sel : rd_data = %s;" % (r.name, r.name))
|
sments.append (" %s_rd_sel : %s = %s;" % (r.name, rd_target, r.name))
|
rd_sel_list.append (r.name + "_rd_sel")
|
rd_sel_list.append (r.name + "_rd_sel")
|
if (self.interrupts):
|
#if (self.interrupts):
|
sments.append (" default : rd_data = int_vec;")
|
# sments.append (" default : rd_data = int_vec;")
|
else: sments.append (" default : rd_data = %d'bx;" % self.data_size)
|
sments.append (" default : %s = %d'b0;" % (rd_target, self.data_size))
|
sments.append ("endcase")
|
sments.append ("endcase")
|
|
|
sments.append ("doe = %s;" % string.join (rd_sel_list, ' | '))
|
#sments.append ("doe = %s;" % string.join (rd_sel_list, ' | '))
|
|
|
return comb_block (sments)
|
return comb_block (sments)
|
|
|
|
|
def verilog (self):
|
def verilog (self):
|
self.post()
|
self.post()
|
|
|
result = 'module ' + self.name + ' (\n'
|
result = 'module ' + self.name + ' (\n'
|
result += string.join (map (lambda x: x.name, self.ports), ',')
|
result += string.join (map (lambda x: x.name, self.ports), ',')
|
result += ');\n'
|
result += ');\n'
|
|
|
# print port list
|
# print port list
|
for p in self.ports:
|
for p in self.ports:
|
result += p.declaration() + '\n'
|
result += p.declaration() + '\n'
|
|
|
# print net list
|
# print net list
|
for n in self.nets:
|
for n in self.nets:
|
result += n.declaration() + '\n'
|
result += n.declaration() + '\n'
|
|
|
# create global logic
|
# create global logic
|
result += self.global_logic()
|
result += self.global_logic()
|
result += self.read_mux()
|
result += self.read_mux()
|
if (self.interrupts > 0): result += self.int_logic()
|
if (self.interrupts > 0): self.int_logic()
|
|
self.wait_logic()
|
|
|
|
# create all blocks in block list
|
|
for b in self.blocks:
|
|
result += b
|
|
|
# print function blocks
|
# print function blocks
|
for r in self.registers:
|
for r in self.registers:
|
result += r.verilog_body()
|
result += r.verilog_body()
|
|
|
result += 'endmodule\n'
|
result += 'endmodule\n'
|
return result
|
return result
|
|
|
|
# calculate number of holding registers required and update
|
|
# hold_regs internal property
|
|
def calc_hold (self, width):
|
|
hregs = width / self.data_size
|
|
if (width % self.data_size) != 0:
|
|
hregs += 1
|
|
if (hregs > self.hold_regs):
|
|
self.hold_regs = hregs
|
|
return hregs
|
|
|
def add_register (self, type, params):
|
def add_register (self, type, params):
|
#def add_register (self, name, type, width):
|
#def add_register (self, name, type, width):
|
if (type == 'status'):
|
if (type == 'status'):
|
self.add (status_reg (params['name'],params['width']))
|
self.add (status_reg (params['name'],params['width']))
|
elif (type == 'config'):
|
elif (type == 'config'):
|
self.add (config_reg (params['name'],params['width'],params['default']))
|
self.add (config_reg (params['name'],params['width'],params['default']))
|
elif (type == 'int_fixed'):
|
elif (type == 'int_msk'):
|
r2 = config_reg (params['name'] + "_msk",params['width'],params['default'])
|
r2 = config_reg (params['name'] + "_msk",params['width'],params['default'])
|
r1 = int_fixed_reg (params['name'],r2,number(params['int_value']),params['width'])
|
r1 = int_msk_reg (params['name'],r2,params['width'])
|
self.add (r1)
|
self.add (r1)
|
self.add (r2)
|
self.add (r2)
|
self.interrupts += 1
|
self.interrupts += 1
|
elif (type == 'soft_set'):
|
elif (type == 'soft_set'):
|
self.add (soft_set_reg(params['name'],params['width'],params['default']))
|
self.add (soft_set_reg(params['name'],params['width'],params['default']))
|
elif (type == 'read_stb'):
|
elif (type == 'read_stb'):
|
self.add (read_stb_reg (params['name'],params['width']))
|
self.add (read_stb_reg (params['name'],params['width']))
|
elif (type == 'write_stb'):
|
elif (type == 'write_stb'):
|
self.add (write_stb_reg (params['name'],params['width'],params['default']))
|
self.add (write_stb_reg (params['name'],params['width'],params['default']))
|
elif (type == 'hw_load'):
|
elif (type == 'user'):
|
self.add (hw_load_reg (params['name'],params['width']))
|
self.user = 1
|
|
self.add (user_reg (params['name'],params['width']))
|
|
elif (type == 'ext_load'):
|
|
width = params['width']
|
|
regs = self.calc_hold (width)
|
|
print "ext_load %s, splitting into %d regs" % (params['name'],regs)
|
|
for i in range(0,regs):
|
|
last = (i == (regs-1))
|
|
self.add (ext_load_reg(params['name'],self.data_size,i,params['width'],last))
|
|
self.hold_inputs.append ( (params['name'], regs) )
|
|
elif (type == 'count'):
|
|
self.add (count_reg (params['name'],params['width']))
|
else:
|
else:
|
print "Unknown register type",type
|
print "Unknown register type",type
|
|
|
def add (self, reg):
|
def add (self, reg):
|
self.registers.append (reg)
|
self.registers.append (reg)
|
self.ports.extend (reg.io())
|
#self.ports.extend (reg.io())
|
self.nets.extend (reg.nets())
|
#self.nets.extend (reg.nets())
|
self.local_width = int(math.ceil (log2 (len (self.registers))))
|
#self.local_width = int(math.ceil (log2 (len (self.registers))))
|
rnum = 0
|
#rnum = 0
|
for r in self.registers:
|
#for r in self.registers:
|
r.offset = rnum
|
# r.offset = rnum
|
rnum += 1
|
# rnum += 1
|
|
|
class basic_register:
|
class basic_register:
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0):
|
self.offset = 0
|
self.offset = 0
|
self.width = width
|
self.width = width
|
self.name = name
|
self.name = name
|
self.interrupt = 0
|
self.interrupt = 0
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
pass
|
pass
|
|
|
|
def type (self):
|
|
return 'basic'
|
|
|
def io (self):
|
def io (self):
|
return []
|
return []
|
|
|
def nets (self):
|
def nets (self):
|
return []
|
return []
|
|
|
def write_cap (self):
|
def write_cap (self):
|
return 0
|
return 0
|
|
|
def id_comment (self):
|
def id_comment (self):
|
return "// register: %s\n" % self.name
|
return "// %s: %s\n" % (self.type(), self.name)
|
|
|
class status_reg (basic_register):
|
class status_reg (basic_register):
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0):
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
|
|
|
def type (self):
|
|
return 'status'
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
return ''
|
return self.id_comment()
|
|
|
def io (self):
|
def io (self):
|
return [port('input', self.name, self.width)]
|
return [port('input', self.name, self.width)]
|
|
|
def nets (self):
|
def nets (self):
|
return [ net('reg', self.name + '_rd_sel')]
|
return [ net('reg', self.name + '_rd_sel')]
|
|
|
|
class ext_load_reg (basic_register):
|
|
def __init__ (self, name='', width=0, eindex=0, twidth=0, last=0):
|
|
basic_register.__init__(self, name+"_%d" % eindex, width)
|
|
self.fullname = name
|
|
self.eindex = eindex
|
|
self.twidth = twidth
|
|
self.last = last
|
|
print "Adding %s eindex %d" % (name, eindex)
|
|
|
|
def type (self): return "ext_load"
|
|
|
|
def write_cap (self): return 1
|
|
|
|
def verilog_body (self):
|
|
print "Building %s eindex %d" % (self.name, self.eindex)
|
|
|
|
txt = ""
|
|
low = self.eindex * self.width
|
|
high = (self.eindex + 1) * self.width - 1
|
|
txt += "assign %s = xxhold_%d;\n" % (self.name, self.eindex)
|
|
txt += "assign %s_out[%d:%d] = xxhold_%d;\n" % (self.fullname, high, low, self.eindex)
|
|
if (self.eindex == 0):
|
|
#txt += "assign %s_rd_stb = %s_rd_sel & !rf_trdy;\n" % (self.fullname,self.name)
|
|
sm = state_machine ("sm_" + self.name)
|
|
sm.add_state ('idle')
|
|
sm.add_state ('rd_req')
|
|
sm.add_state ('done')
|
|
|
|
sm.add_trans ('idle','rd_req',self.name+"_rd_sel", self.name+"_wait_n = 0")
|
|
sm.add_trans ('rd_req','done',"1'b1")
|
|
sm.add_moore ('rd_req',self.name+"_wait_n = 1'b0")
|
|
sm.add_moore ('rd_req',self.fullname+"_rd_stb = 1'b1")
|
|
|
|
sm.add_trans ('done','idle',"~%s_rd_sel" % self.name)
|
|
|
|
sm.add_default (self.fullname+"_rd_stb", "1'b0")
|
|
sm.add_default (self.name+"_wait_n", "1'b1")
|
|
txt += sm.verilog()
|
|
|
|
if (self.last):
|
|
txt += seq_block ("clk", ["if (~reset_n) %s_wr_stb <= 1'b0;" % self.fullname,
|
|
"else %s_wr_stb <= %s_%d_wr_sel;" % (self.fullname,self.fullname,self.eindex)])
|
|
return txt
|
|
|
|
def nets (self):
|
|
nets = [net('reg', self.name + '_rd_sel'),
|
|
net('reg', self.name + '_wr_sel'),
|
|
net('wire', self.name, self.width)]
|
|
if (self.eindex == 0):
|
|
nets.append (net('reg', self.name + "_wait_n"))
|
|
nets.append (net('reg',"sm_%s_state" % self.name, 2))
|
|
nets.append (net('reg',"nxt_sm_%s_state" % self.name, 2))
|
|
if (self.last):
|
|
nets.append (net('reg', self.fullname + '_rd_stb'))
|
|
nets.append (net('reg', self.fullname + '_wr_stb'))
|
|
return nets
|
|
|
|
def io (self):
|
|
# ports are all tied to the 0 eindex register
|
|
plist = []
|
|
if (self.eindex == 0):
|
|
plist.append (port('input', self.fullname+"_in", self.twidth))
|
|
plist.append (port('output', self.fullname+"_out", self.twidth))
|
|
plist.append (port('output', self.fullname+"_rd_stb", 1))
|
|
plist.append (port('output', self.fullname+"_wr_stb", 1))
|
|
return plist
|
|
|
|
|
class config_reg (basic_register):
|
class config_reg (basic_register):
|
def __init__ (self, name='', width=0, default=0):
|
def __init__ (self, name='', width=0, default=0):
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
self.default = default
|
self.default = default
|
|
self.fields = []
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
vstr = self.id_comment()
|
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data')
|
statements = ["if (%s_wr_sel) nxt_%s = %s;" % (self.name, self.name, 'rf_wr_data'),
|
]
|
"else nxt_%s = %s;" % tuple([self.name] * 2)]
|
return self.id_comment() + seq_block ('clk', statements)
|
vstr += comb_block (statements)
|
|
statements = ["if (~reset_n) %s <= #1 %d'h%x;" % (self.name, self.width, self.default),
|
|
"else %s <= #1 nxt_%s;" % tuple([self.name] * 2)]
|
|
|
|
vstr += seq_block ('clk', statements)
|
|
if (len(self.fields) != 0):
|
|
vstr += "assign {"
|
|
vstr += ','.join (map(lambda(x):x.name,self.fields))
|
|
vstr += "} = %s;\n" % self.name
|
|
return vstr
|
|
|
|
def type (self):
|
|
return 'config'
|
|
|
def io (self):
|
def io (self):
|
|
if (len(self.fields) == 0):
|
return [ port('output',self.name, self.width) ]
|
return [ port('output',self.name, self.width) ]
|
|
else:
|
|
plist = []
|
|
for fld in self.fields:
|
|
plist.append (port ('output', fld.name, fld.width))
|
|
return plist
|
|
|
def nets (self):
|
def nets (self):
|
return [ net('reg', self.name, self.width),
|
return [ net('reg', self.name, self.width),
|
|
net('reg', "nxt_"+self.name, self.width),
|
net('reg', self.name + '_rd_sel'),
|
net('reg', self.name + '_rd_sel'),
|
net('reg', self.name + '_wr_sel')]
|
net('reg', self.name + '_wr_sel')]
|
|
|
def write_cap (self):
|
def write_cap (self):
|
return 1
|
return 1
|
|
|
class hw_load_reg (config_reg):
|
class count_reg (config_reg):
|
def __init__ (self, name='', width=0, default=0):
|
def __init__ (self, name='', width=0, default=0):
|
basic_register.__init__(self, name, width)
|
config_reg.__init__(self, name, width)
|
self.default = default
|
self.default = default
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
txt = self.id_comment()
|
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data'),
|
alist = (self.name, self.name, self.width, self.name, self.name)
|
"else if (%s_load) %s <= %s_wrdata;" % (self.name,self.name,self.name)
|
statements = [
|
|
"if (%s_wr_sel) nxt_%s = %s;" % (self.name, self.name, 'rf_wr_data'),
|
|
"else if (%s_inc && (%s != {%d{1'b1}})) nxt_%s = %s + 1;" % alist,
|
|
"else nxt_%s = %s;" % (self.name,self.name)
|
]
|
]
|
return self.id_comment() + seq_block ('clk', statements)
|
txt += comb_block (statements)
|
|
statements = ["if (~reset_n) %s <= #1 %d;" % (self.name, self.default),
|
|
"else %s <= #1 nxt_%s;" % (self.name, self.name)
|
|
]
|
|
txt += seq_block ('clk', statements)
|
|
return txt
|
|
|
def io (self):
|
def io (self):
|
return [ port('input', self.name+'_wrdata', self.width),
|
return [ port('input',self.name + "_inc", 1) ]
|
port('input', self.name+'_load', 1),
|
|
port('output',self.name, self.width) ]
|
|
|
|
def nets (self):
|
class int_msk_reg (basic_register):
|
return [ net('reg', self.name, self.width),
|
def __init__ (self, name, mask_reg, width=0):
|
net('reg', self.name + '_rd_sel'),
|
|
net('reg', self.name + '_wr_sel')]
|
|
|
|
def write_cap (self):
|
|
return 1
|
|
|
|
|
|
class int_fixed_reg (basic_register):
|
|
def __init__ (self, name, mask_reg, int_value, width=0):
|
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
self.mask_reg = mask_reg
|
self.mask_reg = mask_reg
|
self.interrupt = 1
|
self.interrupt = 1
|
self.int_value = int_value
|
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, 0),
|
text = self.id_comment()
|
"else %s <= (%s_set | %s) & ~( {%d{%s}} & %s);" %
|
statements = ["nxt_%s = (%s_set | %s) & ~( {%d{%s}} & %s);" % (self.name, self.name, self.name, self.width, self.name + '_wr_sel', 'rf_wr_data')]
|
(self.name, self.name, self.name, self.width, self.name + '_wr_sel', 'wr_data'),
|
statements += ["nxt_%s_int = |(%s & ~%s);" % (self.name, self.name, self.mask_reg.name)]
|
"if (reset) %s_int <= 0;" % self.name,
|
text += comb_block (statements)
|
"else %s_int <= |(%s & ~%s);" % (self.name, self.name, self.mask_reg.name)
|
statements = ["if (~reset_n) %s <= #1 %d;" % (self.name, 0),
|
|
"else %s <= #1 nxt_%s;" % (self.name, self.name)]
|
|
text += seq_block ('clk', statements)
|
|
statements = ["if (~reset_n) %s_int <= #1 0;" % self.name,
|
|
"else %s_int <= nxt_%s_int;" % (self.name, self.name)
|
]
|
]
|
return self.id_comment() + seq_block ('clk', statements)
|
text += seq_block ('clk', statements)
|
|
return text
|
|
|
|
def type (self):
|
|
return 'int_msk'
|
|
|
def io (self):
|
def io (self):
|
return [ port('input',self.name+"_set", self.width) ]
|
return [ port('input',self.name+"_set", self.width) ]
|
|
|
def nets (self):
|
def nets (self):
|
return [ net('reg', self.name + '_rd_sel'),
|
return [ net('reg', self.name + '_rd_sel'),
|
net('reg', self.name, self.width),
|
net('reg', self.name, self.width),
|
|
net('reg', "nxt_"+self.name, self.width),
|
net('reg', self.name + '_wr_sel'),
|
net('reg', self.name + '_wr_sel'),
|
|
net('reg', 'nxt_'+self.name + '_int'),
|
net('reg', self.name + '_int')]
|
net('reg', self.name + '_int')]
|
|
|
def write_cap (self):
|
def write_cap (self):
|
return 1
|
return 1
|
|
|
class soft_set_reg (basic_register):
|
class soft_set_reg (config_reg):
|
def __init__ (self, name='', width=0, default=0):
|
def __init__ (self, name='', width=0, default=0):
|
basic_register.__init__(self, name, width)
|
basic_register.__init__(self, name, width)
|
self.default = default
|
self.default = default
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
txt = self.id_comment()
|
"else %s <= ( ({%d{%s}} & %s) | %s) & ~(%s);" %
|
statements = [
|
(self.name, self.width, self.name+'_wr_sel', 'wr_data',
|
"nxt_%s = ( ({%d{%s}} & %s) | %s) & ~(%s);" %
|
|
(self.name, self.width, self.name+'_wr_sel', 'rf_wr_data',
|
self.name, self.name + '_clr')
|
self.name, self.name + '_clr')
|
]
|
]
|
return self.id_comment() + seq_block ('clk', statements)
|
txt += comb_block (statements)
|
|
statements = ["if (~reset_n) %s <= #1 %d;" % (self.name, self.default),
|
|
"else %s <= #1 nxt_%s;" % (self.name, self.name)
|
|
]
|
|
txt += seq_block ('clk', statements)
|
|
if (len(self.fields) != 0):
|
|
txt += "assign {"
|
|
txt += ','.join (map(lambda(x):x.name,self.fields))
|
|
txt += "} = %s;\n" % self.name
|
|
return txt
|
|
|
|
def type (self):
|
|
return 'soft_set'
|
|
|
def io (self):
|
def io (self):
|
return [ port('output',self.name, self.width),
|
return config_reg.io(self) + [port ('input',self.name+"_clr", self.width)]
|
port ('input',self.name+"_clr", self.width)]
|
|
|
|
def nets (self):
|
#def nets (self):
|
return [ net('reg', self.name, self.width),
|
# return [ net('reg', self.name, self.width),
|
net('reg', self.name + '_rd_sel'),
|
# net('reg', "nxt_"+self.name, self.width),
|
net('reg', self.name + '_wr_sel')]
|
# net('reg', self.name + '_rd_sel'),
|
|
# net('reg', self.name + '_wr_sel')]
|
|
|
def write_cap (self):
|
#def write_cap (self):
|
return 1
|
# return 1
|
|
|
class write_stb_reg (config_reg):
|
class write_stb_reg (config_reg):
|
def __init__ (self, name='', width=0, default=0):
|
def __init__ (self, name='', width=0, default=0):
|
config_reg.__init__(self, name, width, default)
|
config_reg.__init__(self, name, width, default)
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = ["if (reset) %s <= %d;" % (self.name, self.default),
|
txt = self.id_comment()
|
"else if (%s_wr_sel) %s <= %s;" % (self.name, self.name, 'wr_data'),
|
statements = [
|
"if (reset) %s_stb <= 0;" % (self.name),
|
"if (%s_wr_sel) nxt_%s = %s;" % (self.name, self.name, 'rf_wr_data'),
|
"else if (%s_wr_sel) %s_stb <= 1;" % (self.name, self.name),
|
"else nxt_%s = %s;" % (self.name, self.name)]
|
"else %s_stb <= 0;" % (self.name)
|
txt += comb_block (statements)
|
|
statements = ["if (~reset_n) %s <= #1 %d;" % (self.name, self.default),
|
|
"else %s <= #1 nxt_%s;" % (self.name, self.name)]
|
|
txt += seq_block('clk',statements)
|
|
statements = [
|
|
"if (~reset_n) %s_stb <= #1 0;" % (self.name),
|
|
"else %s_stb <= #1 %s_wr_sel & rf_trdy;" % (self.name, self.name),
|
]
|
]
|
return seq_block ('clk', statements)
|
txt += seq_block ('clk', statements)
|
|
|
|
if (len(self.fields) != 0):
|
|
txt += "assign {"
|
|
txt += ','.join (map(lambda(x):x.name,self.fields))
|
|
txt += "} = %s;\n" % self.name
|
|
|
|
return txt+seq_block ('clk', statements)
|
|
|
|
def type (self):
|
|
return 'write_stb'
|
|
|
def io (self):
|
def io (self):
|
io_list = config_reg.io (self)
|
io_list = config_reg.io (self)
|
io_list.append ( port('output',self.name+"_stb") )
|
io_list.append ( port('output',self.name+"_stb") )
|
return io_list
|
return io_list
|
|
|
def nets (self):
|
def nets (self):
|
net_list = config_reg.nets (self)
|
net_list = config_reg.nets (self)
|
net_list.append ( net('reg', self.name + "_stb") )
|
net_list.append ( net('reg', self.name + "_stb") )
|
return net_list
|
return net_list
|
|
|
class read_stb_reg (status_reg):
|
class read_stb_reg (status_reg):
|
def __init__ (self, name='', width=0):
|
def __init__ (self, name='', width=0):
|
status_reg.__init__(self, name, width)
|
status_reg.__init__(self, name, width)
|
|
|
def verilog_body (self):
|
def verilog_body (self):
|
statements = [
|
statements = [
|
"if (reset) %s_stb <= 0;" % (self.name),
|
"if (~reset_n) %s_stb <= #1 0;" % (self.name),
|
"else if (%s_rd_sel) %s_stb <= 1;" % (self.name, self.name),
|
"else %s_stb <= #1 %s_rd_sel & rf_trdy;" % (self.name, self.name),
|
"else %s_stb <= 0;" % (self.name)
|
|
]
|
]
|
return self.id_comment() + seq_block ('clk', statements)
|
return self.id_comment() + seq_block ('clk', statements)
|
|
|
|
def type (self):
|
|
return 'read_stb'
|
|
|
def io (self):
|
def io (self):
|
io_list = status_reg.io (self)
|
io_list = status_reg.io (self)
|
io_list.append (port('output',self.name+"_stb"))
|
io_list.append (port('output',self.name+"_stb"))
|
return io_list
|
return io_list
|
|
|
def nets (self):
|
def nets (self):
|
net_list = status_reg.nets(self)
|
net_list = status_reg.nets(self)
|
net_list.append (net('reg',self.name + '_stb'))
|
net_list.append (net('reg',self.name + '_stb'))
|
return net_list
|
return net_list
|
|
|
No newline at end of file
|
No newline at end of file
|
|
class state_machine:
|
|
def __init__ (self, name='', clk="clk", reset="reset_n"):
|
|
self.name = name
|
|
self.states = {}
|
|
self.trans = []
|
|
self.clk = clk
|
|
self.reset = reset
|
|
self.idle = ""
|
|
self.defaults = []
|
|
|
|
def add_state (self, name):
|
|
self.states[name] = []
|
|
if (self.idle == ""):
|
|
self.idle = name
|
|
|
|
def add_trans (self, st_from, st_to, cond, asrt=''):
|
|
self.states[st_from].append ( (st_to, cond, asrt) )
|
|
|
|
def add_moore (self, st_name, asrt):
|
|
self.states[st_name].append ( (st_name, '1', asrt) )
|
|
|
|
def add_default (self, signal, value):
|
|
self.defaults.append ( (signal, value) )
|
|
|
|
def verilog (self):
|
|
code = "// state machine %s\n" % self.name
|
|
|
|
# create state names
|
|
snum = 0
|
|
for st in self.states.keys():
|
|
code += "parameter st_%s_%s = %d;\n" % (self.name, st, snum)
|
|
snum += 1
|
|
|
|
# create combinatorial block
|
|
cblk = []
|
|
for d in self.defaults:
|
|
cblk.append ( "%s = %s;" % d)
|
|
cblk.append ("%s = %s;" % ("nxt_" + self.name + "_state", self.name + "_state"))
|
|
cblk.append ("case (%s)" % (self.name + "_state"))
|
|
for st in self.states.keys():
|
|
cblk.append ( "st_%s_%s : " % (self.name, st))
|
|
cblk.append ( " begin")
|
|
first = 1
|
|
moore = []
|
|
for c in self.states[st]:
|
|
if (c[0] == st) and (c[1] == "1"):
|
|
moore.append (c[2])
|
|
else:
|
|
if (not first): statement = " else if"
|
|
else:
|
|
statement = " if"
|
|
first = 0
|
|
cblk.append ( "%s (%s)" % (statement, c[1]))
|
|
cblk.append (" begin")
|
|
if (c[0] != st):
|
|
cblk.append ( " nxt_%s_state = st_%s_%s;" % (self.name, self.name, c[0]))
|
|
if (c[2] != ""):
|
|
cblk.append ( " " + c[2] + ";")
|
|
cblk.append ( " end")
|
|
for m in moore:
|
|
cblk.append (" %s;" % m)
|
|
cblk.append (" end")
|
|
cblk.append ( "endcase")
|
|
code += comb_block (cblk)
|
|
|
|
# create sequential block
|
|
cblk = []
|
|
cblk.append ("if(~%s)" % self.reset)
|
|
cblk.append ("%s_state <= #1 st_%s_%s;" % (self.name, self.name, self.idle))
|
|
cblk.append ("else")
|
|
cblk.append ("%s_state <= #1 nxt_%s_state;" % (self.name, self.name))
|
|
code += seq_block (self.clk, cblk)
|
|
return code
|
|
|
|
class user_reg (basic_register):
|
|
def __init__ (self, name='', width=0):
|
|
basic_register.__init__(self, name, width)
|
|
|
|
def io (self):
|
|
io_list = []
|
|
io_list.append (port('output',self.name+"_wr_stb"))
|
|
io_list.append (port('output',self.name+"_rd_stb"))
|
|
io_list.append (port('output',self.name+"_wr_data", self.width))
|
|
io_list.append (port('input',self.name+"_rd_data",self.width))
|
|
io_list.append (port('input',self.name+"_rd_ack"))
|
|
io_list.append (port('input',self.name+"_wr_ack"))
|
|
return io_list
|
|
|
|
def type (self):
|
|
return 'user'
|
|
|
|
def nets (self):
|
|
net_list = []
|
|
net_list.append (net('reg',self.name+"_rd_sel"))
|
|
net_list.append (net('reg',self.name+"_wr_sel"))
|
|
net_list.append (net('reg',self.name+"_rd_stb"))
|
|
net_list.append (net('reg',self.name+"_wr_stb"))
|
|
net_list.append (net('reg',self.name+"_wait_n"))
|
|
net_list.append (net('reg',self.name,self.width))
|
|
net_list.append (net('reg',self.name+"_wr_data",self.width))
|
|
net_list.append (net('reg',"sm_%s_state" % self.name, 2))
|
|
net_list.append (net('reg',"nxt_sm_%s_state" % self.name, 2))
|
|
return net_list
|
|
|
|
def write_cap (self):
|
|
return 1
|
|
|
|
def verilog_body (self):
|
|
sm = state_machine ("sm_" + self.name)
|
|
sm.add_state ('idle')
|
|
sm.add_state ('rd_req')
|
|
sm.add_state ('wr_req')
|
|
sm.add_state ('w_clear')
|
|
#sm.add_state ('rd_ack')
|
|
#sm.add_state ('wr_ack')
|
|
sm.add_trans ('idle','rd_req',self.name+"_rd_sel", self.name+"_wait_n = 0")
|
|
sm.add_trans ('idle','wr_req',self.name+"_wr_sel", self.name+"_wait_n = 0")
|
|
sm.add_trans ('rd_req', 'w_clear', self.name+"_rd_ack", "")
|
|
#sm.add_trans ('rd_req', 'rd_ack', '1','')
|
|
sm.add_trans ('rd_req', 'rd_req', "!"+self.name+"_rd_ack", self.name+"_wait_n = 0")
|
|
sm.add_moore ('rd_req', self.name+"_rd_stb = 1")
|
|
sm.add_moore ('wr_req', self.name+"_wr_stb = 1")
|
|
sm.add_trans ('wr_req', 'w_clear', self.name+"_wr_ack", "")
|
|
sm.add_trans ('wr_req', 'wr_req', "!"+self.name+"_wr_ack", self.name+"_wait_n = 0")
|
|
|
|
# added w_clear to avoid duplicate requests on interface
|
|
sm.add_trans ('w_clear', 'idle', "~(%s_rd_sel | %s_wr_sel)" % (self.name,self.name), "")
|
|
|
|
sm.add_default (self.name+"_rd_stb", "0")
|
|
sm.add_default (self.name+"_wr_stb", "0")
|
|
sm.add_default (self.name+"_wait_n", "1")
|
|
|
|
comb = comb_block (["%s_wr_data = rf_wr_data;" % self.name,
|
|
"%s = %s_rd_data;" % (self.name, self.name)])
|
|
|
|
return sm.verilog() + comb
|
|
|
No newline at end of file
|
No newline at end of file
|