//
|
//
|
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
//
|
//
|
// Permission is hereby granted, free of charge, to any person obtaining a
|
// Permission is hereby granted, free of charge, to any person obtaining a
|
// copy of this software and associated documentation files (the "Software"),
|
// copy of this software and associated documentation files (the "Software"),
|
// to deal in the Software without restriction, including without limitation
|
// to deal in the Software without restriction, including without limitation
|
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
// and/or sell copies of the Software, and to permit persons to whom the
|
// and/or sell copies of the Software, and to permit persons to whom the
|
// Software is furnished to do so, subject to the following conditions:
|
// Software is furnished to do so, subject to the following conditions:
|
//
|
//
|
// The above copyright notice and this permission notice shall be included
|
// The above copyright notice and this permission notice shall be included
|
// in all copies or substantial portions of the Software.
|
// in all copies or substantial portions of the Software.
|
//
|
//
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
//
|
//
|
|
|
sfr at 0x18 uart_dm0;
|
sfr at 0x18 uart_dm0;
|
sfr at 0x19 uart_dm1;
|
sfr at 0x19 uart_dm1;
|
sfr at 0x1a uart_iir;
|
sfr at 0x1a uart_iir;
|
sfr at 0x1b uart_lcr;
|
sfr at 0x1b uart_lcr;
|
sfr at 0x1c uart_mcr;
|
sfr at 0x1c uart_mcr;
|
sfr at 0x1d uart_lsr;
|
sfr at 0x1d uart_lsr;
|
sfr at 0x1e uart_msr;
|
sfr at 0x1e uart_msr;
|
sfr at 0x1f uart_scr;
|
sfr at 0x1f uart_scr;
|
|
|
sfr at 0x80 sim_ctl_port;
|
sfr at 0x80 sim_ctl_port;
|
sfr at 0x81 msg_port;
|
sfr at 0x81 msg_port;
|
sfr at 0x82 timeout_port;
|
sfr at 0x82 timeout_port;
|
|
|
// THR (transmit holding register) is DM0
|
// THR (transmit holding register) is DM0
|
// RBR (receive buffer register) is also DM0
|
// RBR (receive buffer register) is also DM0
|
|
|
void print (char *string)
|
void print (char *string)
|
{
|
{
|
char *iter;
|
char *iter;
|
|
|
iter = string;
|
iter = string;
|
while (*iter != 0) {
|
while (*iter != 0) {
|
msg_port = *iter++;
|
msg_port = *iter++;
|
}
|
}
|
}
|
}
|
|
|
char rxbuf[128];
|
char rxbuf[128];
|
|
|
void test_byte (unsigned char pattern) {
|
void test_byte (unsigned char pattern) {
|
unsigned char status, data;
|
unsigned char status, data;
|
|
|
// send a byte through the UART
|
// send a byte through the UART
|
uart_dm0 = pattern;
|
uart_dm0 = pattern;
|
|
|
// wait for byte to be received
|
// wait for byte to be received
|
do {
|
do {
|
status = uart_lsr;
|
status = uart_lsr;
|
} while ((status & 0x01) == 0);
|
} while ((status & 0x01) == 0);
|
|
|
// fail if status byte indicates anything other
|
// fail if status byte indicates anything other
|
// than data ready and transmitter empty
|
// than data ready and transmitter empty
|
if (status != 0x61) {
|
if (status != 0x61) {
|
print ("Incorrect status byte\n");
|
print ("Incorrect status byte\n");
|
sim_ctl_port = 0x02;
|
sim_ctl_port = 0x02;
|
}
|
}
|
|
|
// read the sent byte and fail if it's not what we sent
|
// read the sent byte and fail if it's not what we sent
|
data = uart_dm0;
|
data = uart_dm0;
|
if (data != pattern) {
|
if (data != pattern) {
|
print ("Data miscompare\n");
|
print ("Data miscompare\n");
|
sim_ctl_port = 0x02;
|
sim_ctl_port = 0x02;
|
}
|
}
|
}
|
}
|
|
|
int main ()
|
int main ()
|
{
|
{
|
//print ("Hello, world!\n");
|
//print ("Hello, world!\n");
|
|
|
int i, rx_count;
|
int i, rx_count;
|
|
|
// set divisor to 100
|
// set divisor to 100
|
uart_lcr = 0x8b;
|
uart_lcr = 0x8b;
|
uart_dm0 = 0x02;
|
uart_dm0 = 0x02;
|
uart_dm1 = 0x00;
|
uart_dm1 = 0x00;
|
|
|
// line settings:
|
// line settings:
|
// 8 bits, 1 stop bit, even parity
|
// 8 bits, 1 stop bit, even parity
|
uart_lcr = 0x0b;
|
uart_lcr = 0x0b;
|
|
|
// turn on internal loopback in UART
|
// turn on internal loopback in UART
|
uart_mcr = 0x10;
|
uart_mcr = 0x10;
|
test_byte (0x55);
|
test_byte (0x55);
|
test_byte (0x1F);
|
test_byte (0x1F);
|
|
|
// turn off loopback and use external loop
|
// turn off loopback and use external loop
|
uart_mcr = 0x00;
|
uart_mcr = 0x00;
|
test_byte (0xAA);
|
test_byte (0xAA);
|
test_byte (0xBD);
|
test_byte (0xBD);
|
|
|
// maybe do a checksum here
|
// maybe do a checksum here
|
sim_ctl_port = 0x01;
|
sim_ctl_port = 0x01;
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|