//
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/**********************************************************************
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// File: mtx_trps_8x8_dpsram.v
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* File : mtx_trps_8x8_dpsram.v
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// Author: Ivan Rezki
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* Author: Ivan Rezki
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// Topic: RTL Core
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* email : irezki@gmail.com
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// 2-Dimensional Fast Hartley Transform
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* Topic : RTL Core
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//
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* 2-Dimensional Fast Hartley Transform
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*
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// Matrix Transpose 8x8
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*
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// DPSRAM-based Double Buffer
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* Matrix Transpose 8x8
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// Buffer size is 64*2 words, each word is 16 bits
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* DPSRAM-based Double Buffer
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* Buffer size is 64*2 words, each word is 16 bits
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// Matrix Transpose -> 64 clk delay
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*
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// - Double Buffer Solution:
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* Matrix Transpose -> 64 clk delay
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* - Double Buffer Solution:
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*
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* RIGHT TO USE: This code example, or any portion thereof, may be
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* used and distributed without restriction, provided that this entire
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* comment block is included with the example.
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*
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* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
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* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
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* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
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* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
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* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
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* USE OF THIS CODE.
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**********************************************************************/
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module mtx_trps_8x8_dpsram (
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module mtx_trps_8x8_dpsram (
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rstn,
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rstn,
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sclk,
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sclk,
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// Input
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// Input
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inp_valid,
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inp_valid,
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inp_data,
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inp_data,
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// Output
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// Output
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mem_data,
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mem_data,
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mem_valid
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mem_valid
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);
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);
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parameter N = 8;
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parameter N = 8;
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input rstn;
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input rstn;
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input sclk;
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input sclk;
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input inp_valid;
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input inp_valid;
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input [N-1:0] inp_data;
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input [N-1:0] inp_data;
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output [N-1:0] mem_data;
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output [N-1:0] mem_data;
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output mem_valid;
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output mem_valid;
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reg [6:0] cnt128d_wr; // Write Mode Counter
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reg [6:0] cnt128d_wr; // Write Mode Counter
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wire indicator; // 64 words written - Indication(pos. or neg. edge)
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wire indicator; // 64 words written - Indication(pos. or neg. edge)
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reg indicator_1d; // Indication 1 clock delay
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reg indicator_1d; // Indication 1 clock delay
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wire indicator_pos_edge; // positive edge
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wire indicator_pos_edge; // positive edge
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wire indicator_neg_edge; // negative edge
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wire indicator_neg_edge; // negative edge
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reg [6:0] cnt128d_rd; // Read Counter
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reg [6:0] cnt128d_rd; // Read Counter
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wire cnt128d_rd_valid_start; // Counter start increment
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wire cnt128d_rd_valid_start; // Counter start increment
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wire cnt128d_rd_valid_stop; // Counter stop increment
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wire cnt128d_rd_valid_stop; // Counter stop increment
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reg cnt128d_rd_valid; // valid time for cnt128d_rd counter
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reg cnt128d_rd_valid; // valid time for cnt128d_rd counter
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reg mem_valid; // 1 clock delay after reading
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reg mem_valid; // 1 clock delay after reading
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// DPSRAM Memory Signal Description
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// DPSRAM Memory Signal Description
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wire [15:0] wr_DATA;
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wire [15:0] wr_DATA;
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wire [ 6:0] wr_ADDR;
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wire [ 6:0] wr_ADDR;
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wire wr_CSN;
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wire wr_CSN;
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wire wr_WEN;
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wire wr_WEN;
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wire [15:0] rd_DATA;
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wire [ 6:0] rd_ADDR;
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wire [ 6:0] rd_ADDR;
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wire rd_CSN;
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wire rd_CSN;
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`ifdef USE_FPGA_SPSRAM
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wire [15:0] rd_DATA;
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dpsram_128x16 u_dpsram(
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dpsram_128x16 u_dpsram(
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.addra (wr_ADDR),
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.addra (wr_ADDR),
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.addrb (rd_ADDR),
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.addrb (rd_ADDR),
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.clka (sclk),
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.clka (sclk),
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.clkb (sclk),
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.clkb (sclk),
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.dina (wr_DATA),
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.dina (wr_DATA),
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.dinb ({16{1'b0}}),
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.dinb ({16{1'b0}}),
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.douta (/* OPEN */),
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.douta (/* OPEN */),
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.doutb (rd_DATA),
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.doutb (rd_DATA),
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.ena (wr_CSN),
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.ena (wr_CSN),
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.enb (rd_CSN),
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.enb (rd_CSN),
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.wea (wr_WEN),
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.wea (wr_WEN),
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.web (1'b1)
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.web (1'b1)
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);
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);
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`endif
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`ifdef USE_ASIC_SPSRAM
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reg [15:0] rd_DATA = 16'd0;
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reg [15:0] sram[0:127];
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always @(posedge sclk)
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if (~wr_WEN && ~wr_CSN) sram[wr_ADDR] <= wr_DATA; // Write
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always @(posedge sclk)
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if ( 1'b1 && ~rd_CSN) rd_DATA <= sram[rd_ADDR]; // Read
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`endif
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always @(posedge sclk or negedge rstn)
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always @(posedge sclk or negedge rstn)
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if (!rstn) cnt128d_wr <= #1 0;
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if (!rstn) cnt128d_wr <= #1 0;
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else if (inp_valid) cnt128d_wr <= #1 cnt128d_wr + 1;
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else if (inp_valid) cnt128d_wr <= #1 cnt128d_wr + 1;
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assign wr_DATA = {{16-N{1'b0}},inp_data};
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assign wr_DATA = {{16-N{1'b0}},inp_data};
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assign wr_ADDR = cnt128d_wr;
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assign wr_ADDR = cnt128d_wr;
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assign wr_CSN = ~inp_valid;
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assign wr_CSN = ~inp_valid;
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assign wr_WEN = ~inp_valid;
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assign wr_WEN = ~inp_valid;
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// Start Reading After fisrt 64 words had been written
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// Start Reading After fisrt 64 words had been written
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assign indicator = cnt128d_wr[6];
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assign indicator = cnt128d_wr[6];
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always @(posedge sclk or negedge rstn)
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always @(posedge sclk or negedge rstn)
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if (!rstn) indicator_1d <= #1 1'b0;
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if (!rstn) indicator_1d <= #1 1'b0;
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else indicator_1d <= #1 indicator;
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else indicator_1d <= #1 indicator;
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assign indicator_pos_edge = indicator & ~indicator_1d;
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assign indicator_pos_edge = indicator & ~indicator_1d;
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assign indicator_neg_edge = ~indicator & indicator_1d;
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assign indicator_neg_edge = ~indicator & indicator_1d;
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assign cnt128d_rd_valid_start = indicator_pos_edge | indicator_neg_edge;
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assign cnt128d_rd_valid_start = indicator_pos_edge | indicator_neg_edge;
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assign cnt128d_rd_valid_stop = (cnt128d_rd[5:0] == 63) ? 1'b1 : 1'b0;
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assign cnt128d_rd_valid_stop = (cnt128d_rd[5:0] == 63) ? 1'b1 : 1'b0;
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always @(posedge sclk or negedge rstn)
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always @(posedge sclk or negedge rstn)
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if (!rstn) cnt128d_rd_valid <= #1 1'b0;
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if (!rstn) cnt128d_rd_valid <= #1 1'b0;
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else if (cnt128d_rd_valid_start)cnt128d_rd_valid <= #1 1'b1;
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else if (cnt128d_rd_valid_start)cnt128d_rd_valid <= #1 1'b1;
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else if (cnt128d_rd_valid_stop) cnt128d_rd_valid <= #1 1'b0;
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else if (cnt128d_rd_valid_stop) cnt128d_rd_valid <= #1 1'b0;
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// Read Mode Counter
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// Read Mode Counter
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always @(posedge sclk or negedge rstn)
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always @(posedge sclk or negedge rstn)
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if (!rstn) cnt128d_rd <= #1 1'b0;
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if (!rstn) cnt128d_rd <= #1 1'b0;
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else if (cnt128d_rd_valid) cnt128d_rd <= #1 cnt128d_rd + 1;
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else if (cnt128d_rd_valid) cnt128d_rd <= #1 cnt128d_rd + 1;
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assign rd_ADDR = {cnt128d_rd[6],cnt128d_rd[2:0],cnt128d_rd[5:3]};
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assign rd_ADDR = {cnt128d_rd[6],cnt128d_rd[2:0],cnt128d_rd[5:3]};
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assign rd_CSN = ~cnt128d_rd_valid;
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assign rd_CSN = ~cnt128d_rd_valid;
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// Output
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// Output
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always @(posedge sclk or negedge rstn)
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always @(posedge sclk or negedge rstn)
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if (!rstn) mem_valid <= #1 1'b0;
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if (!rstn) mem_valid <= #1 1'b0;
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else mem_valid <= #1 cnt128d_rd_valid;
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else mem_valid <= #1 cnt128d_rd_valid;
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assign #1 mem_data = rd_DATA[N-1:0];
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assign #1 mem_data = rd_DATA[N-1:0];
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// synopsys translate_off
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// synopsys translate_off
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// <<<------------- DUMP Section
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// <<<------------- DUMP Section
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/*
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// 2D FHT OUTPUT DUMP DATA
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// 2D FHT OUTPUT DUMP DATA
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parameter MEM_TRPS_DPSRAM_FILE = "./result/mem_trps_dpsram.txt";
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parameter MEM_TRPS_DPSRAM_FILE = "./result/mem_trps_dpsram.txt";
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integer mem_trps_dpsram_dump;
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integer mem_trps_dpsram_dump;
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initial mem_trps_dpsram_dump = $fopen(MEM_TRPS_DPSRAM_FILE);
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initial mem_trps_dpsram_dump = $fopen(MEM_TRPS_DPSRAM_FILE);
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always @(posedge sclk)
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always @(posedge sclk)
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if (mem_valid) $fdisplay(mem_trps_dpsram_dump,"%h",mem_data);
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if (mem_valid) $fdisplay(mem_trps_dpsram_dump,"%h",mem_data);
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*/
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// synopsys translate_on
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// synopsys translate_on
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endmodule
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endmodule
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