//
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/**********************************************************************
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// File: signed_mult_const_fpga.v
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* File : signed_mult_const_fpga.v
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// Author: Ivan Rezki
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* Author: Ivan Rezki
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// Topic: RTL Core
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* email : irezki@gmail.com
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// 2-Dimensional Fast Hartley Transform
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* Topic : RTL Core
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//
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* 2-Dimensional Fast Hartley Transform
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*
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// Signed Multiplier - constant sqrt(2) = 1.41421
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*
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* Function: Signed Multiplier - constant sqrt(2) = 1.41421
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// 8 bit accuracy:
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*
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// 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
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* 8 bit accuracy:
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// product = 362*a/2^8
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* 1.41421*a = (256*1.41421)*a/256 = 362.03776*a/256 = 362*a/256
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// wire [8:0] mult_constant = 9'd362;
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* product = 362*a/2^8
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* wire [8:0] mult_constant = 9'd362;
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// 15 bit accuracy:
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*
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// 1.41421*a = (32768*1.41421)*a/32768 = 46340.95*a/32768
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* 15 bit accuracy:
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// product = 46341*a/2^15
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* 1.41421*a = (32768*1.41421)*a/32768 = 46340.95*a/32768
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// wire [15:0] mult_constant = 16'd46341;
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* product = 46341*a/2^15
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* wire [15:0] mult_constant = 16'd46341;
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// 16 bit accuracy:
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*
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// 1.41421*a = (65536*1.41421)*a/65536 = 92681*a/65536
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* 16 bit accuracy:
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// product = 92681*a/2^16
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* 1.41421*a = (65536*1.41421)*a/65536 = 92681*a/65536
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// wire [16:0] mult_constant = 17'd92681;
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* product = 92681*a/2^16
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* wire [16:0] mult_constant = 17'd92681;
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*
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* RIGHT TO USE: This code example, or any portion thereof, may be
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* used and distributed without restriction, provided that this entire
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* comment block is included with the example.
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*
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* DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
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* OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
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* TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
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* EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
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* INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
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* USE OF THIS CODE.
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**********************************************************************/
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module signed_mult_const_fpga (
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module signed_mult_const_fpga (
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rstn,
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rstn,
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clk,
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clk,
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valid,
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valid,
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a,
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a,
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p
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p
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);
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);
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parameter N = 8;
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parameter N = 8;
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input rstn;
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input rstn;
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input clk;
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input clk;
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input valid;
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input valid;
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input signed [N-1:0] a; // variable - positive/negative
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input signed [N-1:0] a; // variable - positive/negative
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output signed [N :0] p; // product output
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output signed [N :0] p; // product output
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// FHT constant
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// FHT constant
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// wire [8:0] mult_constant; // always positive
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// wire [8:0] mult_constant; // always positive
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// assign mult_constant = 9'd362;
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// assign mult_constant = 9'd362;
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wire signed [17:0] mult_constant; // always positive
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wire signed [17:0] mult_constant; // always positive
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assign mult_constant = {1'b0, 17'd92681};
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assign mult_constant = {1'b0, 17'd92681};
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reg signed [N-1:0] a_FF;
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reg signed [N-1:0] a_FF;
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always @(posedge clk)
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always @(posedge clk)
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if (!rstn) a_FF <= #1 0;
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if (!rstn) a_FF <= #1 0;
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else if (valid) a_FF <= #1 a;
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else if (valid) a_FF <= #1 a;
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wire signed [(16+1)+N-1:0] p_tmp = $signed(a_FF) * $signed(mult_constant);
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wire signed [(16+1)+N-1:0] p_tmp = $signed(a_FF) * $signed(mult_constant);
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//assign p = p_tmp[(16+1)+N-1:16];// >> 16;
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//assign p = p_tmp[(16+1)+N-1:16];// >> 16;
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assign p = p_tmp >> 16;
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assign p = p_tmp >> 16;
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endmodule
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endmodule
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