--===========================================================================--
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--===========================================================================--
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--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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--
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-- www.OpenCores.Org - January 2000
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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-- Design units : miniUART core for the OCRP-1
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-- Design units : miniUART core for the OCRP-1
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--
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--
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-- File name : clkUnit.vhd
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-- File name : clkUnit.vhd
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--
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the OR1K processor and the Host computer through
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-- between the OR1K processor and the Host computer through
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-- an RS-232 communication protocol.
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-- an RS-232 communication protocol.
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--
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--
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-- Library : uart_lib.vhd
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-- Library : uart_lib.vhd
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--
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--
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-- Dependencies : IEEE.Std_Logic_1164
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-- Dependencies : IEEE.Std_Logic_1164
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--
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--
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--===========================================================================--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision list
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-- Revision list
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-- Version Author Date Changes
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-- Version Author Date Changes
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--
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- ovilup@mail.dnttm.ro
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-- ovilup@mail.dnttm.ro
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Generates the Baud clock and enable signals for RX & TX
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-- Description : Generates the Baud clock and enable signals for RX & TX
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-- units.
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-- units.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Entity for Baud rate generator Unit - 9600 baudrate --
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-- Entity for Baud rate generator Unit - 9600 baudrate --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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library work;
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use work.UART_Def.all;
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use work.UART_Def.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Baud rate generator
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-- Baud rate generator
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity ClkUnit is
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entity ClkUnit is
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port (
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port (
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SysClk : in Std_Logic; -- System Clock
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SysClk : in Std_Logic; -- System Clock
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EnableRx : out Std_Logic; -- Control signal
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EnableRx : out Std_Logic; -- Control signal
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EnableTx : out Std_Logic; -- Control signal
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EnableTx : out Std_Logic; -- Control signal
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Reset : in Std_Logic); -- Reset input
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Reset : in Std_Logic); -- Reset input
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end entity; --================== End of entity ==============================--
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end entity; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for Baud rate generator Unit
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-- Architecture for Baud rate generator Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture Behaviour of ClkUnit is
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architecture Behaviour of ClkUnit is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal ClkDiv26 : Std_Logic;
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signal ClkDiv26 : Std_Logic;
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signal tmpEnRX : Std_Logic;
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signal tmpEnRX : Std_Logic;
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signal tmpEnTX : Std_Logic;
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signal tmpEnTX : Std_Logic;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Divides the system clock of 40 MHz by 26
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-- Divides the system clock of 40 MHz by 26
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DivClk26 : process(SysClk,Reset)
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DivClk26 : process(SysClk,Reset)
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constant CntOne : unsigned(4 downto 0) := "00001";
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constant CntOne : unsigned(4 downto 0) := "00001";
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variable Cnt26 : unsigned(4 downto 0);
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variable Cnt26 : unsigned(4 downto 0);
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begin
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begin
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if Rising_Edge(SysClk) then
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if Rising_Edge(SysClk) then
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if Reset = '0' then
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if Reset = '0' then
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Cnt26 := "00000";
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Cnt26 := "00000";
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ClkDiv26 <= '0';
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ClkDiv26 <= '0';
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else
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else
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Cnt26 := Cnt26 + CntOne;
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Cnt26 := Cnt26 + CntOne;
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case Cnt26 is
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case Cnt26 is
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when "11010" =>
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when "11010" =>
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ClkDiv26 <= '1';
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ClkDiv26 <= '1';
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Cnt26 := "00000";
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Cnt26 := "00000";
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when others =>
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when others =>
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ClkDiv26 <= '0';
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ClkDiv26 <= '0';
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Provides the EnableRX signal, at ~ 155 KHz
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-- Provides the EnableRX signal, at ~ 155 KHz
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DivClk10 : process(SysClk,Reset,Clkdiv26)
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DivClk10 : process(SysClk,Reset,Clkdiv26)
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constant CntOne : unsigned(3 downto 0) := "0001";
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constant CntOne : unsigned(3 downto 0) := "0001";
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variable Cnt10 : unsigned(3 downto 0);
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variable Cnt10 : unsigned(3 downto 0);
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begin
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begin
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if Rising_Edge(SysClk) then
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if Rising_Edge(SysClk) then
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if Reset = '0' then
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if Reset = '0' then
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Cnt10 := "0000";
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Cnt10 := "0000";
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tmpEnRX <= '0';
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tmpEnRX <= '0';
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elsif ClkDiv26 = '1' then
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elsif ClkDiv26 = '1' then
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Cnt10 := Cnt10 + CntOne;
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Cnt10 := Cnt10 + CntOne;
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end if;
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end if;
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case Cnt10 is
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case Cnt10 is
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when "1010" =>
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when "1010" =>
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tmpEnRX <= '1';
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tmpEnRX <= '1';
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Cnt10 := "0000";
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Cnt10 := "0000";
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when others =>
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when others =>
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tmpEnRX <= '0';
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tmpEnRX <= '0';
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Provides the EnableTX signal, at 9.6 KHz
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-- Provides the EnableTX signal, at 9.6 KHz
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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DivClk16 : process(SysClk,Reset,tmpEnRX)
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DivClk16 : process(SysClk,Reset,tmpEnRX)
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constant CntOne : unsigned(4 downto 0) := "00001";
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constant CntOne : unsigned(4 downto 0) := "00001";
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variable Cnt16 : unsigned(4 downto 0);
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variable Cnt16 : unsigned(4 downto 0);
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begin
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begin
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if Rising_Edge(SysClk) then
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if Rising_Edge(SysClk) then
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if Reset = '0' then
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if Reset = '0' then
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Cnt16 := "00000";
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Cnt16 := "00000";
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tmpEnTX <= '0';
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tmpEnTX <= '0';
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elsif tmpEnRX = '1' then
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elsif tmpEnRX = '1' then
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Cnt16 := Cnt16 + CntOne;
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Cnt16 := Cnt16 + CntOne;
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end if;
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end if;
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case Cnt16 is
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case Cnt16 is
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when "01111" =>
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when "01111" =>
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tmpEnTX <= '1';
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tmpEnTX <= '1';
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Cnt16 := Cnt16 + CntOne;
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Cnt16 := Cnt16 + CntOne;
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when "10010" =>
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when "10010" =>
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Cnt16 := "00000";
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Cnt16 := "00000";
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when others =>
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when others =>
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tmpEnTX <= '0';
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tmpEnTX <= '0';
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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|
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EnableRX <= tmpEnRX;
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EnableRX <= tmpEnRX;
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EnableTX <= tmpEnTX;
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EnableTX <= tmpEnTX;
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