--===========================================================================--
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--===========================================================================--
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--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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--
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-- www.OpenCores.Org - January 2000
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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--
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--
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-- Design units : miniUART core for the OCRP-1
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-- Design units : miniUART core for the OCRP-1
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--
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--
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-- File name : RxUnit.vhd
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-- File name : RxUnit.vhd
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--
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the OR1K processor and the Host computer through
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-- between the OR1K processor and the Host computer through
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-- an RS-232 communication protocol.
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-- an RS-232 communication protocol.
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--
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--
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-- Library : uart_lib.vhd
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-- Library : uart_lib.vhd
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--
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--
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-- Dependencies : IEEE.Std_Logic_1164
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-- Dependencies : IEEE.Std_Logic_1164
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--
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--
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--===========================================================================--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision list
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-- Revision list
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-- Version Author Date Changes
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-- Version Author Date Changes
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--
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
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-- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
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-- olupas@opencores.org
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-- olupas@opencores.org
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Implements the receive unit of the miniUART core. Samples
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-- Description : Implements the receive unit of the miniUART core. Samples
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-- 16 times the RxD line and retain the value in the middle of
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-- 16 times the RxD line and retain the value in the middle of
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-- the time interval.
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-- the time interval.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Entity for Receive Unit - 9600 baudrate --
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-- Entity for Receive Unit - 9600 baudrate --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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library work;
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use work.UART_Def.all;
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use work.UART_Def.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Receive unit
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-- Receive unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity RxUnit is
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entity RxUnit is
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port (
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port (
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Clk : in Std_Logic; -- system clock signal
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Clk : in Std_Logic; -- system clock signal
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Reset : in Std_Logic; -- Reset input
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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Enable : in Std_Logic; -- Enable input
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RxD : in Std_Logic; -- RS-232 data input
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RxD : in Std_Logic; -- RS-232 data input
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RD : in Std_Logic; -- Read data signal
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RD : in Std_Logic; -- Read data signal
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FErr : out Std_Logic; -- Status signal
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FErr : out Std_Logic; -- Status signal
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OErr : out Std_Logic; -- Status signal
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OErr : out Std_Logic; -- Status signal
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DRdy : out Std_Logic; -- Status signal
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DRdy : out Std_Logic; -- Status signal
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DataIn : out Std_Logic_Vector(7 downto 0));
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DataIn : out Std_Logic_Vector(7 downto 0));
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end entity; --================== End of entity ==============================--
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end entity; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for receive Unit
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-- Architecture for receive Unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture Behaviour of RxUnit is
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architecture Behaviour of RxUnit is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal Start : Std_Logic; -- Syncro signal
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signal Start : Std_Logic; -- Syncro signal
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signal tmpRxD : Std_Logic; -- RxD buffer
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signal tmpRxD : Std_Logic; -- RxD buffer
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signal tmpDRdy : Std_Logic; -- Data ready buffer
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signal tmpDRdy : Std_Logic; -- Data ready buffer
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signal outErr : Std_Logic; --
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signal outErr : Std_Logic; --
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signal frameErr : Std_Logic; --
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signal frameErr : Std_Logic; --
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signal BitCnt : Unsigned(3 downto 0); --
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signal BitCnt : Unsigned(3 downto 0); --
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signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
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signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
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signal ShtReg : Std_Logic_Vector(7 downto 0); --
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signal ShtReg : Std_Logic_Vector(7 downto 0); --
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signal DOut : Std_Logic_Vector(7 downto 0); --
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signal DOut : Std_Logic_Vector(7 downto 0); --
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begin
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begin
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Receiver process
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-- Receiver process
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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RcvProc : process(Clk,Reset,Enable,RxD)
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RcvProc : process(Clk,Reset,Enable,RxD)
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variable tmpBitCnt : Integer range 0 to 15;
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variable tmpBitCnt : Integer range 0 to 15;
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variable tmpSampleCnt : Integer range 0 to 15;
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variable tmpSampleCnt : Integer range 0 to 15;
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constant CntOne : Unsigned(3 downto 0):="0001";
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constant CntOne : Unsigned(3 downto 0):="0001";
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begin
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begin
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if Rising_Edge(Clk) then
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if Rising_Edge(Clk) then
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tmpBitCnt := ToInteger(BitCnt);
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tmpBitCnt := ToInteger(BitCnt);
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tmpSampleCnt := ToInteger(SampleCnt);
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tmpSampleCnt := ToInteger(SampleCnt);
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if Reset = '0' then
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if Reset = '0' then
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BitCnt <= "0000";
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BitCnt <= "0000";
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SampleCnt <= "0000";
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SampleCnt <= "0000";
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Start <= '0';
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Start <= '0';
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tmpDRdy <= '0';
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tmpDRdy <= '0';
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frameErr <= '0';
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frameErr <= '0';
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outErr <= '0';
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outErr <= '0';
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ShtReg <= "00000000"; --
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ShtReg <= "00000000"; --
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DOut <= "00000000"; --
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DOut <= "00000000"; --
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else
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else
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if RD = '1' then
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if RD = '1' then
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tmpDRdy <= '0'; -- Data was read
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tmpDRdy <= '0'; -- Data was read
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end if;
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end if;
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if Enable = '1' then
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if Enable = '1' then
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if Start = '0' then
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if Start = '0' then
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if RxD = '0' then -- Start bit,
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if RxD = '0' then -- Start bit,
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SampleCnt <= SampleCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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Start <= '1';
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Start <= '1';
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end if;
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end if;
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else
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else
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if tmpSampleCnt = 8 then -- reads the RxD line
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if tmpSampleCnt = 8 then -- reads the RxD line
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tmpRxD <= RxD;
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tmpRxD <= RxD;
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SampleCnt <= SampleCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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elsif tmpSampleCnt = 15 then
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elsif tmpSampleCnt = 15 then
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case tmpBitCnt is
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case tmpBitCnt is
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when 0 =>
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when 0 =>
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if tmpRxD = '1' then -- Start Bit
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if tmpRxD = '1' then -- Start Bit
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Start <= '0';
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Start <= '0';
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else
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else
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BitCnt <= BitCnt + CntOne;
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BitCnt <= BitCnt + CntOne;
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end if;
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end if;
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SampleCnt <= SampleCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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when 1|2|3|4|5|6|7|8 =>
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when 1|2|3|4|5|6|7|8 =>
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BitCnt <= BitCnt + CntOne;
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BitCnt <= BitCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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ShtReg <= tmpRxD & ShtReg(7 downto 1);
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ShtReg <= tmpRxD & ShtReg(7 downto 1);
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when 9 =>
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when 9 =>
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if tmpRxD = '0' then -- stop bit expected
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if tmpRxD = '0' then -- stop bit expected
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frameErr <= '1';
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frameErr <= '1';
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else
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else
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frameErr <= '0';
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frameErr <= '0';
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end if;
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end if;
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if tmpDRdy = '1' then --
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if tmpDRdy = '1' then --
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outErr <= '1';
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outErr <= '1';
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else
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else
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outErr <= '0';
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outErr <= '0';
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end if;
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end if;
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tmpDRdy <= '1';
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tmpDRdy <= '1';
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DOut <= ShtReg;
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DOut <= ShtReg;
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BitCnt <= "0000";
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BitCnt <= "0000";
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Start <= '0';
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Start <= '0';
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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else
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else
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SampleCnt <= SampleCnt + CntOne;
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SampleCnt <= SampleCnt + CntOne;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DRdy <= tmpDRdy;
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DRdy <= tmpDRdy;
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DataIn <= DOut;
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DataIn <= DOut;
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FErr <= frameErr;
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FErr <= frameErr;
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OErr <= outErr;
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OErr <= outErr;
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