--===========================================================================--
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--===========================================================================--
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--
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--
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-- S Y N T H E Z I A B L E miniUART C O R E
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-- S Y N T H E Z I A B L E miniUART C O R E
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--
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--
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-- www.OpenCores.Org - January 2000
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-- www.OpenCores.Org - January 2000
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-- This core adheres to the GNU public license
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-- This core adheres to the GNU public license
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--
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--
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-- Design units : miniUART core for the OCRP-1
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-- Design units : miniUART core for the OCRP-1
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--
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--
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-- File name : TxUnit.vhd
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-- File name : TxUnit.vhd
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--
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--
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-- Purpose : Implements an miniUART device for communication purposes
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-- Purpose : Implements an miniUART device for communication purposes
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-- between the OR1K processor and the Host computer through
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-- between the OR1K processor and the Host computer through
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-- an RS-232 communication protocol.
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-- an RS-232 communication protocol.
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--
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--
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-- Library : uart_lib.vhd
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-- Library : uart_lib.vhd
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--
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--
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-- Dependencies : IEEE.Std_Logic_1164
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-- Dependencies : IEEE.Std_Logic_1164
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--
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--
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--===========================================================================--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision list
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-- Revision list
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-- Version Author Date Changes
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-- Version Author Date Changes
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--
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--
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 0.1 Ovidiu Lupas 15 January 2000 New model
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-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
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-- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
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-- olupas@opencores.org
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-- olupas@opencores.org
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description :
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-- Description :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Entity for the Tx Unit --
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-- Entity for the Tx Unit --
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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library work;
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use work.Uart_Def.all;
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use work.Uart_Def.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Transmitter unit
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-- Transmitter unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity TxUnit is
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entity TxUnit is
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port (
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port (
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Clk : in Std_Logic; -- Clock signal
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Clk : in Std_Logic; -- Clock signal
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Reset : in Std_Logic; -- Reset input
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Reset : in Std_Logic; -- Reset input
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Enable : in Std_Logic; -- Enable input
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Enable : in Std_Logic; -- Enable input
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Load : in Std_Logic; -- Load transmit data
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Load : in Std_Logic; -- Load transmit data
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TxD : out Std_Logic; -- RS-232 data output
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TxD : out Std_Logic; -- RS-232 data output
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TRegE : out Std_Logic; -- Tx register empty
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TRegE : out Std_Logic; -- Tx register empty
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TBufE : out Std_Logic; -- Tx buffer empty
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TBufE : out Std_Logic; -- Tx buffer empty
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DataO : in Std_Logic_Vector(7 downto 0));
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DataO : in Std_Logic_Vector(7 downto 0));
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end entity; --================== End of entity ==============================--
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end entity; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Architecture for TxUnit
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-- Architecture for TxUnit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture Behaviour of TxUnit is
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architecture Behaviour of TxUnit is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Signals
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-- Signals
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
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signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
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signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
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signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
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signal BitCnt : Unsigned(3 downto 0); -- bit counter
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signal BitCnt : Unsigned(3 downto 0); -- bit counter
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signal tmpTRegE : Std_Logic; --
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signal tmpTRegE : Std_Logic; --
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signal tmpTBufE : Std_Logic; --
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signal tmpTBufE : Std_Logic; --
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Implements the Tx unit
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-- Implements the Tx unit
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
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process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
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variable tmp_TRegE : Std_Logic;
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variable tmp_TRegE : Std_Logic;
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constant CntOne : Unsigned(3 downto 0):="0001";
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constant CntOne : Unsigned(3 downto 0):="0001";
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begin
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begin
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if Rising_Edge(Clk) then
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if Rising_Edge(Clk) then
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if Reset = '0' then
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if Reset = '0' then
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tmpTRegE <= '1';
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tmpTRegE <= '1';
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tmpTBufE <= '1';
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tmpTBufE <= '1';
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TxD <= '1';
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TxD <= '1';
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BitCnt <= "0000";
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BitCnt <= "0000";
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elsif Load = '1' then
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elsif Load = '1' then
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TBuff <= DataO;
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TBuff <= DataO;
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tmpTBufE <= '0';
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tmpTBufE <= '0';
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elsif Enable = '1' then
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elsif Enable = '1' then
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if ( tmpTBufE = '0') and (tmpTRegE = '1') then
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if ( tmpTBufE = '0') and (tmpTRegE = '1') then
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TReg <= TBuff;
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TReg <= TBuff;
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tmpTRegE <= '0';
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tmpTRegE <= '0';
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-- tmp_TRegE := '0';
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-- tmp_TRegE := '0';
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tmpTBufE <= '1';
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tmpTBufE <= '1';
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-- else
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-- else
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-- tmp_TRegE := tmpTRegE;
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-- tmp_TRegE := tmpTRegE;
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end if;
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end if;
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if tmpTRegE = '0' then
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if tmpTRegE = '0' then
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case BitCnt is
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case BitCnt is
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when "0000" =>
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when "0000" =>
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TxD <= '0';
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TxD <= '0';
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BitCnt <= BitCnt + CntOne;
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BitCnt <= BitCnt + CntOne;
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when "0001" | "0010" | "0011" |
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when "0001" | "0010" | "0011" |
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"0100" | "0101" | "0110" |
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"0100" | "0101" | "0110" |
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"0111" | "1000" =>
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"0111" | "1000" =>
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TxD <= TReg(0);
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TxD <= TReg(0);
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TReg <= '1' & TReg(7 downto 1);
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TReg <= '1' & TReg(7 downto 1);
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BitCnt <= BitCnt + CntOne;
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BitCnt <= BitCnt + CntOne;
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when "1001" =>
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when "1001" =>
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TxD <= '1';
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TxD <= '1';
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TReg <= '1' & TReg(7 downto 1);
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TReg <= '1' & TReg(7 downto 1);
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BitCnt <= "0000";
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BitCnt <= "0000";
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tmpTRegE <= '1';
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tmpTRegE <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
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TRegE <= tmpTRegE;
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TRegE <= tmpTRegE;
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TBufE <= tmpTBufE;
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TBufE <= tmpTBufE;
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