--============================================================================--
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--============================================================================--
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-- Design units : TestBench for miniUART device.
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-- Design units : TestBench for miniUART device.
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--
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--
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-- File name : UARTTest.vhd
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-- File name : UARTTest.vhd
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--
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--
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-- Purpose : Implements the test bench for miniUART device.
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-- Purpose : Implements the test bench for miniUART device.
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--
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--
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-- Library : uart_Lib.vhd
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-- Library : uart_Lib.vhd
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--
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--
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-- Dependencies : IEEE.Std_Logic_1164
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-- Dependencies : IEEE.Std_Logic_1164
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Revision list
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-- Revision list
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-- Version Author Date Changes
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-- Version Author Date Changes
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--
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--
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-- 0.1 Ovidiu Lupas December 1999 New model
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-- 0.1 Ovidiu Lupas December 1999 New model
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Clock generator
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-- Clock generator
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE,work;
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library IEEE,work;
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use IEEE.Std_Logic_1164.all;
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use IEEE.Std_Logic_1164.all;
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--
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--
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entity ClkGen is
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entity ClkGen is
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port (
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port (
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Clk : out Std_Logic); -- Oscillator clock
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Clk : out Std_Logic); -- Oscillator clock
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end ClkGen;--==================== End of entity ==============================--
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end ClkGen;--==================== End of entity ==============================--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Architecture for clock and reset signals generator
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-- Architecture for clock and reset signals generator
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture Behaviour of ClkGen is
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architecture Behaviour of ClkGen is
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begin --========================== Architecture ==============================--
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begin --========================== Architecture ==============================--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Provide the system clock signal
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-- Provide the system clock signal
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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ClkDriver : process
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ClkDriver : process
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variable clktmp : Std_Logic := '1';
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variable clktmp : Std_Logic := '1';
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variable tpw_CI_posedge : Time := 12 ns; -- ~40 MHz
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variable tpw_CI_posedge : Time := 12 ns; -- ~40 MHz
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begin
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begin
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Clk <= clktmp;
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Clk <= clktmp;
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clktmp := not clktmp;
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clktmp := not clktmp;
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wait for tpw_CI_posedge;
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wait for tpw_CI_posedge;
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end process;
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end process;
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end Behaviour; --=================== End of architecure =====================--
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end Behaviour; --=================== End of architecure =====================--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- LoopBack Device
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-- LoopBack Device
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE,work;
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library IEEE,work;
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use IEEE.Std_Logic_1164.all;
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use IEEE.Std_Logic_1164.all;
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--
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--
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entity LoopBack is
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entity LoopBack is
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port (
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port (
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Clk : in Std_Logic; -- Oscillator clock
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Clk : in Std_Logic; -- Oscillator clock
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RxWr : in Std_Logic; -- Rx line
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RxWr : in Std_Logic; -- Rx line
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TxWr : out Std_Logic); -- Tx line
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TxWr : out Std_Logic); -- Tx line
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end LoopBack; --==================== End of entity ==========================--
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end LoopBack; --==================== End of entity ==========================--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Architecture for clock and reset signals generator
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-- Architecture for clock and reset signals generator
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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architecture Behaviour of LoopBack is
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architecture Behaviour of LoopBack is
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begin --========================== Architecture ==============================--
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begin --========================== Architecture ==============================--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- Provide the external clock signal
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-- Provide the external clock signal
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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ClkTrig : process(Clk)
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ClkTrig : process(Clk)
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begin
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begin
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TxWr <= RxWr;
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TxWr <= RxWr;
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end process;
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end process;
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end Behaviour; --=================== End of architecure =====================--
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end Behaviour; --=================== End of architecure =====================--
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|
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Testbench for UART device
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-- Testbench for UART device
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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library work;
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library work;
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use work.Uart_Def.all;
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use work.Uart_Def.all;
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|
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entity UARTTEST is
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entity UARTTEST is
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end UARTTEST;
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end UARTTEST;
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architecture stimulus of UARTTEST is
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architecture stimulus of UARTTEST is
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Signals
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-- Signals
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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signal Reset : Std_Logic; -- Synchro signal
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signal Reset : Std_Logic; -- Synchro signal
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signal Clk : Std_Logic; -- Clock signal
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signal Clk : Std_Logic; -- Clock signal
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signal DataIn : Std_Logic_Vector(7 downto 0);
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signal DataIn : Std_Logic_Vector(7 downto 0);
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signal DataOut : Std_Logic_Vector(7 downto 0);
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signal DataOut : Std_Logic_Vector(7 downto 0);
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signal RxD : Std_Logic; -- RS-232 data input
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signal RxD : Std_Logic; -- RS-232 data input
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signal TxD : Std_Logic; -- RS-232 data output
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signal TxD : Std_Logic; -- RS-232 data output
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signal CS_N : Std_Logic;
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signal CS_N : Std_Logic;
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signal RD_N : Std_Logic;
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signal RD_N : Std_Logic;
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signal WR_N : Std_Logic;
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signal WR_N : Std_Logic;
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signal IntRx_N : Std_Logic; -- Receive interrupt
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signal IntRx_N : Std_Logic; -- Receive interrupt
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signal IntTx_N : Std_Logic; -- Transmit interrupt
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signal IntTx_N : Std_Logic; -- Transmit interrupt
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signal Addr : Std_Logic_Vector(1 downto 0); --
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signal Addr : Std_Logic_Vector(1 downto 0); --
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- Clock Divider
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-- Clock Divider
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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component ClkGen is
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component ClkGen is
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port (
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port (
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Clk : out Std_Logic); -- Oscillator clock
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Clk : out Std_Logic); -- Oscillator clock
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end component;
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end component;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- LoopBack Device
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-- LoopBack Device
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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component LoopBack is
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component LoopBack is
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port (
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port (
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Clk : in Std_Logic; -- Oscillator clock
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Clk : in Std_Logic; -- Oscillator clock
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RxWr : in Std_Logic; -- Rx line
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RxWr : in Std_Logic; -- Rx line
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TxWr : out Std_Logic); -- Tx line
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TxWr : out Std_Logic); -- Tx line
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end component;
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end component;
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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-- UART Device
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-- UART Device
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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component miniUART is
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component miniUART is
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port (
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port (
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SysClk : in Std_Logic; -- System Clock
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SysClk : in Std_Logic; -- System Clock
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Reset : in Std_Logic; -- Reset input
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Reset : in Std_Logic; -- Reset input
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CS_N : in Std_Logic;
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CS_N : in Std_Logic;
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RD_N : in Std_Logic;
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RD_N : in Std_Logic;
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WR_N : in Std_Logic;
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WR_N : in Std_Logic;
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RxD : in Std_Logic;
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RxD : in Std_Logic;
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TxD : out Std_Logic;
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TxD : out Std_Logic;
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IntRx_N : out Std_Logic; -- Receive interrupt
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IntRx_N : out Std_Logic; -- Receive interrupt
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IntTx_N : out Std_Logic; -- Transmit interrupt
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IntTx_N : out Std_Logic; -- Transmit interrupt
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Addr : in Std_Logic_Vector(1 downto 0); --
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Addr : in Std_Logic_Vector(1 downto 0); --
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DataIn : in Std_Logic_Vector(7 downto 0); --
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DataIn : in Std_Logic_Vector(7 downto 0); --
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DataOut : out Std_Logic_Vector(7 downto 0)); --
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DataOut : out Std_Logic_Vector(7 downto 0)); --
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end component;
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end component;
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begin --======================== Architecture ========================--
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begin --======================== Architecture ========================--
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Instantiation of components
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-- Instantiation of components
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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Clock : ClkGen port map (Clk);
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Clock : ClkGen port map (Clk);
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LoopDev : LoopBack port map (Clk,TxD,RxD);
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LoopDev : LoopBack port map (Clk,TxD,RxD);
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miniUARTDev : miniUART port map (Clk,Reset,CS_N,RD_N,WR_N,RxD,TxD,
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miniUARTDev : miniUART port map (Clk,Reset,CS_N,RD_N,WR_N,RxD,TxD,
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IntRx_N,IntTx_N,Addr,DataIn,DataOut);
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IntRx_N,IntTx_N,Addr,DataIn,DataOut);
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Reset cycle
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-- Reset cycle
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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RstCyc : process
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RstCyc : process
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begin
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begin
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Reset <= '1';
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Reset <= '1';
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wait for 5 ns;
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wait for 5 ns;
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Reset <= '0';
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Reset <= '0';
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wait for 250 ns;
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wait for 250 ns;
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Reset <= '1';
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Reset <= '1';
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wait;
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wait;
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end process;
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end process;
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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--
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--
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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ProcCyc : process(Clk,IntRx_N,IntTx_N,Reset)
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ProcCyc : process(Clk,IntRx_N,IntTx_N,Reset)
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variable counter : unsigned(3 downto 0);
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variable counter : unsigned(3 downto 0);
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constant cone : unsigned(3 downto 0):= "0001";
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constant cone : unsigned(3 downto 0):= "0001";
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variable temp : bit := '0';
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variable temp : bit := '0';
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begin
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begin
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if Rising_Edge(Reset) then
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if Rising_Edge(Reset) then
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counter := "0000";
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counter := "0000";
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WR_N <= '1';
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WR_N <= '1';
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RD_N <= '1';
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RD_N <= '1';
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CS_N <= '1';
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CS_N <= '1';
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elsif Rising_Edge(Clk) then
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elsif Rising_Edge(Clk) then
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if IntTx_N = '0' then
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if IntTx_N = '0' then
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if temp = '0' then
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if temp = '0' then
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temp := '1';
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temp := '1';
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case counter is
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case counter is
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when "0000" =>
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when "0000" =>
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Addr <= "00";
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Addr <= "00";
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DataIn <= x"AA";
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DataIn <= x"AA";
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WR_N <= '0';
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WR_N <= '0';
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CS_N <= '0';
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CS_N <= '0';
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counter := counter + cone;
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counter := counter + cone;
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when "0001" =>
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when "0001" =>
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Addr <= "00";
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Addr <= "00";
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DataIn <= x"AF";
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DataIn <= x"AF";
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WR_N <= '0';
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WR_N <= '0';
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CS_N <= '0';
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CS_N <= '0';
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counter := counter + cone;
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counter := counter + cone;
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when "0010" =>
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when "0010" =>
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Addr <= "00";
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Addr <= "00";
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DataIn <= x"55";
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DataIn <= x"55";
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WR_N <= '0';
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WR_N <= '0';
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CS_N <= '0';
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CS_N <= '0';
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counter := counter + cone;
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counter := counter + cone;
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when "0011" =>
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when "0011" =>
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Addr <= "00";
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Addr <= "00";
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DataIn <= x"E8";
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DataIn <= x"E8";
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WR_N <= '0';
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WR_N <= '0';
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CS_N <= '0';
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CS_N <= '0';
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counter := "0000";
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counter := "0000";
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when others => null;
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when others => null;
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end case;
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end case;
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elsif temp = '1' then
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elsif temp = '1' then
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temp := '0';
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temp := '0';
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end if;
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end if;
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elsif IntRx_N = '0' then
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elsif IntRx_N = '0' then
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Addr <= "00";
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Addr <= "00";
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RD_N <= '0';
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RD_N <= '0';
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CS_N <= '0';
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CS_N <= '0';
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else
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else
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RD_N <= '1';
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RD_N <= '1';
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CS_N <= '1';
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CS_N <= '1';
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WR_N <= '1';
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WR_N <= '1';
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DataIn <= "ZZZZZZZZ";
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DataIn <= "ZZZZZZZZ";
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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|
|
