// UART Wishbone-compatible core top level
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// UART Wishbone-compatible core top level
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//
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//
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
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// Company: Flextronics Semiconductor
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// Company: Flextronics Semiconductor
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//
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//
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// Releases:
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// Releases:
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// 1.1 First release
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// 1.1 First release
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "UART_defines.v"
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`include "UART_defines.v"
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module UART_top (
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module UART_top (
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clk,
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clk,
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// Wishbone signals
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// Wishbone signals
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wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
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int_o, // interrupt request
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int_o, // interrupt request
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// UART signals
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// UART signals
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// serial input/output
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// serial input/output
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stx_o, srx_i,
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stx_o, srx_i,
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// modem signals
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// modem signals
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rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i
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rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i
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);
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);
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input clk;
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input clk;
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// WISHBONE interface
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// WISHBONE interface
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input wb_rst_i;
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input wb_rst_i;
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input [`ADDR_WIDTH-1:0] wb_addr_i;
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input [`ADDR_WIDTH-1:0] wb_addr_i;
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input [7:0] wb_dat_i;
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input [7:0] wb_dat_i;
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output [7:0] wb_dat_o;
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output [7:0] wb_dat_o;
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input wb_we_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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output wb_ack_o;
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output wb_ack_o;
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output int_o;
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output int_o;
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// UART signals
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// UART signals
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input srx_i;
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input srx_i;
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output stx_o;
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output stx_o;
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output rts_o;
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output rts_o;
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input cts_i;
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input cts_i;
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output dtr_o;
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output dtr_o;
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input dsr_i;
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input dsr_i;
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input ri_i;
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input ri_i;
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input dcd_i;
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input dcd_i;
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wire stx_o;
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wire stx_o;
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wire rts_o;
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wire rts_o;
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wire dtr_o;
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wire dtr_o;
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wire [`ADDR_WIDTH-1:0] wb_addr_i;
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wire [`ADDR_WIDTH-1:0] wb_addr_i;
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wire [7:0] wb_dat_i;
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wire [7:0] wb_dat_i;
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wire [7:0] wb_dat_o;
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wire [7:0] wb_dat_o;
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wire we_o; // Write enable for registers
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wire we_o; // Write enable for registers
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wire [3:0] ier;
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wire [3:0] ier;
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wire [7:0] iir;
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wire [7:0] iir;
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wire [3:0] fcr; /// bits 7,6,2,1 of fcr. Other bits are ignored
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wire [3:0] fcr; /// bits 7,6,2,1 of fcr. Other bits are ignored
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wire [4:0] mcr;
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wire [4:0] mcr;
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wire [7:0] lcr;
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wire [7:0] lcr;
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wire [7:0] lsr;
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wire [7:0] lsr;
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wire [7:0] msr;
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wire [7:0] msr;
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wire [31:0] dl; // 32-bit divisor latch
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wire [31:0] dl; // 32-bit divisor latch
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wire enable;
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wire enable;
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//
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//
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// MODULE INSTANCES
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// MODULE INSTANCES
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//
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//
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//// WISHBONE interface module
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//// WISHBONE interface module
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UART_wb wb_interface(
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UART_wb wb_interface(
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.clk( clk ),
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.wb_rst_i( wb_rst_i ),
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// .wb_dat_i( wb_dat_i ),
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// .wb_dat_i( wb_dat_i ),
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// .wb_dat_o( wb_dat_o ),
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// .wb_dat_o( wb_dat_o ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_ack_o( wb_ack_o ),
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.wb_ack_o( wb_ack_o ),
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// .int_o( int_o ),
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// .int_o( int_o ),
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.we_o( we_o )
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.we_o( we_o )
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);
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);
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// Registers
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// Registers
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UART_regs regs(
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UART_regs regs(
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.clk( clk ),
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.clk( clk ),
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.wb_rst_i( wb_rst_i ),
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.wb_rst_i( wb_rst_i ),
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.wb_addr_i( wb_addr_i ),
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.wb_addr_i( wb_addr_i ),
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.wb_dat_i( wb_dat_i ),
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.wb_dat_i( wb_dat_i ),
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.wb_dat_o( wb_dat_o ),
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.wb_dat_o( wb_dat_o ),
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.wb_we_i( we_o ),
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.wb_we_i( we_o ),
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.ier( ier ),
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.ier( ier ),
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.iir( iir ),
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.iir( iir ),
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.fcr( fcr ),
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.fcr( fcr ),
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.mcr( mcr ),
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.mcr( mcr ),
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.lcr( lcr ),
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.lcr( lcr ),
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.lsr( lsr ),
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.lsr( lsr ),
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.msr( msr ),
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.msr( msr ),
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.dl( dl ),
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.dl( dl ),
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.modem_inputs( {cts_i, dsr_i,
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.modem_inputs( {cts_i, dsr_i,
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ri_i, dcd_i} ),
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ri_i, dcd_i} ),
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.stx_o( stx_o ),
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.stx_o( stx_o ),
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.srx_i( srx_i ),
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.srx_i( srx_i ),
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.enable( enable ),
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.enable( enable ),
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.rts_o( rts_o ),
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.rts_o( rts_o ),
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.dtr_o( dtr_o )
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.dtr_o( dtr_o )
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);
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);
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endmodule
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endmodule
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