-- UART transactor
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-- UART transactor
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 03.02.2008
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-- Date: 03.02.2008
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-- Version: 1.0
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-- Version: 1.0
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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use work.uart_package.all;
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use work.uart_package.all;
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use work.txt_util.all;
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use work.txt_util.all;
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entity uart_transactor is
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entity uart_transactor is
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generic (
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generic (
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stim_file : string := "uart_stim.dat"; -- Stimulus input file
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stim_file : string := "sim/uart_stim.dat"; -- Stimulus input file
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log_file : string := "uart_log.txt" -- Log file
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log_file : string := "sim/uart_log.txt" -- Log file
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);
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);
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end uart_transactor;
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end uart_transactor;
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architecture tb of uart_transactor is
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architecture tb of uart_transactor is
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file stimulus : TEXT open read_mode is stim_file; -- Open stimulus file for read
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file stimulus : TEXT open read_mode is stim_file; -- Open stimulus file for read
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file log : TEXT open write_mode is log_file; -- Open log file for write
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file log : TEXT open write_mode is log_file; -- Open log file for write
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-- The DUT
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-- The DUT
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component uart_16750 is
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component uart_16750 is
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port (
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port (
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CLK : in std_logic; -- Clock
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RST : in std_logic; -- Reset
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BAUDCE : in std_logic; -- Baudrate generator clock enable
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BAUDCE : in std_logic; -- Baudrate generator clock enable
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CS : in std_logic; -- Chip select
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CS : in std_logic; -- Chip select
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WR : in std_logic; -- Write to UART
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WR : in std_logic; -- Write to UART
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RD : in std_logic; -- Read from UART
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RD : in std_logic; -- Read from UART
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A : in std_logic_vector(2 downto 0); -- Register select
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A : in std_logic_vector(2 downto 0); -- Register select
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DIN : in std_logic_vector(7 downto 0); -- Data bus input
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DIN : in std_logic_vector(7 downto 0); -- Data bus input
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DOUT : out std_logic_vector(7 downto 0); -- Data bus output
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DOUT : out std_logic_vector(7 downto 0); -- Data bus output
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DDIS : out std_logic; -- Driver disable
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DDIS : out std_logic; -- Driver disable
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INT : out std_logic; -- Interrupt output
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INT : out std_logic; -- Interrupt output
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OUT1N : out std_logic; -- Output 1
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OUT1N : out std_logic; -- Output 1
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OUT2N : out std_logic; -- Output 2
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OUT2N : out std_logic; -- Output 2
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RCLK : in std_logic; -- Receiver clock (16x baudrate)
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RCLK : in std_logic; -- Receiver clock (16x baudrate)
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BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
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BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate)
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RTSN : out std_logic; -- RTS output
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RTSN : out std_logic; -- RTS output
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DTRN : out std_logic; -- DTR output
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DTRN : out std_logic; -- DTR output
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CTSN : in std_logic; -- CTS input
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CTSN : in std_logic; -- CTS input
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DSRN : in std_logic; -- DSR input
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DSRN : in std_logic; -- DSR input
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DCDN : in std_logic; -- DCD input
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DCDN : in std_logic; -- DCD input
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RIN : in std_logic; -- RI input
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RIN : in std_logic; -- RI input
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SIN : in std_logic; -- Receiver input
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SIN : in std_logic; -- Receiver input
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SOUT : out std_logic -- Transmitter output
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SOUT : out std_logic -- Transmitter output
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);
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);
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end component;
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end component;
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component slib_clock_div is
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component slib_clock_div is
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generic (
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generic (
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RATIO : integer := 18 -- Clock divider ratio
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RATIO : integer := 18 -- Clock divider ratio
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);
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);
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port (
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port (
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CLK : in std_logic; -- Clock
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RST : in std_logic; -- Reset
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CE : in std_logic; -- Clock enable input
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CE : in std_logic; -- Clock enable input
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Q : out std_logic -- New clock enable output
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Q : out std_logic -- New clock enable output
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);
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);
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end component;
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end component;
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-- DUT signals
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-- DUT signals
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signal clk, rst : std_logic;
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signal clk, rst : std_logic;
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signal uart_if : uart_interface;
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signal uart_if : uart_interface;
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signal dout : std_logic_vector (7 downto 0);
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signal dout : std_logic_vector (7 downto 0);
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signal ddis, int : std_logic;
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signal ddis, int : std_logic;
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signal baudce, rclk, baudoutn : std_logic;
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signal baudce, rclk, baudoutn : std_logic;
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signal out1n, out2n, rtsn, dtrn, ctsn, dsrn, dcdn, rin, sin, sout : std_logic;
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signal out1n, out2n, rtsn, dtrn, ctsn, dsrn, dcdn, rin, sin, sout : std_logic;
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constant cycle : time := 30 ns;
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constant cycle : time := 30 ns;
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begin
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begin
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-- Main clock
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-- Main clock
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CLOCK: process
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CLOCK: process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for cycle/2;
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wait for cycle/2;
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clk <= '1';
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clk <= '1';
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wait for cycle/2;
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wait for cycle/2;
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end process;
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end process;
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-- Baudrate generator clock enable
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-- Baudrate generator clock enable
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BGCE: slib_clock_div generic map (RATIO => 18) port map (clk, rst, '1', baudce);
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BGCE: slib_clock_div generic map (RATIO => 18) port map (clk, rst, '1', baudce);
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rclk <= baudoutn;
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rclk <= baudoutn;
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-- Pull-up
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-- Pull-up
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--uart_if.data <= (others => 'H');
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--uart_if.data <= (others => 'H');
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-- UART interface bus tri-state buffer
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-- UART interface bus tri-state buffer
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LPCBUF: process (ddis, dout)
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LPCBUF: process (ddis, dout)
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begin
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begin
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if (ddis = '0') then
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if (ddis = '0') then
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uart_if.data <= dout;
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uart_if.data <= dout;
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else
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else
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uart_if.data <= (others => 'Z');
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uart_if.data <= (others => 'Z');
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end if;
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end if;
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end process;
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end process;
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DUT: uart_16750 port map ( CLK => CLK,
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DUT: uart_16750 port map ( CLK => CLK,
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RST => RST,
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RST => RST,
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BAUDCE => BAUDCE,
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BAUDCE => BAUDCE,
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CS => uart_if.cs,
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CS => uart_if.cs,
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WR => uart_if.wr,
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WR => uart_if.wr,
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RD => uart_if.rd,
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RD => uart_if.rd,
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A => uart_if.a,
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A => uart_if.a,
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DIN => uart_if.data,
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DIN => uart_if.data,
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DOUT => dout,
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DOUT => dout,
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DDIS => ddis,
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DDIS => ddis,
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INT => int,
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INT => int,
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OUT1N => out1n,
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OUT1N => out1n,
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OUT2N => out2n,
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OUT2N => out2n,
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RCLK => rclk,
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RCLK => rclk,
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BAUDOUTN=> baudoutn,
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BAUDOUTN=> baudoutn,
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RTSN => rtsn,
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RTSN => rtsn,
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DTRN => dtrn,
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DTRN => dtrn,
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CTSN => ctsn,
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CTSN => ctsn,
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DSRN => dsrn,
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DSRN => dsrn,
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DCDN => dcdn,
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DCDN => dcdn,
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RIN => rin,
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RIN => rin,
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SIN => sin,
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SIN => sin,
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SOUT => sout
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SOUT => sout
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);
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);
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-- Main transaction process
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-- Main transaction process
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TRANPROC: process
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TRANPROC: process
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variable s : string(1 to 100);
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variable s : string(1 to 100);
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variable address : std_logic_vector(2 downto 0);
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variable address : std_logic_vector(2 downto 0);
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variable data : std_logic_vector(7 downto 0);
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variable data : std_logic_vector(7 downto 0);
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variable data2 : std_logic_vector(7 downto 0);
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variable data2 : std_logic_vector(7 downto 0);
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begin
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begin
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-- Default values
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-- Default values
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rst <= '1';
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rst <= '1';
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ctsn <= '1';
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ctsn <= '1';
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dsrn <= '1';
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dsrn <= '1';
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dcdn <= '1';
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dcdn <= '1';
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rin <= '1';
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rin <= '1';
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sin <= '1';
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sin <= '1';
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uart_if.a <= (others => '0');
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uart_if.a <= (others => '0');
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uart_if.data <= (others => 'Z');
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uart_if.data <= (others => 'Z');
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uart_if.cs <= '0';
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uart_if.cs <= '0';
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uart_if.rd <= '0';
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uart_if.rd <= '0';
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uart_if.wr <= '0';
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uart_if.wr <= '0';
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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-- Get commands from stimulus file
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-- Get commands from stimulus file
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while not endfile(stimulus) loop
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while not endfile(stimulus) loop
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str_read(stimulus, s); -- Read line into string
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str_read(stimulus, s); -- Read line into string
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if (s(1 to 4) = "#SET") then -- Set values
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if (s(1 to 4) = "#SET") then -- Set values
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-- Format: RSTN CTSN DSRN DCDN RIN
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-- Format: RSTN CTSN DSRN DCDN RIN
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rst <= to_std_logic(s(6));
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rst <= to_std_logic(s(6));
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--CTSN <= to_std_logic(s(8));
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--CTSN <= to_std_logic(s(8));
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--DSRN <= to_std_logic(s(10));
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--DSRN <= to_std_logic(s(10));
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--DCDN <= to_std_logic(s(12));
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--DCDN <= to_std_logic(s(12));
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--RIN <= to_std_logic(s(14));
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--RIN <= to_std_logic(s(14));
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elsif (s(1 to 5) = "#WAIT") then -- Wait n cycles
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elsif (s(1 to 5) = "#WAIT") then -- Wait n cycles
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wait for integer'value(s(7 to 12))*cycle;
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wait for integer'value(s(7 to 12))*cycle;
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elsif (s(1 to 3) = "#RD") then -- Read from UART and compare
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elsif (s(1 to 3) = "#RD") then -- Read from UART and compare
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address := to_std_logic_vector(s(5 to 7));
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address := to_std_logic_vector(s(5 to 7));
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data := to_std_logic_vector(s(9 to 16));
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data := to_std_logic_vector(s(9 to 16));
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uart_read (uart_if, address, data2, log);
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uart_read (uart_if, address, data2, log);
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if (not compare(data, data2)) then
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if (not compare(data, data2)) then
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print (log, time'image(now) & ": " & "Failed: Expected 0x" & hstr(data) & " got 0x" & hstr(data2));
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print (log, time'image(now) & ": " & "Failed: Expected 0x" & hstr(data) & " got 0x" & hstr(data2));
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end if;
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end if;
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elsif (s(1 to 3) = "#WR") then -- Write to LPC
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elsif (s(1 to 3) = "#WR") then -- Write to LPC
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address := to_std_logic_vector(s(5 to 7));
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address := to_std_logic_vector(s(5 to 7));
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data := to_std_logic_vector(s(9 to 16));
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data := to_std_logic_vector(s(9 to 16));
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uart_write (uart_if, address, data, log);
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uart_write (uart_if, address, data, log);
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elsif (s(1 to 4) = "#LOG") then -- Write message to log
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elsif (s(1 to 4) = "#LOG") then -- Write message to log
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print (log, time'image(now) & ": " & s(6 to 80));
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print (log, time'image(now) & ": " & s(6 to 80));
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elsif (s(1 to 4) = "#CUO") then -- Check UART outputs INT OUT1N OUT2N RTSN DTRN
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elsif (s(1 to 4) = "#CUO") then -- Check UART outputs INT OUT1N OUT2N RTSN DTRN
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data2(4 downto 0) := to_std_logic_vector(s(6 to 10));
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data2(4 downto 0) := to_std_logic_vector(s(6 to 10));
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data(4 downto 0) := INT & OUT1N & OUT2N & RTSN & DTRN;
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data(4 downto 0) := INT & OUT1N & OUT2N & RTSN & DTRN;
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if (not compare(data(3 downto 0), data2(3 downto 0))) then
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if (not compare(data(3 downto 0), data2(3 downto 0))) then
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print (log, time'image(now) & ": " & "UART outputs failed: Expected " &
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print (log, time'image(now) & ": " & "UART outputs failed: Expected " &
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str(data2(4 downto 0)) & " got " & str(data(4 downto 0)));
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str(data2(4 downto 0)) & " got " & str(data(4 downto 0)));
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else
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else
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print (log, time'image(now) & ": " & "UART outputs: " & str(data(4 downto 0)));
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print (log, time'image(now) & ": " & "UART outputs: " & str(data(4 downto 0)));
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end if;
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end if;
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elsif (s(1 to 4) = "#EUS") then -- Send serial data from external UART to DUT
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uart_send (SOUT, 8.68 us, integer'value (s(6 to 7)), integer'value (s(9 to 11)), log);
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--uart_send (SOUT, 3.33 ms, 8, integer'value (s(8 to 10)), log);
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else
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else
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print ("Unknown command: " & s);
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print ("Unknown command: " & s);
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end if;
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end if;
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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end tb;
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end tb;
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