--
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--
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-- UART receiver
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-- UART receiver
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--
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--
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-- Author: Sebastian Witt
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-- Author: Sebastian Witt
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-- Date: 27.01.2008
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-- Date: 27.01.2008
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-- Version: 1.1
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-- Version: 1.1
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU Lesser General Public
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the
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-- License along with this library; if not, write to the
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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-- Boston, MA 02111-1307 USA
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-- Boston, MA 02111-1307 USA
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--
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--
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.all;
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USE IEEE.std_logic_1164.all;
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USE IEEE.numeric_std.all;
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USE IEEE.numeric_std.all;
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-- Serial UART receiver
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-- Serial UART receiver
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entity uart_receiver is
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entity uart_receiver is
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port (
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port (
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CLK : in std_logic; -- Clock
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RST : in std_logic; -- Reset
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RXCLK : in std_logic; -- Receiver clock (16x baudrate)
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RXCLK : in std_logic; -- Receiver clock (16x baudrate)
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RXCLEAR : in std_logic; -- Reset receiver state
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RXCLEAR : in std_logic; -- Reset receiver state
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WLS : in std_logic_vector(1 downto 0); -- Word length select
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WLS : in std_logic_vector(1 downto 0); -- Word length select
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STB : in std_logic; -- Number of stop bits
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STB : in std_logic; -- Number of stop bits
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PEN : in std_logic; -- Parity enable
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PEN : in std_logic; -- Parity enable
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EPS : in std_logic; -- Even parity select
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EPS : in std_logic; -- Even parity select
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SP : in std_logic; -- Stick parity
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SP : in std_logic; -- Stick parity
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SIN : in std_logic; -- Receiver input
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SIN : in std_logic; -- Receiver input
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PE : out std_logic; -- Parity error
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PE : out std_logic; -- Parity error
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FE : out std_logic; -- Framing error
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FE : out std_logic; -- Framing error
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BI : out std_logic; -- Break interrupt
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BI : out std_logic; -- Break interrupt
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DOUT : out std_logic_vector(7 downto 0); -- Output data
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DOUT : out std_logic_vector(7 downto 0); -- Output data
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RXFINISHED : out std_logic -- Receiver operation finished
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RXFINISHED : out std_logic -- Receiver operation finished
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);
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);
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end uart_receiver;
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end uart_receiver;
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architecture rtl of uart_receiver is
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architecture rtl of uart_receiver is
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-- Majority voting logic
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-- Majority voting logic
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component slib_mv_filter is
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component slib_mv_filter is
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generic (
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generic (
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WIDTH : natural := 4;
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WIDTH : natural := 4;
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THRESHOLD : natural := 10
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THRESHOLD : natural := 10
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);
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);
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port (
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port (
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CLK : in std_logic; -- Clock
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RST : in std_logic; -- Reset
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SAMPLE : in std_logic; -- Clock enable for sample process
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SAMPLE : in std_logic; -- Clock enable for sample process
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CLEAR : in std_logic; -- Reset process
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CLEAR : in std_logic; -- Reset process
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D : in std_logic; -- Signal input
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D : in std_logic; -- Signal input
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Q : out std_logic -- Signal D was at least THRESHOLD samples high
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Q : out std_logic -- Signal D was at least THRESHOLD samples high
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);
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);
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end component;
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end component;
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-- Counter
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-- Counter
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component slib_counter is
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component slib_counter is
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generic (
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generic (
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WIDTH : natural := 4 -- Counter width
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WIDTH : natural := 4 -- Counter width
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);
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);
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port (
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port (
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CLK : in std_logic; -- Clock
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CLK : in std_logic; -- Clock
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RST : in std_logic; -- Reset
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RST : in std_logic; -- Reset
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CLEAR : in std_logic; -- Clear counter register
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CLEAR : in std_logic; -- Clear counter register
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LOAD : in std_logic; -- Load counter register
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LOAD : in std_logic; -- Load counter register
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ENABLE : in std_logic; -- Enable count operation
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ENABLE : in std_logic; -- Enable count operation
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DOWN : in std_logic; -- Count direction down
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DOWN : in std_logic; -- Count direction down
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D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
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D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
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Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
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Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
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OVERFLOW : out std_logic -- Counter overflow
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OVERFLOW : out std_logic -- Counter overflow
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);
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);
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end component;
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end component;
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-- FSM
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-- FSM
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type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
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type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
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signal CState, NState : state_type;
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signal CState, NState : state_type;
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-- Signals
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-- Signals
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signal iBaudCountClear : std_logic; -- Baud counter clear
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signal iBaudCountClear : std_logic; -- Baud counter clear
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signal iBaudStep : std_logic; -- Next symbol pulse
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signal iBaudStep : std_logic; -- Next symbol pulse
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signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
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signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
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signal iFilterClear : std_logic; -- Reset input filter
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signal iFilterClear : std_logic; -- Reset input filter
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signal iFSIN : std_logic; -- Filtered SIN
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signal iFSIN : std_logic; -- Filtered SIN
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signal iParity : std_logic; -- Data parity
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signal iParity : std_logic; -- Data parity
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signal iParityReceived : std_logic; -- Parity received
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signal iParityReceived : std_logic; -- Parity received
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signal iDataCount : integer range 0 to 8; -- Data bit counter
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signal iDataCount : integer range 0 to 8; -- Data bit counter
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signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
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signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
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signal iDataCountFinish : std_logic; -- Data bit counter finished
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signal iDataCountFinish : std_logic; -- Data bit counter finished
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signal iRXFinished : std_logic; -- Word received, output data valid
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signal iRXFinished : std_logic; -- Word received, output data valid
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signal iFE : std_logic; -- Internal frame error
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signal iFE : std_logic; -- Internal frame error
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signal iBI : std_logic; -- Internal break interrupt
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signal iBI : std_logic; -- Internal break interrupt
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signal iNoStopReceived : std_logic; -- No valid stop bit received
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signal iNoStopReceived : std_logic; -- No valid stop bit received
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signal iDOUT : std_logic_vector(7 downto 0); -- Data output
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signal iDOUT : std_logic_vector(7 downto 0); -- Data output
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begin
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begin
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-- Baudrate counter: RXCLK/16
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-- Baudrate counter: RXCLK/16
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RX_BRC: slib_counter generic map (
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RX_BRC: slib_counter generic map (
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WIDTH => 4
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WIDTH => 4
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) port map (
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) port map (
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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CLEAR => iBaudCountClear,
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CLEAR => iBaudCountClear,
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LOAD => '0',
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LOAD => '0',
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ENABLE => RXCLK,
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ENABLE => RXCLK,
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DOWN => '0',
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DOWN => '0',
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D => x"0",
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D => x"0",
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OVERFLOW => iBaudStep
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OVERFLOW => iBaudStep
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);
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);
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-- Input filter
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-- Input filter
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RX_MVF: slib_mv_filter generic map (
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RX_MVF: slib_mv_filter generic map (
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WIDTH => 4,
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WIDTH => 4,
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THRESHOLD => 10
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THRESHOLD => 10
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) port map (
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) port map (
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CLK => CLK,
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CLK => CLK,
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RST => RST,
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RST => RST,
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SAMPLE => RXCLK,
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SAMPLE => RXCLK,
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CLEAR => iFilterClear,
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CLEAR => iFilterClear,
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D => SIN,
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D => SIN,
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Q => iFSIN
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Q => iFSIN
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);
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);
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-- iBaudStepD
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-- iBaudStepD
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RX_IFC: process (CLK, RST)
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RX_IFC: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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iBaudStepD <= '0';
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iBaudStepD <= '0';
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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iBaudStepD <= iBaudStep;
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iBaudStepD <= iBaudStep;
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end if;
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end if;
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end process;
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end process;
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iFilterClear <= iBaudStepD or iBaudCountClear;
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iFilterClear <= iBaudStepD or iBaudCountClear;
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-- Parity generation
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-- Parity generation
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RX_PAR: process (iDOUT, EPS)
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RX_PAR: process (iDOUT, EPS)
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begin
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begin
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iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
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iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
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end process;
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end process;
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-- Data bit capture
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-- Data bit capture
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RX_DATACOUNT: process (CLK, RST)
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RX_DATACOUNT: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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iDataCount <= 0;
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iDataCount <= 0;
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iDOUT <= (others => '0');
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iDOUT <= (others => '0');
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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if (iDataCountInit = '1') then
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if (iDataCountInit = '1') then
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iDataCount <= 0;
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iDataCount <= 0;
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iDOUT <= (others => '0');
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iDOUT <= (others => '0');
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else
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else
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if (iBaudStep = '1' and iDataCountFinish = '0') then
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if (iBaudStep = '1' and iDataCountFinish = '0') then
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iDOUT(iDataCount) <= iFSIN;
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iDOUT(iDataCount) <= iFSIN;
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iDataCount <= iDataCount + 1;
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iDataCount <= iDataCount + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
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iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
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(WLS = "01" and iDataCount = 6) or
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(WLS = "01" and iDataCount = 6) or
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(WLS = "10" and iDataCount = 7) or
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(WLS = "10" and iDataCount = 7) or
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(WLS = "11" and iDataCount = 8) else '0';
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(WLS = "11" and iDataCount = 8) else '0';
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-- FSM update process
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-- FSM update process
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RX_FSMUPDATE: process (CLK, RST)
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RX_FSMUPDATE: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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CState <= IDLE;
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CState <= IDLE;
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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CState <= NState;
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CState <= NState;
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end if;
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end if;
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end process;
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end process;
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-- RX FSM
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-- RX FSM
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RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
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RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
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begin
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begin
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-- Defaults
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-- Defaults
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NState <= IDLE;
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NState <= IDLE;
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iBaudCountClear <= '0';
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iBaudCountClear <= '0';
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iDataCountInit <= '0';
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iDataCountInit <= '0';
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iRXFinished <= '0';
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iRXFinished <= '0';
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case CState is
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case CState is
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when IDLE => if (SIN = '0') then -- Start detected
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when IDLE => if (SIN = '0') then -- Start detected
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NState <= START;
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NState <= START;
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end if;
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end if;
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iBaudCountClear <= '1';
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iBaudCountClear <= '1';
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iDataCountInit <= '1';
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iDataCountInit <= '1';
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when START => iDataCountInit <= '1';
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when START => iDataCountInit <= '1';
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if (iBaudStep = '1') then -- Wait for start bit end
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if (iBaudStep = '1') then -- Wait for start bit end
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if (iFSIN = '0') then
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if (iFSIN = '0') then
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NState <= DATA;
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NState <= DATA;
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end if;
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end if;
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else
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else
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NState <= START;
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NState <= START;
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end if;
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end if;
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when DATA => if (iDataCountFinish = '1') then -- Received all data bits
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when DATA => if (iDataCountFinish = '1') then -- Received all data bits
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if (PEN = '1') then
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if (PEN = '1') then
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NState <= PAR; -- Parity enabled
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NState <= PAR; -- Parity enabled
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else
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else
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NState <= STOP; -- No parity
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NState <= STOP; -- No parity
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end if;
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end if;
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else
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else
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NState <= DATA;
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NState <= DATA;
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end if;
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end if;
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when PAR => if (iBaudStep = '1') then -- Wait for parity bit
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when PAR => if (iBaudStep = '1') then -- Wait for parity bit
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NState <= STOP;
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NState <= STOP;
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else
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else
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NState <= PAR;
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NState <= PAR;
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end if;
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end if;
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when STOP => if (iBaudStep = '1') then -- Wait for stop bit
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when STOP => if (iBaudStep = '1') then -- Wait for stop bit
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if (iFSIN = '0') then -- No stop bit received
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if (iFSIN = '0') then -- No stop bit received
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iRXFinished <= '1';
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iRXFinished <= '1';
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NState <= MWAIT;
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NState <= MWAIT;
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else
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else
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iRXFinished <= '1';
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iRXFinished <= '1';
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NState <= IDLE; -- Stop bit end
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NState <= IDLE; -- Stop bit end
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end if;
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end if;
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else
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else
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NState <= STOP;
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NState <= STOP;
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end if;
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end if;
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when MWAIT => if (SIN = '0') then -- Wait for mark
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when MWAIT => if (SIN = '0') then -- Wait for mark
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NState <= MWAIT;
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NState <= MWAIT;
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end if;
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end if;
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when others => null;
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when others => null;
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end case;
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end case;
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end process;
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end process;
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-- Check parity
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-- Check parity
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RX_PARCHECK: process (CLK, RST)
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RX_PARCHECK: process (CLK, RST)
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begin
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begin
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if (RST = '1') then
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if (RST = '1') then
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PE <= '0';
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PE <= '0';
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iParityReceived <= '0';
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iParityReceived <= '0';
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elsif (CLK'event and CLK = '1') then
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elsif (CLK'event and CLK = '1') then
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if (CState = PAR and iBaudStep = '1') then
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if (CState = PAR and iBaudStep = '1') then
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iParityReceived <= iFSIN; -- Received parity bit
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iParityReceived <= iFSIN; -- Received parity bit
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end if;
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end if;
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-- Check parity
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-- Check parity
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if (PEN = '1') then -- Parity enabled
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if (PEN = '1') then -- Parity enabled
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PE <= '0';
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PE <= '0';
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if (SP = '1') then -- Sticky parity
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if (SP = '1') then -- Sticky parity
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if ((EPS xor iParityReceived) = '0') then
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if ((EPS xor iParityReceived) = '0') then
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PE <= '1'; -- Parity error
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PE <= '1'; -- Parity error
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end if;
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end if;
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else
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else
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if (iParity /= iParityReceived) then
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if (iParity /= iParityReceived) then
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PE <= '1'; -- Parity error
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PE <= '1'; -- Parity error
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end if;
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end if;
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end if;
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end if;
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else
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else
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PE <= '0'; -- Parity disabled
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PE <= '0'; -- Parity disabled
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iParityReceived <= '0';
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iParityReceived <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Framing error and break interrupt
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-- Framing error and break interrupt
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iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
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iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
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iBI <= '1' when iDOUT = "00000000" and
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iBI <= '1' when iDOUT = "00000000" and
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iParityReceived = '0' and
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iParityReceived = '0' and
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iNoStopReceived = '1' else '0';
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iNoStopReceived = '1' else '0';
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iFE <= '1' when iNoStopReceived = '1' else '0';
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iFE <= '1' when iNoStopReceived = '1' else '0';
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-- Output signals
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-- Output signals
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DOUT <= iDOUT;
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DOUT <= iDOUT;
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BI <= iBI;
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BI <= iBI;
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FE <= iFE;
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FE <= iFE;
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RXFINISHED <= iRXFinished;
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RXFINISHED <= iRXFinished;
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end rtl;
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end rtl;
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