#!/usr/bin/perl
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#!/usr/bin/perl
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use strict;
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use strict;
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# Create stimulus/test file for 16550/16750 compatible UART cores
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# Create stimulus/test file for 16550/16750 compatible UART cores
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#
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#
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# Author: Sebastian Witt
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# Author: Sebastian Witt
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# Date: 06.02.2008
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# Date: 06.02.2008
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# Version: 1.4
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# Version: 1.4
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# License: GPL
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# License: GPL
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#
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#
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# History: 1.0 - Initial version
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# History: 1.0 - Initial version
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# 1.1 - Update
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# 1.1 - Update
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# 1.2 - FIFO test update
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# 1.2 - FIFO test update
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# 1.3 - Automatic flow control tests
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# 1.3 - Automatic flow control tests
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# 1.4 - FIFO 64 tests
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# 1.4 - FIFO 64 tests
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#
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#
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#
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#
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# Global control settings
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# Global control settings
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#
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#
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use constant CYCLE => 30e-9; # Cycle time
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use constant CYCLE => 30e-9; # Cycle time
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#use constant CYCLE => 1e-9; # Cycle time
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#use constant CYCLE => 1e-9; # Cycle time
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use constant LOCAL_LOOP => 1; # Use UART local loopback
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use constant LOCAL_LOOP => 1; # Use UART local loopback
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use constant INITREGS => 1; # Initialize registers
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use constant INITREGS => 1; # Initialize registers
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use constant TEST_CONTROL => 1; # Test control lines
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use constant TEST_CONTROL => 1; # Test control lines
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use constant TEST_INTERRUPT => 1; # Test interrupts
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use constant TEST_INTERRUPT => 1; # Test interrupts
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use constant TEST_DEFAULT => 1; # Test standard modes
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use constant TEST_DEFAULT => 1; # Test standard modes
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use constant TEST_FIFO => 1; # Test 64 byte FIFO mode
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use constant TEST_FIFO => 1; # Test 64 byte FIFO mode
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use constant TEST_FIFO64 => 1; # Test 64 byte FIFO mode
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use constant TEST_FIFO64 => 1; # Test 64 byte FIFO mode
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use constant TEST_AFC => 1; # Test automatic flow control
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use constant TEST_AFC => 1; # Test automatic flow control
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use constant UART_ADDRESS => 0x3f8; # UART base address
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use constant UART_ADDRESS => 0x3f8; # UART base address
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# Prototypes
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# Prototypes
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sub logmessage($); # Message
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sub logmessage($); # Message
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sub uart_write($$); # Address, Data
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sub uart_write($$); # Address, Data
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sub uart_read($$); # Address, Expected data
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sub uart_read($$); # Address, Expected data
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sub uart_setbaudrate($); # Baudrate
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sub uart_setbaudrate($); # Baudrate
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##################################################################
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##################################################################
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# Main process
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# Main process
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##################################################################
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##################################################################
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# Register addresses
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# Register addresses
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use constant {
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use constant {
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RBR => 0x00,
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RBR => 0x00,
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DLL => 0x00,
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DLL => 0x00,
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THR => 0x00,
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THR => 0x00,
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DLM => 0x01,
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DLM => 0x01,
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IER => 0x01,
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IER => 0x01,
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IIR => 0x02,
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IIR => 0x02,
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FCR => 0x02,
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FCR => 0x02,
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LCR => 0x03,
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LCR => 0x03,
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MCR => 0x04,
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MCR => 0x04,
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LSR => 0x05,
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LSR => 0x05,
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MSR => 0x06,
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MSR => 0x06,
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SCR => 0x07,
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SCR => 0x07,
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};
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};
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# Register settings
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# Register settings
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use constant {
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use constant {
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IER_ERBI => 0x01,
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IER_ERBI => 0x01,
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IER_ETBEI => 0x02,
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IER_ETBEI => 0x02,
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IER_ELSI => 0x04,
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IER_ELSI => 0x04,
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IER_EDSSI => 0x08,
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IER_EDSSI => 0x08,
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IIR_IP => 0x01,
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IIR_IP => 0x01,
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IIR_NONE => 0x01,
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IIR_NONE => 0x01,
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IIR_RLSI => 0x06,
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IIR_RLSI => 0x06,
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IIR_RDAI => 0x04,
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IIR_RDAI => 0x04,
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IIR_CTOI => 0x0C,
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IIR_CTOI => 0x0C,
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IIR_THRI => 0x02,
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IIR_THRI => 0x02,
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IIR_MSRI => 0x00,
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IIR_MSRI => 0x00,
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IIR_F64E => 0x20,
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IIR_F64E => 0x20,
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IIR_FE => 0xC0,
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IIR_FE => 0xC0,
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FCR_FE => 0x01,
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FCR_FE => 0x01,
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FCR_RXFR => 0x02,
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FCR_RXFR => 0x02,
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FCR_TXFR => 0x04,
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FCR_TXFR => 0x04,
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FCR_DMS => 0x08,
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FCR_DMS => 0x08,
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FCR_F64E => 0x20,
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FCR_F64E => 0x20,
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FCR_RT1 => 0x00,
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FCR_RT1 => 0x00,
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FCR_RT4 => 0x40,
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FCR_RT4 => 0x40,
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FCR_RT8 => 0x80,
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FCR_RT8 => 0x80,
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FCR_RT14 => 0xC0,
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FCR_RT14 => 0xC0,
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FCR_RT16 => 0x40,
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FCR_RT16 => 0x40,
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FCR_RT32 => 0x80,
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FCR_RT32 => 0x80,
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FCR_RT56 => 0xC0,
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FCR_RT56 => 0xC0,
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LCR_WLS5 => 0x00,
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LCR_WLS5 => 0x00,
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LCR_WLS6 => 0x01,
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LCR_WLS6 => 0x01,
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LCR_WLS7 => 0x02,
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LCR_WLS7 => 0x02,
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LCR_WLS8 => 0x03,
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LCR_WLS8 => 0x03,
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LCR_STB => 0x04,
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LCR_STB => 0x04,
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LCR_PEN => 0x08,
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LCR_PEN => 0x08,
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LCR_EPS => 0x10,
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LCR_EPS => 0x10,
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LCR_SP => 0x20,
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LCR_SP => 0x20,
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LCR_BC => 0x40,
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LCR_BC => 0x40,
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LCR_DLAB => 0x80,
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LCR_DLAB => 0x80,
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MCR_DTR => 0x01,
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MCR_DTR => 0x01,
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MCR_RTS => 0x02,
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MCR_RTS => 0x02,
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MCR_OUT1 => 0x04,
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MCR_OUT1 => 0x04,
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MCR_OUT2 => 0x08,
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MCR_OUT2 => 0x08,
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MCR_LOOP => 0x10,
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MCR_LOOP => 0x10,
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MCR_AFE => 0x20,
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MCR_AFE => 0x20,
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LSR_DR => 0x01,
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LSR_DR => 0x01,
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LSR_OE => 0x02,
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LSR_OE => 0x02,
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LSR_PE => 0x04,
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LSR_PE => 0x04,
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LSR_FE => 0x08,
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LSR_FE => 0x08,
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LSR_BI => 0x10,
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LSR_BI => 0x10,
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LSR_THRE => 0x20,
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LSR_THRE => 0x20,
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LSR_TEMT => 0x40,
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LSR_TEMT => 0x40,
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LSR_RXFE => 0x80,
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LSR_RXFE => 0x80,
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MSR_DCTS => 0x01,
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MSR_DCTS => 0x01,
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MSR_DDSR => 0x02,
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MSR_DDSR => 0x02,
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MSR_TERI => 0x04,
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MSR_TERI => 0x04,
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MSR_DDCD => 0x08,
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MSR_DDCD => 0x08,
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MSR_CTS => 0x10,
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MSR_CTS => 0x10,
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MSR_DSR => 0x20,
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MSR_DSR => 0x20,
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MSR_RI => 0x40,
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MSR_RI => 0x40,
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MSR_DCD => 0x80,
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MSR_DCD => 0x80,
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};
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};
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# Baudrate generator clock input period
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# Baudrate generator clock input period
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use constant BAUDGENCLK => 1.8432e6;
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use constant BAUDGENCLK => 1.8432e6;
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# Current DLM/DLL register
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# Current DLM/DLL register
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my $divisor = 0x0000;
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my $divisor = 0x0000;
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# Shadow registers with default values after reset
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# Shadow registers with default values after reset
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my $RBR = 0x00;
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my $RBR = 0x00;
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my $IER = 0x00;
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my $IER = 0x00;
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my $IIR = IIR_IP;
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my $IIR = IIR_IP;
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my $FCR = 0x00;
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my $FCR = 0x00;
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my $LCR = 0x00;
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my $LCR = 0x00;
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my $MCR = 0x00;
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my $MCR = 0x00;
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my $LSR = LSR_THRE | LSR_TEMT;
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my $LSR = LSR_THRE | LSR_TEMT;
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#my $MSR = 0x00;
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#my $MSR = 0x00;
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my $MSR = 0x0F;
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my $MSR = 0x0F;
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my $SCR = 0x00;
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my $SCR = 0x00;
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# De-assert reset (if available)
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# De-assert reset (if available)
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waitcycle (10);
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waitcycle (10);
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print ("#SET 0 1 1 1 1\n");
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print ("#SET 0 1 1 1 1\n");
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if (INITREGS) {
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if (INITREGS) {
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logmessage ("UART: Initializing...");
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logmessage ("UART: Initializing...");
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uart_write (IER, $IER);
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uart_write (IER, $IER);
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uart_write (FCR, $FCR);
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uart_write (FCR, $FCR);
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uart_write (LCR, $LCR);
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uart_write (LCR, $LCR);
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uart_write (MCR, $MCR);
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uart_write (MCR, $MCR);
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uart_write (SCR, $SCR);
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uart_write (SCR, $SCR);
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}
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}
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logmessage ("UART: Checking registers after reset...");
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logmessage ("UART: Checking registers after reset...");
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uart_read (RBR, $RBR);
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uart_read (RBR, $RBR);
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uart_read (RBR, $RBR);
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uart_read (RBR, $RBR);
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uart_read (IER, $IER);
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uart_read (IER, $IER);
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uart_read (IIR, $IIR);
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uart_read (IIR, $IIR);
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uart_read (LCR, $LCR);
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uart_read (LCR, $LCR);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (LSR, $LSR);
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uart_read (LSR, $LSR);
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uart_read (MSR, $MSR);
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uart_read (MSR, $MSR);
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uart_read (SCR, $SCR);
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uart_read (SCR, $SCR);
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#logmessage ("UART: Checking SCR write/read...");
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#logmessage ("UART: Checking SCR write/read...");
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#for (my $i = 0; $i <= 0x10; $i++) {
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#for (my $i = 0; $i <= 0x10; $i++) {
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# uart_write (SCR, $i);
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# uart_write (SCR, $i);
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# uart_read (SCR, $i);
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# uart_read (SCR, $i);
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#}
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#}
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if (LOCAL_LOOP) {
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if (LOCAL_LOOP) {
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logmessage ("UART: Enabling local LOOP mode...");
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logmessage ("UART: Enabling local LOOP mode...");
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uart_write (MCR, MCR_LOOP);
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uart_write (MCR, MCR_LOOP);
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uart_read (MCR, MCR_LOOP);
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uart_read (MCR, MCR_LOOP);
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}
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}
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uart_setbaudrate (115200);
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uart_setbaudrate (115200);
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logmessage ("UART: Enabling interrupts...");
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logmessage ("UART: Enabling interrupts...");
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uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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sub uart_check_control_lines ()
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sub uart_check_control_lines ()
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{
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{
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logmessage ("UART: Checking control lines...");
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logmessage ("UART: Checking control lines...");
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uart_write (MCR, $MCR | MCR_DTR);
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uart_write (MCR, $MCR | MCR_DTR);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DSR | MSR_DDSR);
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uart_read (MSR, MSR_DSR | MSR_DDSR);
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uart_read (MSR, MSR_DSR);
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uart_read (MSR, MSR_DSR);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR | MCR_RTS);
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uart_write (MCR, $MCR | MCR_RTS);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCTS);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR | MCR_OUT1);
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uart_write (MCR, $MCR | MCR_OUT1);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_RI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_RI);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR & ~MCR_OUT1);
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uart_write (MCR, $MCR & ~MCR_OUT1);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_TERI);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_read (MSR, MSR_CTS | MSR_DSR);
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uart_write (MCR, $MCR | MCR_OUT2);
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uart_write (MCR, $MCR | MCR_OUT2);
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD | MSR_DDCD);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
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uart_read (MSR, MSR_CTS | MSR_DSR | MSR_DCD);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
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uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2));
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uart_read (MCR, $MCR);
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uart_read (MCR, $MCR);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
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uart_read (MSR, MSR_DDSR | MSR_DCTS | MSR_DDCD);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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}
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}
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sub uart_check_interrupt_control ()
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sub uart_check_interrupt_control ()
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{
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{
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logmessage ("UART: Checking interrupt priority control...");
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logmessage ("UART: Checking interrupt priority control...");
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uart_write (MCR, $MCR | MCR_DTR);
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uart_write (MCR, $MCR | MCR_DTR);
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uart_write (MCR, $MCR & ~MCR_DTR);
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uart_write (MCR, $MCR & ~MCR_DTR);
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uart_write (THR, 0x12);
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uart_write (THR, 0x12);
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uart_wait (1);
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uart_wait (1);
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uart_write (LCR, $LCR | LCR_BC);
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uart_write (LCR, $LCR | LCR_BC);
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uart_wait (1);
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uart_wait (1);
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uart_write (LCR, $LCR & ~LCR_BC);
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uart_write (LCR, $LCR & ~LCR_BC);
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uart_read (IIR, IIR_RLSI);
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uart_read (IIR, IIR_RLSI);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_BI | LSR_FE | LSR_THRE | LSR_TEMT);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x00);
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uart_rrbr (0x00);
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uart_write (THR, 0x34);
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uart_write (THR, 0x34);
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uart_wait (1);
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uart_wait (1);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_write (THR, 0x56);
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uart_write (THR, 0x56);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_wait (1);
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uart_wait (1);
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uart_read (IIR, IIR_RLSI);
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uart_read (IIR, IIR_RLSI);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x56);
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uart_rrbr (0x56);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (IIR, IIR_MSRI);
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uart_read (MSR, MSR_DDSR);
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uart_read (MSR, MSR_DDSR);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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uart_write (THR, 0x78);
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uart_write (THR, 0x78);
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uart_wait (1);
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uart_wait (1);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_rrbr (0x78);
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uart_rrbr (0x78);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_THRI);
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uart_read (IIR, IIR_NONE);
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uart_read (IIR, IIR_NONE);
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}
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}
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sub uart_check_default ()
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sub uart_check_default ()
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{
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{
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for (my $mode = 0; $mode < 0x40; $mode++) {
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for (my $mode = 0; $mode < 0x40; $mode++) {
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logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
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logmessage (sprintf ("UART: Setting LCR to 0x%02X", $mode));
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uart_write (LCR, $mode);
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uart_write (LCR, $mode);
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logmessage ("UART: Transmission test single byte (FIFO disabled)");
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logmessage ("UART: Transmission test single byte (FIFO disabled)");
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uart_wait (1);
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uart_wait (1);
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uart_write (THR, 0x55);
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uart_write (THR, 0x55);
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uart_wait (1);
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uart_wait (1);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (IIR, IIR_RDAI);
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uart_read (IIR, IIR_RDAI);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
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uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x55);
|
uart_rrbr (0x55);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_THRI);
|
uart_read (IIR, IIR_THRI);
|
uart_read (IIR, IIR_NONE);
|
uart_read (IIR, IIR_NONE);
|
|
|
logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
|
logmessage ("UART: Transmission test multiple bytes (FIFO disabled)");
|
for (my $i = 0; $i < 10; $i++) {
|
for (my $i = 0; $i < 10; $i++) {
|
uart_read (IIR, IIR_NONE);
|
uart_read (IIR, IIR_NONE);
|
uart_write (THR, $i);
|
uart_write (THR, $i);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr ($i);
|
uart_rrbr ($i);
|
uart_read (IIR, IIR_THRI);
|
uart_read (IIR, IIR_THRI);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
}
|
}
|
|
|
#logmessage ("UART: Transmission test loop (FIFO disabled)");
|
#logmessage ("UART: Transmission test loop (FIFO disabled)");
|
#for (my $i = 0; $i < 1000; $i++) {
|
#for (my $i = 0; $i < 1000; $i++) {
|
# if (!($i % 100)) {
|
# if (!($i % 100)) {
|
# logmessage ("UART: Loop " . $i);
|
# logmessage ("UART: Loop " . $i);
|
# }
|
# }
|
# uart_write (THR, $i);
|
# uart_write (THR, $i);
|
# uart_read (IIR, IIR_THRI);
|
# uart_read (IIR, IIR_THRI);
|
# uart_wait (1);
|
# uart_wait (1);
|
# uart_read (IIR, IIR_RDAI);
|
# uart_read (IIR, IIR_RDAI);
|
# uart_rrbr ($i);
|
# uart_rrbr ($i);
|
# uart_read (IIR, IIR_NONE);
|
# uart_read (IIR, IIR_NONE);
|
#}
|
#}
|
|
|
logmessage ("UART: Transmission test overflow (FIFO disabled)");
|
logmessage ("UART: Transmission test overflow (FIFO disabled)");
|
uart_write (THR, 0x55);
|
uart_write (THR, 0x55);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (IIR, IIR_RDAI);
|
uart_write (THR, 0xAA);
|
uart_write (THR, 0xAA);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (IIR, IIR_RLSI);
|
uart_read (IIR, IIR_RLSI);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (IIR, IIR_RDAI);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0xAA);
|
uart_rrbr (0xAA);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_THRI);
|
uart_read (IIR, IIR_THRI);
|
uart_read (IIR, IIR_NONE);
|
uart_read (IIR, IIR_NONE);
|
|
|
logmessage ("UART: Break control test");
|
logmessage ("UART: Break control test");
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_read (LCR, $LCR);
|
uart_read (LCR, $LCR);
|
uart_wait (2);
|
uart_wait (2);
|
uart_read (IIR, IIR_RLSI);
|
uart_read (IIR, IIR_RLSI);
|
if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
|
if (($LCR & LCR_PEN) && !($LCR & LCR_EPS)) {
|
uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_PE | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
} else {
|
} else {
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT);
|
}
|
}
|
uart_read (IIR, IIR_RDAI);
|
uart_read (IIR, IIR_RDAI);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (RBR, 0x00);
|
uart_read (RBR, 0x00);
|
uart_read (IIR, IIR_NONE);
|
uart_read (IIR, IIR_NONE);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_read (LCR, $LCR);
|
uart_read (LCR, $LCR);
|
uart_wait (2);
|
uart_wait (2);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE);
|
uart_read (IIR, IIR_NONE);
|
}
|
}
|
|
|
uart_write (LCR, 0x00);
|
uart_write (LCR, 0x00);
|
}
|
}
|
|
|
sub uart_check_fifo ()
|
sub uart_check_fifo ()
|
{
|
{
|
logmessage ("UART: Enabling FIFO...");
|
logmessage ("UART: Enabling FIFO...");
|
uart_write (FCR, FCR_FE);
|
uart_write (FCR, FCR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_send (1);
|
uart_send (1);
|
uart_wait (4);
|
uart_wait (4);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO trigger level 4 byte...");
|
logmessage ("UART: Testing FIFO trigger level 4 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
uart_send (3);
|
uart_send (3);
|
uart_wait (7);
|
uart_wait (7);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_send (2);
|
uart_send (2);
|
uart_wait (6);
|
uart_wait (6);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_wait (2);
|
uart_wait (2);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_rrbr (2);
|
uart_rrbr (2);
|
uart_rrbr (0);
|
uart_rrbr (0);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO trigger level 8 byte...");
|
logmessage ("UART: Testing FIFO trigger level 8 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT8);
|
uart_write (FCR, FCR_FE | FCR_RT8);
|
uart_send (7);
|
uart_send (7);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_wait (11);
|
uart_wait (11);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_send (2);
|
uart_send (2);
|
uart_wait (6);
|
uart_wait (6);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_wait (2);
|
uart_wait (2);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_rrbr (2);
|
uart_rrbr (2);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (3);
|
uart_rrbr (3);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (4);
|
uart_rrbr (4);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (5);
|
uart_rrbr (5);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (6);
|
uart_rrbr (6);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0);
|
uart_rrbr (0);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO trigger level 14 byte...");
|
logmessage ("UART: Testing FIFO trigger level 14 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
uart_send (13);
|
uart_send (13);
|
uart_wait (17);
|
uart_wait (17);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_send (2);
|
uart_send (2);
|
uart_wait (6);
|
uart_wait (6);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_rrbr (2);
|
uart_rrbr (2);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (3);
|
uart_rrbr (3);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (4);
|
uart_rrbr (4);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (5);
|
uart_rrbr (5);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (6);
|
uart_rrbr (6);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (7);
|
uart_rrbr (7);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (8);
|
uart_rrbr (8);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (9);
|
uart_rrbr (9);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (10);
|
uart_rrbr (10);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (11);
|
uart_rrbr (11);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (12);
|
uart_rrbr (12);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0);
|
uart_rrbr (0);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (1);
|
uart_rrbr (1);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO overrun...");
|
logmessage ("UART: Testing FIFO overrun...");
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_send (17);
|
uart_send (17);
|
uart_wait (17);
|
uart_wait (17);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_RDAI | IIR_FE);
|
uart_read (IIR, IIR_RDAI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_write (FCR, FCR_FE | FCR_RXFR);
|
uart_write (FCR, FCR_FE | FCR_RXFR);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Miscellaneous FIFO tests...");
|
logmessage ("UART: Miscellaneous FIFO tests...");
|
uart_write (LCR, 0x03);
|
uart_write (LCR, 0x03);
|
uart_write (IER, IER_ERBI);
|
uart_write (IER, IER_ERBI);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
uart_write (FCR, FCR_FE | FCR_RT14);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Sending 8 words");
|
logmessage ("UART: Sending 8 words");
|
uart_send (8);
|
uart_send (8);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_wait (12);
|
uart_wait (12);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Receiving 8 words");
|
logmessage ("UART: Receiving 8 words");
|
uart_recv (8, 0);
|
uart_recv (8, 0);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Sending 16 words");
|
logmessage ("UART: Sending 16 words");
|
uart_send (16);
|
uart_send (16);
|
uart_wait (4);
|
uart_wait (4);
|
logmessage ("UART: Receiving 4 words");
|
logmessage ("UART: Receiving 4 words");
|
uart_recv (4, 0);
|
uart_recv (4, 0);
|
logmessage ("UART: Sending 4 words");
|
logmessage ("UART: Sending 4 words");
|
uart_send (4);
|
uart_send (4);
|
uart_wait (12);
|
uart_wait (12);
|
logmessage ("UART: Receiving 12 words");
|
logmessage ("UART: Receiving 12 words");
|
uart_recv (12, 4);
|
uart_recv (12, 4);
|
uart_wait (8);
|
uart_wait (8);
|
logmessage ("UART: Receiving 2 words");
|
logmessage ("UART: Receiving 2 words");
|
uart_recv (2, 0);
|
uart_recv (2, 0);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Sending 40 words");
|
logmessage ("UART: Sending 40 words");
|
uart_send (40);
|
uart_send (40);
|
uart_wait (4);
|
uart_wait (4);
|
uart_read (LSR, LSR_DR);
|
uart_read (LSR, LSR_DR);
|
uart_wait (20);
|
uart_wait (20);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
logmessage ("UART: Receiving 3 words");
|
logmessage ("UART: Receiving 3 words");
|
uart_recv (2, 2);
|
uart_recv (2, 2);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
logmessage ("UART: Receiving 13 words");
|
logmessage ("UART: Receiving 13 words");
|
uart_recv (13, 1);
|
uart_recv (13, 1);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: Testing FIFO error counter...");
|
logmessage ("UART: Testing FIFO error counter...");
|
uart_write (IER, IER_ERBI | IER_ELSI);
|
uart_write (IER, IER_ERBI | IER_ELSI);
|
logmessage ("UART: Sending 2 words");
|
logmessage ("UART: Sending 2 words");
|
uart_send (2);
|
uart_send (2);
|
uart_wait (2);
|
uart_wait (2);
|
logmessage ("UART: Sending break");
|
logmessage ("UART: Sending break");
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_wait (1);
|
uart_wait (1);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
logmessage ("UART: Sending 4 words");
|
logmessage ("UART: Sending 4 words");
|
uart_send (4);
|
uart_send (4);
|
uart_wait (4);
|
uart_wait (4);
|
logmessage ("UART: Sending break");
|
logmessage ("UART: Sending break");
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_wait (1);
|
uart_wait (1);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
logmessage ("UART: Sending 2 words");
|
logmessage ("UART: Sending 2 words");
|
uart_send (2);
|
uart_send (2);
|
uart_wait (6);
|
uart_wait (6);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
logmessage ("UART: Reading 2 words");
|
logmessage ("UART: Reading 2 words");
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
logmessage ("UART: Reading break word");
|
logmessage ("UART: Reading break word");
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
logmessage ("UART: Reading 4 words");
|
logmessage ("UART: Reading 4 words");
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_rrbr (0x02);
|
uart_rrbr (0x02);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_rrbr (0x03);
|
uart_rrbr (0x03);
|
uart_wait (1);
|
uart_wait (1);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
logmessage ("UART: Reading break word");
|
logmessage ("UART: Reading break word");
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
|
|
logmessage ("UART: Sending break");
|
logmessage ("UART: Sending break");
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_write (LCR, $LCR | LCR_BC);
|
uart_wait (1);
|
uart_wait (1);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_write (LCR, $LCR & ~LCR_BC);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (IIR, IIR_RLSI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
|
logmessage ("UART: Reading break word");
|
logmessage ("UART: Reading break word");
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
|
|
logmessage ("UART: FIFO test end");
|
logmessage ("UART: FIFO test end");
|
}
|
}
|
|
|
sub uart_check_fifo64 ()
|
sub uart_check_fifo64 ()
|
{
|
{
|
logmessage ("UART: Testing FIFO in 64 byte mode...");
|
logmessage ("UART: Testing FIFO in 64 byte mode...");
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
uart_write (FCR, FCR_F64E | FCR_FE | FCR_RXFR | FCR_TXFR);
|
uart_write (FCR, FCR_F64E | FCR_FE | FCR_RXFR | FCR_TXFR);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (FCR, FCR_F64E | FCR_FE);
|
uart_write (FCR, FCR_F64E | FCR_FE);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
|
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
logmessage ("UART: Testing FIFO trigger level 1 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_write (FCR, FCR_FE | FCR_RT1);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_send (1);
|
uart_send (1);
|
uart_wait (4);
|
uart_wait (4);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
|
|
logmessage ("UART: Testing FIFO trigger level 16 byte...");
|
logmessage ("UART: Testing FIFO trigger level 16 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT16);
|
uart_write (FCR, FCR_FE | FCR_RT16);
|
uart_send (15);
|
uart_send (15);
|
uart_wait (15);
|
uart_wait (15);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_send (3);
|
uart_send (3);
|
uart_wait (3);
|
uart_wait (3);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_rrbr (0x02);
|
uart_rrbr (0x02);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_recv (12, 3);
|
uart_recv (12, 3);
|
uart_recv (3);
|
uart_recv (3);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
|
|
logmessage ("UART: Testing FIFO trigger level 32 byte...");
|
logmessage ("UART: Testing FIFO trigger level 32 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT32);
|
uart_write (FCR, FCR_FE | FCR_RT32);
|
uart_send (31);
|
uart_send (31);
|
uart_wait (31);
|
uart_wait (31);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_send (3);
|
uart_send (3);
|
uart_wait (3);
|
uart_wait (3);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_rrbr (0x02);
|
uart_rrbr (0x02);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_recv (28, 3);
|
uart_recv (28, 3);
|
uart_recv (3);
|
uart_recv (3);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
|
|
logmessage ("UART: Testing FIFO trigger level 56 byte...");
|
logmessage ("UART: Testing FIFO trigger level 56 byte...");
|
uart_write (FCR, FCR_FE | FCR_RT56);
|
uart_write (FCR, FCR_FE | FCR_RT56);
|
uart_send (55);
|
uart_send (55);
|
uart_wait (55);
|
uart_wait (55);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x00);
|
uart_rrbr (0x00);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_send (3);
|
uart_send (3);
|
uart_wait (3);
|
uart_wait (3);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_rrbr (0x01);
|
uart_rrbr (0x01);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
|
uart_rrbr (0x02);
|
uart_rrbr (0x02);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_THRI | IIR_FE | IIR_F64E);
|
uart_recv (52, 3);
|
uart_recv (52, 3);
|
uart_recv (3);
|
uart_recv (3);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
uart_read (IIR, IIR_NONE | IIR_FE | IIR_F64E);
|
|
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (FCR, $FCR & ~FCR_F64E);
|
uart_write (FCR, $FCR & ~FCR_F64E);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
|
|
logmessage ("UART: FIFO64 test end");
|
logmessage ("UART: FIFO64 test end");
|
}
|
}
|
|
|
sub uart_check_afc ()
|
sub uart_check_afc ()
|
{
|
{
|
logmessage ("UART: Automatic flow control test");
|
logmessage ("UART: Automatic flow control test");
|
uart_write (LCR, LCR_WLS8);
|
uart_write (LCR, LCR_WLS8);
|
uart_read (LCR, LCR_WLS8);
|
uart_read (LCR, LCR_WLS8);
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
uart_read (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
|
logmessage ("UART: Setting FIFO trigger level to 4 bytes");
|
logmessage ("UART: Setting FIFO trigger level to 4 bytes");
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
uart_write (FCR, FCR_FE | FCR_RT4);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
logmessage ("UART: Enabling Auto-CTS");
|
logmessage ("UART: Enabling Auto-CTS");
|
uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
|
uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
|
uart_read (MSR, 0);
|
uart_read (MSR, 0);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
logmessage ("UART: Send 3 words");
|
logmessage ("UART: Send 3 words");
|
uart_send (3);
|
uart_send (3);
|
uart_wait (6);
|
uart_wait (6);
|
logmessage ("UART: Expecting no data was sent");
|
logmessage ("UART: Expecting no data was sent");
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (LSR, 0);
|
uart_read (LSR, 0);
|
logmessage ("UART: Enabling Auto-RTS");
|
logmessage ("UART: Enabling Auto-RTS");
|
uart_write (MCR, $MCR | MCR_RTS);
|
uart_write (MCR, $MCR | MCR_RTS);
|
logmessage ("UART: Check if CTS is enabled");
|
logmessage ("UART: Check if CTS is enabled");
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
uart_wait (8);
|
uart_wait (8);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Check if CTS is enabled");
|
logmessage ("UART: Check if CTS is enabled");
|
uart_read (MSR, MSR_CTS);
|
uart_read (MSR, MSR_CTS);
|
logmessage ("UART: Send 1 word");
|
logmessage ("UART: Send 1 word");
|
uart_send (1);
|
uart_send (1);
|
uart_wait (2);
|
uart_wait (2);
|
logmessage ("UART: Check if CTS is disabled");
|
logmessage ("UART: Check if CTS is disabled");
|
uart_read (MSR, MSR_DCTS);
|
uart_read (MSR, MSR_DCTS);
|
logmessage ("UART: Check LSR");
|
logmessage ("UART: Check LSR");
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
uart_read (IIR, IIR_CTOI | IIR_FE);
|
logmessage ("UART: Receive 3 words");
|
logmessage ("UART: Receive 3 words");
|
uart_recv (3);
|
uart_recv (3);
|
logmessage ("UART: Check if CTS is disabled");
|
logmessage ("UART: Check if CTS is disabled");
|
uart_read (MSR, 0);
|
uart_read (MSR, 0);
|
logmessage ("UART: Receive 1 word");
|
logmessage ("UART: Receive 1 word");
|
uart_recv (1);
|
uart_recv (1);
|
logmessage ("UART: Check LSR");
|
logmessage ("UART: Check LSR");
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
logmessage ("UART: Check if CTS is enabled again");
|
logmessage ("UART: Check if CTS is enabled again");
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
logmessage ("UART: Send 6 words");
|
logmessage ("UART: Send 6 words");
|
uart_send (5);
|
uart_send (5);
|
uart_send (1);
|
uart_send (1);
|
uart_wait (4);
|
uart_wait (4);
|
logmessage ("UART: Check if CTS is disabled");
|
logmessage ("UART: Check if CTS is disabled");
|
uart_read (MSR, MSR_DCTS);
|
uart_read (MSR, MSR_DCTS);
|
logmessage ("UART: Check LSR");
|
logmessage ("UART: Check LSR");
|
uart_read (LSR, LSR_DR);
|
uart_read (LSR, LSR_DR);
|
uart_wait (1);
|
uart_wait (1);
|
logmessage ("UART: Receive 5 words");
|
logmessage ("UART: Receive 5 words");
|
uart_recv (5);
|
uart_recv (5);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_wait (2);
|
uart_wait (2);
|
logmessage ("UART: Check LSR");
|
logmessage ("UART: Check LSR");
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
|
logmessage ("UART: Check if CTS is enabled again");
|
logmessage ("UART: Check if CTS is enabled again");
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
uart_read (MSR, MSR_DCTS | MSR_CTS);
|
logmessage ("UART: Receive 1 words");
|
logmessage ("UART: Receive 1 words");
|
uart_recv (1);
|
uart_recv (1);
|
logmessage ("UART: Check LSR");
|
logmessage ("UART: Check LSR");
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (LSR, LSR_THRE | LSR_TEMT);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_THRI | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
logmessage ("UART: Check if CTS is enabled");
|
logmessage ("UART: Check if CTS is enabled");
|
uart_read (MSR, MSR_CTS);
|
uart_read (MSR, MSR_CTS);
|
logmessage ("UART: Disable Automatic flow control");
|
logmessage ("UART: Disable Automatic flow control");
|
uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
|
uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
|
uart_read (MSR, MSR_DCTS);
|
uart_read (MSR, MSR_DCTS);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (IIR, IIR_NONE | IIR_FE);
|
uart_read (MCR, $MCR);
|
uart_read (MCR, $MCR);
|
logmessage ("UART: Automatic flow control test finished");
|
logmessage ("UART: Automatic flow control test finished");
|
}
|
}
|
|
|
if (TEST_CONTROL) {
|
if (TEST_CONTROL) {
|
uart_check_control_lines ();
|
uart_check_control_lines ();
|
}
|
}
|
if (TEST_INTERRUPT) {
|
if (TEST_INTERRUPT) {
|
uart_check_interrupt_control ();
|
uart_check_interrupt_control ();
|
}
|
}
|
if (TEST_DEFAULT) {
|
if (TEST_DEFAULT) {
|
uart_check_default ();
|
uart_check_default ();
|
}
|
}
|
if (TEST_FIFO) {
|
if (TEST_FIFO) {
|
uart_check_fifo ();
|
uart_check_fifo ();
|
}
|
}
|
if (TEST_FIFO64) {
|
if (TEST_FIFO64) {
|
uart_check_fifo64 ();
|
uart_check_fifo64 ();
|
}
|
}
|
if (TEST_AFC) {
|
if (TEST_AFC) {
|
uart_check_afc ();
|
uart_check_afc ();
|
}
|
}
|
|
|
##################################################################
|
##################################################################
|
# End main process
|
# End main process
|
##################################################################
|
##################################################################
|
|
|
|
|
|
|
##################################################################
|
##################################################################
|
# Sub functions
|
# Sub functions
|
##################################################################
|
##################################################################
|
|
|
# Convert number to binary string
|
# Convert number to binary string
|
sub num2binary($$)
|
sub num2binary($$)
|
{
|
{
|
my($num) = @_;
|
my($num) = @_;
|
my $binary = $num ? '' : '0'; # in case $num is zero
|
my $binary = $num ? '' : '0'; # in case $num is zero
|
my $len = $_[1];
|
my $len = $_[1];
|
my $result;
|
my $result;
|
|
|
while ($num) {
|
while ($num) {
|
$binary .= $num & 1 ? 1 : 0; # do the LSB
|
$binary .= $num & 1 ? 1 : 0; # do the LSB
|
$num >>= 1; # on to the next bit
|
$num >>= 1; # on to the next bit
|
}
|
}
|
|
|
$result = scalar reverse $binary;
|
$result = scalar reverse $binary;
|
while (length($result)<$len) {
|
while (length($result)<$len) {
|
$result = "0".$result;
|
$result = "0".$result;
|
}
|
}
|
|
|
return $result;
|
return $result;
|
}
|
}
|
|
|
|
|
# Insert wait cycles
|
# Insert wait cycles
|
sub waitcycle($)
|
sub waitcycle($)
|
{
|
{
|
printf ("#WAIT %d\n", $_[0]);
|
printf ("#WAIT %d\n", $_[0]);
|
#printf ("DE %d\n", $_[0]+5);
|
#printf ("DE %d\n", $_[0]+5);
|
}
|
}
|
|
|
# Log message
|
# Log message
|
sub logmessage($)
|
sub logmessage($)
|
{
|
{
|
print "#LOG $_[0]\n";
|
print "#LOG $_[0]\n";
|
#print "LO $_[0]\n";
|
#print "LO $_[0]\n";
|
}
|
}
|
|
|
# Read from UART
|
# Read from UART
|
sub uart_read($$)
|
sub uart_read($$)
|
{
|
{
|
printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
#printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
#printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
}
|
}
|
|
|
# Filter read from RBR (mask word length)
|
# Filter read from RBR (mask word length)
|
sub uart_rrbr($)
|
sub uart_rrbr($)
|
{
|
{
|
my $wls = $LCR & 0x03;
|
my $wls = $LCR & 0x03;
|
my $data = $_[0];
|
my $data = $_[0];
|
|
|
if ($wls == 0x00) { $data &= 0x1F; }
|
if ($wls == 0x00) { $data &= 0x1F; }
|
if ($wls == 0x01) { $data &= 0x3F; }
|
if ($wls == 0x01) { $data &= 0x3F; }
|
if ($wls == 0x02) { $data &= 0x7F; }
|
if ($wls == 0x02) { $data &= 0x7F; }
|
uart_read (RBR, $data);
|
uart_read (RBR, $data);
|
}
|
}
|
|
|
# Write to UART
|
# Write to UART
|
sub uart_write($$)
|
sub uart_write($$)
|
{
|
{
|
# Shadow register writes to local copy
|
# Shadow register writes to local copy
|
SWITCH: {
|
SWITCH: {
|
if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
|
if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
|
if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
|
if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
|
if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
|
if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
|
if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
|
if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
|
if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
|
if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
|
if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
|
if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
|
}
|
}
|
|
|
printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
|
#printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
#printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
|
}
|
}
|
|
|
# Set UART baudrate
|
# Set UART baudrate
|
sub uart_setbaudrate($)
|
sub uart_setbaudrate($)
|
{
|
{
|
logmessage ("UART: Setting baudrate to $_[0]");
|
logmessage ("UART: Setting baudrate to $_[0]");
|
$divisor = BAUDGENCLK / (16 * $_[0]);
|
$divisor = BAUDGENCLK / (16 * $_[0]);
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (LCR, $LCR | LCR_DLAB);
|
uart_write (DLL, $divisor);
|
uart_write (DLL, $divisor);
|
uart_write (DLM, $divisor >> 8);
|
uart_write (DLM, $divisor >> 8);
|
uart_read (LCR, $LCR);
|
uart_read (LCR, $LCR);
|
uart_read (DLL, $divisor);
|
uart_read (DLL, $divisor);
|
uart_read (DLM, $divisor >> 8);
|
uart_read (DLM, $divisor >> 8);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_write (LCR, $LCR & ~LCR_DLAB);
|
uart_read (LCR, $LCR);
|
uart_read (LCR, $LCR);
|
}
|
}
|
|
|
# Wait until n words are transmitted/received
|
# Wait until n words are transmitted/received
|
sub uart_wait ($)
|
sub uart_wait ($)
|
{
|
{
|
my $steps = 1; # Start bit
|
my $steps = 1; # Start bit
|
$steps += 5 + ($LCR & 0x03); # Data
|
$steps += 5 + ($LCR & 0x03); # Data
|
$steps += $LCR & LCR_PEN ? 1 : 0; # Parity
|
$steps += $LCR & LCR_PEN ? 1 : 0; # Parity
|
$steps += $LCR & LCR_STB ? 2 : 1; # Stop bit
|
$steps += $LCR & LCR_STB ? 2 : 1; # Stop bit
|
$steps += 2; # Extra delay
|
$steps += 2; # Extra delay
|
|
|
my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
|
my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
|
waitcycle ($txtime/CYCLE);
|
waitcycle ($txtime/CYCLE);
|
}
|
}
|
|
|
# Send n bytes
|
# Send n bytes
|
sub uart_send ($)
|
sub uart_send ($)
|
{
|
{
|
for (my $i = 0; $i < $_[0]; $i++) {
|
for (my $i = 0; $i < $_[0]; $i++) {
|
uart_write (THR, $i);
|
uart_write (THR, $i);
|
if (!($FCR & FCR_FE)) {
|
if (!($FCR & FCR_FE)) {
|
uart_wait (1);
|
uart_wait (1);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
# Receive n bytes
|
# Receive n bytes
|
sub uart_recv ($$)
|
sub uart_recv ($$)
|
{
|
{
|
for (my $i = 0; $i < $_[0]; $i++) {
|
for (my $i = 0; $i < $_[0]; $i++) {
|
uart_rrbr ($i + $_[1]);
|
uart_rrbr ($i + $_[1]);
|
}
|
}
|
}
|
}
|
|
|
|
|