//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// uart receive module
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// uart receive module
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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module uart_rx
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module uart_rx
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(
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(
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clock, reset,
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clock, reset,
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ce_16, ser_in,
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ce_16, ser_in,
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rx_data, new_rx_data
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rx_data, new_rx_data
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);
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);
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// modules inputs and outputs
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// modules inputs and outputs
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input clock; // global clock input
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input clock; // global clock input
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input reset; // global reset input
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input reset; // global reset input
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input ce_16; // baud rate multiplyed by 16 - generated by baud module
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input ce_16; // baud rate multiplyed by 16 - generated by baud module
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input ser_in; // serial data input
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input ser_in; // serial data input
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output [7:0] rx_data; // data byte received
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output [7:0] rx_data; // data byte received
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output new_rx_data; // signs that a new byte was received
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output new_rx_data; // signs that a new byte was received
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// internal wires
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// internal wires
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wire ce_1; // clock enable at bit rate
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wire ce_1; // clock enable at bit rate
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wire ce_1_mid; // clock enable at the middle of each bit - used to sample data
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wire ce_1_mid; // clock enable at the middle of each bit - used to sample data
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// internal registers
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// internal registers
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reg [7:0] rx_data;
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reg [7:0] rx_data;
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reg new_rx_data;
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reg new_rx_data;
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reg [1:0] in_sync;
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reg [1:0] in_sync;
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reg rx_busy;
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reg rx_busy;
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reg [3:0] count16;
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reg [3:0] count16;
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reg [3:0] bit_count;
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reg [3:0] bit_count;
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reg [7:0] data_buf;
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reg [7:0] data_buf;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module implementation
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// module implementation
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// input async input is sampled twice
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// input async input is sampled twice
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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in_sync <= 2'b11;
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in_sync <= 2'b11;
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else
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else
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in_sync <= {in_sync[0], ser_in};
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in_sync <= {in_sync[0], ser_in};
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end
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end
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// a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
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// a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
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// this counter is used to detect the start bit while the receiver is not receiving and
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// this counter is used to detect the start bit while the receiver is not receiving and
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// signs the sampling cycle during reception.
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// signs the sampling cycle during reception.
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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count16 <= 4'b0;
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count16 <= 4'b0;
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else if (ce_16)
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else if (ce_16)
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begin
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begin
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if (rx_busy | (in_sync[1] == 1'b0))
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if (rx_busy | (in_sync[1] == 1'b0))
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count16 <= count16 + 4'b1;
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count16 <= count16 + 4'b1;
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else
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else
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count16 <= 4'b0;
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count16 <= 4'b0;
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end
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end
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end
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end
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// ce_1 pulse indicating expected end of current bit
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// ce_1 pulse indicating expected end of current bit
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assign ce_1 = (count16 == 4'b1111) & ce_16;
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assign ce_1 = (count16 == 4'b1111) & ce_16;
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// ce_1_mid pulse indication the sampling clock cycle of the current data bit
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// ce_1_mid pulse indication the sampling clock cycle of the current data bit
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assign ce_1_mid = (count16 == 4'b0111) & ce_16;
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assign ce_1_mid = (count16 == 4'b0111) & ce_16;
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// receiving busy flag
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// receiving busy flag
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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rx_busy <= 1'b0;
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rx_busy <= 1'b0;
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else if (~rx_busy & ce_1_mid)
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else if (~rx_busy & ce_1_mid)
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rx_busy <= 1'b1;
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rx_busy <= 1'b1;
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else if (rx_busy & (bit_count == 4'h9) & ce_1)
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else if (rx_busy & (bit_count == 4'h8) & ce_1_mid)
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rx_busy <= 1'b0;
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rx_busy <= 1'b0;
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end
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end
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// bit counter
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// bit counter
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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bit_count <= 4'h0;
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bit_count <= 4'h0;
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else if (~rx_busy)
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else if (~rx_busy)
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bit_count <= 4'h0;
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bit_count <= 4'h0;
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else if (rx_busy & ce_1_mid)
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else if (rx_busy & ce_1_mid)
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bit_count <= bit_count + 4'h1;
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bit_count <= bit_count + 4'h1;
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end
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end
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// data buffer shift register
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// data buffer shift register
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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data_buf <= 8'h0;
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data_buf <= 8'h0;
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else if (rx_busy & ce_1_mid)
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else if (rx_busy & ce_1_mid)
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data_buf <= {in_sync[1], data_buf[7:1]};
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data_buf <= {in_sync[1], data_buf[7:1]};
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end
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end
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// data output and flag
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// data output and flag
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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rx_data <= 8'h0;
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rx_data <= 8'h0;
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new_rx_data <= 1'b0;
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new_rx_data <= 1'b0;
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end
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end
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else if (rx_busy & (bit_count == 4'h8) & ce_1)
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else if (rx_busy & (bit_count == 4'h8) & ce_1)
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begin
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begin
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rx_data <= data_buf;
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rx_data <= data_buf;
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new_rx_data <= 1'b1;
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new_rx_data <= 1'b1;
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end
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end
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else
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else
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new_rx_data <= 1'b0;
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new_rx_data <= 1'b0;
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end
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end
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endmodule
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endmodule
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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