//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// uart transmit module
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// uart transmit module
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//
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//
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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module uart_tx
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module uart_tx
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(
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(
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clock, reset,
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clock, reset,
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ce_16, tx_data, new_tx_data,
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ce_16, tx_data, new_tx_data,
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ser_out, tx_busy
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ser_out, tx_busy
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);
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);
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// modules inputs and outputs
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// modules inputs and outputs
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input clock; // global clock input
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input clock; // global clock input
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input reset; // global reset input
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input reset; // global reset input
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input ce_16; // baud rate multiplyed by 16 - generated by baud module
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input ce_16; // baud rate multiplyed by 16 - generated by baud module
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input [7:0] tx_data; // data byte to transmit
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input [7:0] tx_data; // data byte to transmit
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input new_tx_data; // asserted to indicate that there is a new data byte for transmission
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input new_tx_data; // asserted to indicate that there is a new data byte for transmission
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output ser_out; // serial data output
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output ser_out; // serial data output
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output tx_busy; // signs that transmitter is busy
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output tx_busy; // signs that transmitter is busy
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// internal wires
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// internal wires
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wire ce_1; // clock enable at bit rate
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wire ce_1; // clock enable at bit rate
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// internal registers
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// internal registers
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reg ser_out;
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reg ser_out;
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reg tx_busy;
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reg tx_busy;
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reg [3:0] count16;
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reg [3:0] count16;
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reg [3:0] bit_count;
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reg [3:0] bit_count;
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reg [8:0] data_buf;
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reg [8:0] data_buf;
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// module implementation
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// module implementation
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// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
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// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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count16 <= 4'b0;
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count16 <= 4'b0;
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else if (tx_busy & ce_16)
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else if (tx_busy & ce_16)
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count16 <= count16 + 4'b1;
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count16 <= count16 + 4'b1;
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else if (~tx_busy)
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else if (~tx_busy)
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count16 <= 4'b0;
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count16 <= 4'b0;
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end
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end
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// ce_1 pulse indicating output data bit should be updated
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// ce_1 pulse indicating output data bit should be updated
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assign ce_1 = (count16 == 4'b1111) & ce_16;
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assign ce_1 = (count16 == 4'b1111) & ce_16;
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// tx_busy flag
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// tx_busy flag
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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tx_busy <= 1'b0;
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tx_busy <= 1'b0;
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else if (~tx_busy & new_tx_data)
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else if (~tx_busy & new_tx_data)
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tx_busy <= 1'b1;
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tx_busy <= 1'b1;
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else if (tx_busy & (bit_count == 4'ha) & ce_1)
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else if (tx_busy & (bit_count == 4'h9) & ce_1)
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tx_busy <= 1'b0;
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tx_busy <= 1'b0;
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end
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end
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// output bit counter
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// output bit counter
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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bit_count <= 4'h0;
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bit_count <= 4'h0;
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else if (tx_busy & ce_1)
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else if (tx_busy & ce_1)
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bit_count <= bit_count + 4'h1;
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bit_count <= bit_count + 4'h1;
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else if (~tx_busy)
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else if (~tx_busy)
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bit_count <= 4'h0;
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bit_count <= 4'h0;
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end
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end
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// data shift register
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// data shift register
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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data_buf <= 9'b0;
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data_buf <= 9'b0;
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else if (~tx_busy)
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else if (~tx_busy)
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data_buf <= {tx_data, 1'b0};
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data_buf <= {tx_data, 1'b0};
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else if (tx_busy & ce_1)
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else if (tx_busy & ce_1)
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data_buf <= {1'b1, data_buf[8:1]};
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data_buf <= {1'b1, data_buf[8:1]};
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end
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end
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// output data bit
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// output data bit
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always @ (posedge clock or posedge reset)
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always @ (posedge clock or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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ser_out <= 1'b1;
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ser_out <= 1'b1;
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else if (tx_busy)
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else if (tx_busy)
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ser_out <= data_buf[0];
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ser_out <= data_buf[0];
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else
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else
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ser_out <= 1'b1;
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ser_out <= 1'b1;
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end
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end
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endmodule
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endmodule
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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// Th.. Th.. Th.. Thats all folks !!!
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// Th.. Th.. Th.. Thats all folks !!!
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//---------------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------------
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