//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : MONITOR
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// UNIT : MONITOR
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// TITLE : UART Monitor
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// TITLE : UART Monitor
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// DESCRIPTION: This
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// DESCRIPTION: This
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 12012016 FILE CREATION
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// 1 HANY SALAH 12012016 FILE CREATION
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// 2 HANY SALAH 31012016 ADD INVALID WRITE CASE TO TRANSACTION
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// PACKETAIZATION METHOD
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// OPENCORES MEMBERS ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE
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// CREATOR'S PERMISSION
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// CREATOR'S PERMISSION
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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class uart_monitor extends uvm_monitor;
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class uart_monitor extends uvm_monitor;
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uart_transaction trans;
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uart_transaction trans;
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uart_config _config;
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uart_config _config;
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virtual uart_interface uart_inf;
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virtual uart_interface uart_inf;
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virtual rf_interface rf_inf;
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virtual rf_interface rf_inf;
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uvm_analysis_port #(uart_transaction) mon_scbd;
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uvm_analysis_port #(uart_transaction) mon_scbd;
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`uvm_component_utils(uart_monitor)
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`uvm_component_utils(uart_monitor)
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function new (string name, uvm_component parent);
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function new (string name, uvm_component parent);
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super.new(name,parent);
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super.new(name,parent);
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endfunction:new
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endfunction:new
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function void display_content ();
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function void display_content ();
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$display("here %s\n command_type = %p \n command = %p \n char_type = %p \n space_type1 = %p \n space_wrong1 = %8b \n space_type2 = %p \n space_wrong2 = %8b \n eol_type = %p \n eol_wrong = %8b \n address = %h \n data = %8b", get_full_name(),trans._mode,
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$display("here %s\n command_type = %p \n command = %p \n char_type = %p \n space_type1 = %p \n space_wrong1 = %8b \n space_type2 = %p \n space_wrong2 = %8b \n eol_type = %p \n eol_wrong = %8b \n address = %h \n data = %8b", get_full_name(),trans._mode,
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trans._command,
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trans._command,
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trans._chartype,
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trans._chartype,
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trans._spacetype1,
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trans._spacetype1,
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trans.space_wrong1,
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trans.space_wrong1,
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trans._spacetype2,
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trans._spacetype2,
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trans.space_wrong2,
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trans.space_wrong2,
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trans._eoltype,
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trans._eoltype,
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trans.eol_wrong,
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trans.eol_wrong,
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trans.address,
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trans.address,
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trans._data[0]);
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trans._data[0]);
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endfunction:display_content
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endfunction:display_content
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extern function void build_phase (uvm_phase phase);
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extern function void build_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern function void end_of_elaboration_phase (uvm_phase phase);
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extern function void end_of_elaboration_phase (uvm_phase phase);
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extern task run_phase (uvm_phase phase);
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extern task run_phase (uvm_phase phase);
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endclass:uart_monitor
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endclass:uart_monitor
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function void uart_monitor::build_phase (uvm_phase phase);
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function void uart_monitor::build_phase (uvm_phase phase);
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super.build_phase(phase);
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super.build_phase(phase);
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_config = uart_config::type_id::create("_config",this);
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_config = uart_config::type_id::create("_config",this);
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trans = uart_transaction::type_id::create("trans");
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trans = uart_transaction::type_id::create("trans");
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mon_scbd = new ("mon_scbd",this);
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mon_scbd = new ("mon_scbd",this);
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endfunction:build_phase
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endfunction:build_phase
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function void uart_monitor::connect_phase (uvm_phase phase);
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function void uart_monitor::connect_phase (uvm_phase phase);
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endfunction:connect_phase
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endfunction:connect_phase
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function void uart_monitor::end_of_elaboration_phase(uvm_phase phase);
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function void uart_monitor::end_of_elaboration_phase(uvm_phase phase);
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if (!uvm_config_db#(uart_config)::get(this,"","UART_CONFIGURATION",_config))
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if (!uvm_config_db#(uart_config)::get(this,"","UART_CONFIGURATION",_config))
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`uvm_fatal("NOCONFIGURATION",{"configuration instance must be set for",get_full_name(),"._config"})
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`uvm_fatal("NOCONFIGURATION",{"configuration instance must be set for",get_full_name(),"._config"})
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if (!uvm_config_db#(virtual uart_interface)::get(this,"","uart_inf",_config.uart_inf))
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if (!uvm_config_db#(virtual uart_interface)::get(this,"","uart_inf",_config.uart_inf))
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`uvm_fatal("NOINF",{"UART Interface instance must be set for",get_full_name,".uart_inf"})
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`uvm_fatal("NOINF",{"UART Interface instance must be set for",get_full_name,".uart_inf"})
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uart_inf = _config.uart_inf;
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uart_inf = _config.uart_inf;
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if(!uvm_config_db#(virtual rf_interface)::get(this,"","rf_inf",_config.rf_inf))
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if(!uvm_config_db#(virtual rf_interface)::get(this,"","rf_inf",_config.rf_inf))
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`uvm_fatal("NOINF",{"RF Interface instance must be set for",get_full_name(),".rf_inf"})
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`uvm_fatal("NOINF",{"RF Interface instance must be set for",get_full_name(),".rf_inf"})
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rf_inf = _config.rf_inf;
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rf_inf = _config.rf_inf;
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endfunction:end_of_elaboration_phase
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endfunction:end_of_elaboration_phase
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task uart_monitor::run_phase (uvm_phase phase);
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task uart_monitor::run_phase (uvm_phase phase);
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int iteration;
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int iteration;
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int command_type;
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int command_type;
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int _command;
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int _command;
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int _chartype;
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int _chartype;
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int _spacetype1;
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int _spacetype1;
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int _spacetype2;
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int _spacetype2;
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int _eoltype;
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int _eoltype;
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int _reqack;
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int _reqack;
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int _reqinc;
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int _reqinc;
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byte data_temp[$];
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iteration = 0;
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iteration = 0;
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forever
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forever
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begin
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begin
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iteration++;
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iteration++;
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//trans.reset_fields();
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uart_inf.wait_event();
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uart_inf.wait_event();
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trans.acknowledge=8'b00;
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uart_inf.capture_command(command_type,
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uart_inf.capture_command(command_type,
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_command,
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_command,
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_chartype,
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_chartype,
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_spacetype1,
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_spacetype1,
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trans.space_wrong1,
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trans.space_wrong1,
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_spacetype2,
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_spacetype2,
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trans.space_wrong2,
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trans.space_wrong2,
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_eoltype,
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_eoltype,
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trans.eol_wrong,
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trans.eol_wrong,
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trans.address,
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trans.address,
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trans._data,
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trans._data,
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trans.acknowledge,
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trans.acknowledge,
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trans.length_data,
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trans.length_data,
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_reqack,
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_reqack,
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_reqinc);
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_reqinc);
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trans._mode = mode'(command_type);
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trans._mode = mode'(command_type);
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trans._command = command'(_command);
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trans._command = command'(_command);
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trans._chartype = char_type'(_chartype);
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trans._chartype = char_type'(_chartype);
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trans._spacetype1 = space_type'(_spacetype1);
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trans._spacetype1 = space_type'(_spacetype1);
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trans._spacetype2 = space_type'(_spacetype2);
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trans._spacetype2 = space_type'(_spacetype2);
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trans._eoltype = eol_type '(_eoltype);
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trans._eoltype = eol_type '(_eoltype);
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trans._reqinc = req '(_reqinc);
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trans._reqinc = req '(_reqinc);
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trans._reqack = req '(_reqack);
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trans._reqack = req '(_reqack);
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if (trans._command == write)
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if (trans._command == write || trans._command == invalid_write)
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begin
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begin
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if (trans._mode == text)
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if (trans._mode == text || trans._mode == wrong_mode_text)
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begin
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begin
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trans._data[0] = rf_inf.read_mem_data(trans.address[7:0]);
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trans._data[0] = rf_inf.read_mem_data(trans.address);
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end
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end
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else if (trans._mode == binary)
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else if (trans._mode == binary || trans._mode == wrong_mode_bin)
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begin
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begin
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rf_inf.read_block(trans.data_length,
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rf_inf.read_block(trans.length_data,
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trans.address,
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trans.address,
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trans._data);
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trans._data);
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end
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end
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end
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end
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//display_content();
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//display_content();
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trans._id = iteration;
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mon_scbd.write(trans);
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mon_scbd.write(trans);
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end
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end
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endtask:run_phase
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endtask:run_phase
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