//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : AGENT
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// UNIT : AGENT
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART AGENT
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// TITLE : UART AGENT
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// DESCRIPTION: This
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// DESCRIPTION: This
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 10012016 FILE CREATION
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// 1 HANY SALAH 10012016 FILE CREATION
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// 2 HANY SALAH 09022016 ADD COVERAGE BLOCK
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// 2 HANY SALAH 09022016 ADD COVERAGE BLOCK
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// 3 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
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// 3 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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class uart_agent extends uvm_agent;
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class uart_agent extends uvm_agent;
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// UART Driver
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// UART Driver
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uart_driver _drv;
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uart_driver _drv;
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// UART Sequencer
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// UART Sequencer
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uvm_sequencer#(uart_transaction) _seq;
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uvm_sequencer#(uart_transaction) _seq;
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// UART Monitor
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// UART Monitor
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uart_monitor _mon;
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uart_monitor _mon;
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// UART Coverage block
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// UART Coverage block
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uart_coverage _cov;
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uart_coverage _cov;
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// TLM analysis port that is linked to driver tlm analysis port.
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// TLM analysis port that is linked to driver tlm analysis port.
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uvm_analysis_port #(uart_transaction) drv_port;
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uvm_analysis_port #(uart_transaction) drv_port;
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// TLM analysis port that is linked to monitor tlm analysis port.
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// TLM analysis port that is linked to monitor tlm analysis port.
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uvm_analysis_port #(uart_transaction) mon_port;
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uvm_analysis_port #(uart_transaction) mon_port;
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`uvm_component_utils(uart_agent)
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`uvm_component_utils(uart_agent)
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function new (string name,uvm_component parent);
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function new (string name,uvm_component parent);
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super.new(name,parent);
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super.new(name,parent);
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endfunction:new
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endfunction:new
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extern function void build_phase (uvm_phase phase);
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extern function void build_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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endclass:uart_agent
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endclass:uart_agent
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function void uart_agent::build_phase (uvm_phase phase);
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function void uart_agent::build_phase (uvm_phase phase);
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super.build_phase(phase);
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super.build_phase(phase);
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_drv = uart_driver::type_id::create("_drv",this);
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_drv = uart_driver::type_id::create("_drv",this);
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_seq = uvm_sequencer#(uart_transaction)::type_id::create("_seq",this);
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_seq = uvm_sequencer#(uart_transaction)::type_id::create("_seq",this);
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_mon = uart_monitor::type_id::create("_mon",this);
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_mon = uart_monitor::type_id::create("_mon",this);
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_cov = uart_coverage::type_id::create("_cov",this);
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_cov = uart_coverage::type_id::create("_cov",this);
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drv_port = new ("drv_port",this);
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drv_port = new ("drv_port",this);
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mon_port = new ("mon_port",this);
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mon_port = new ("mon_port",this);
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endfunction:build_phase
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endfunction:build_phase
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function void uart_agent::connect_phase (uvm_phase phase);
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function void uart_agent::connect_phase (uvm_phase phase);
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super.connect_phase(phase);
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super.connect_phase(phase);
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_drv.seq_item_port.connect(_seq.seq_item_export);
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_drv.seq_item_port.connect(_seq.seq_item_export);
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_drv.drv_scbd_cov.connect(drv_port);
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_drv.drv_scbd_cov.connect(drv_port);
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_mon.mon_scbd.connect(mon_port);
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_mon.mon_scbd.connect(mon_port);
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_mon.mon_scbd.connect(_cov.cov_mon);
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_mon.mon_scbd.connect(_cov.analysis_export);
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endfunction:connect_phase
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endfunction:connect_phase
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