//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// UART2BUS VERIFICATION
|
// UART2BUS VERIFICATION
|
//
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//
|
//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
|
// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
|
// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : TEST
|
// UNIT : TEST
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
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// TITLE : UART TEST
|
// TITLE : UART TEST
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// DESCRIPTION: THIS COMPONENT INCLUDES THE MAIN TESTS THAT WILL BE FORCED TO THE DUT. IT INCLUDES
|
// DESCRIPTION: THIS COMPONENT INCLUDES THE MAIN TESTS THAT WILL BE FORCED TO THE DUT. IT INCLUDES
|
// VIRTUAL BASE TEST FUNCTION THAT SHARES THE MOST COMMON ATTRIBUTES OF ALL TESTS.
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// VIRTUAL BASE TEST FUNCTION THAT SHARES THE MOST COMMON ATTRIBUTES OF ALL TESTS.
|
// THE TESTS IMPLEMENTED THROUGH BELOW ARE RELATED TO THE TESTBENCH SPECIFICATIONS
|
// THE TESTS IMPLEMENTED THROUGH BELOW ARE RELATED TO THE TESTBENCH SPECIFICATIONS
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// DOCUMENT. YOU CAN DOWNLOAD IT DIRECTLY THROUGH OPENCORES.COM OR FIND IT IN THE DOC
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// DOCUMENT. YOU CAN DOWNLOAD IT DIRECTLY THROUGH OPENCORES.COM OR FIND IT IN THE DOC
|
// DIRECTORY.
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// DIRECTORY.
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
|
//-------------
|
//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 10012016 FILE CREATION
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// 1 HANY SALAH 10012016 FILE CREATION
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// 2 HANY SALAH 20012016 ADD BINARY MODE TESTS AND INVALID TESTS
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// 2 HANY SALAH 20012016 ADD BINARY MODE TESTS AND INVALID TESTS
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// 3 HANY SALAH 12022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
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// 3 HANY SALAH 12022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
|
//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
|
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
|
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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|
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// The base test class that includes the uvm printer and establish the whole environment.
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// The base test class that includes the uvm printer and establish the whole environment.
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// It also responsible for setting the environment configurations described in details through the
|
// It also responsible for setting the environment configurations described in details through the
|
// testbench specifications document.
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// testbench specifications document.
|
// The environment configurations are set during the end of elaboration phase. It includes:
|
// The environment configurations are set during the end of elaboration phase. It includes:
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The active edge : The active clock edge at which, the data is changed on the UART buses.
|
// - The active edge : The active clock edge at which, the data is changed on the UART buses.
|
// It could be positive edge or negative edge.
|
// It could be positive edge or negative edge.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The start bit : Represent the sequence through which the byte is serialized; either to
|
// - The start bit : Represent the sequence through which the byte is serialized; either to
|
// start with the most significant bit or the least significant bit.
|
// start with the most significant bit or the least significant bit.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
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// - The data format : The data representation through the text commands either to be ASCII
|
// - The data format : The data representation through the text commands either to be ASCII
|
// format or ordinary binary format.
|
// format or ordinary binary format.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The number of stop: The number of stop bits sent after the latest bit of each byte. It
|
// - The number of stop: The number of stop bits sent after the latest bit of each byte. It
|
// bit(s) would be either one or two bits
|
// bit(s) would be either one or two bits
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The number of bits: The number of bits within each transferred field. It would be either
|
// - The number of bits: The number of bits within each transferred field. It would be either
|
// in the field 7 or 8 bits per field.
|
// in the field 7 or 8 bits per field.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The parity mode : The used parity type of each field. It would be either no parity bit,
|
// - The parity mode : The used parity type of each field. It would be either no parity bit,
|
// odd parity or even parity.
|
// odd parity or even parity.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The response time : Represent the maximum allowable time within which DUT should respond
|
// - The response time : Represent the maximum allowable time within which DUT should respond
|
// to the driven request.
|
// to the driven request.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
// - The false data : Enable force false data on the output port within the read command
|
// - The false data : Enable force false data on the output port within the read command
|
// enable through the both modes; text or binary.
|
// enable through the both modes; text or binary.
|
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
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virtual class uart_base_test extends uvm_test;
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virtual class uart_base_test extends uvm_test;
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|
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uart_env env;
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uart_env env;
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uvm_table_printer printer;
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uvm_table_printer printer;
|
|
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uart_config _config;
|
uart_config _config;
|
|
|
`uvm_component_utils(uart_base_test)
|
`uvm_component_utils(uart_base_test)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
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endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
|
|
env = uart_env::type_id::create("env",this);
|
env = uart_env::type_id::create("env",this);
|
|
|
_config = uart_config::type_id::create("_config",this);
|
_config = uart_config::type_id::create("_config",this);
|
|
|
uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
|
uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
|
|
|
printer = new();
|
printer = new();
|
printer.knobs.depth = 3;
|
printer.knobs.depth = 3;
|
|
env_configuration();
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
function void connect_phase (uvm_phase phase);
|
function void connect_phase (uvm_phase phase);
|
super.connect_phase(phase);
|
super.connect_phase(phase);
|
endfunction:connect_phase
|
endfunction:connect_phase
|
|
|
function void end_of_elaboration_phase (uvm_phase phase);
|
function void env_configuration ();
|
super.end_of_elaboration_phase(phase);
|
|
_config._edge = pos_edge;
|
_config._edge = pos_edge;
|
_config._start = lsb;
|
_config._start = lsb;
|
_config._datamode = ascii;
|
_config._datamode = ascii;
|
_config.num_stop_bits = 1;
|
_config.num_stop_bits = 1;
|
_config.num_of_bits = 8;
|
_config.num_of_bits = 8;
|
_config._paritymode = parity_off;
|
_config._paritymode = parity_off;
|
_config.response_time = 8680;
|
_config.response_time = 8680;
|
_config.use_false_data= no;
|
_config.use_false_data= no;
|
endfunction:end_of_elaboration_phase
|
endfunction:env_configuration
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
phase.phase_done.set_drain_time(this,5000);
|
phase.phase_done.set_drain_time(this,5000);
|
endtask:run_phase
|
endtask:run_phase
|
endclass:uart_base_test
|
endclass:uart_base_test
|
|
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// PURE TEXT MODE TESTS
|
// PURE TEXT MODE TESTS
|
//
|
//
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// This test apply thirteen successive tests of UART write request using text communication mode.
|
// This test apply thirteen successive tests of UART write request using text communication mode.
|
// Refer to test plan section in the testbench specifications document for more details.
|
// Refer to test plan section in the testbench specifications document for more details.
|
class write_text_mode extends uart_base_test;
|
class write_text_mode extends uart_base_test;
|
|
|
seq_1p1 seq1;
|
seq_1p1 seq1;
|
seq_1p2 seq2;
|
seq_1p2 seq2;
|
seq_1p3 seq3;
|
seq_1p3 seq3;
|
seq_1p4 seq4;
|
seq_1p4 seq4;
|
seq_1p5 seq5;
|
seq_1p5 seq5;
|
seq_1p6 seq6;
|
seq_1p6 seq6;
|
seq_1p7 seq7;
|
seq_1p7 seq7;
|
seq_1p8 seq8;
|
seq_1p8 seq8;
|
seq_1p9 seq9;
|
seq_1p9 seq9;
|
seq_1p10 seq10;
|
seq_1p10 seq10;
|
seq_1p11 seq11;
|
seq_1p11 seq11;
|
seq_1p12 seq12;
|
seq_1p12 seq12;
|
seq_1p13 seq13;
|
seq_1p13 seq13;
|
|
|
`uvm_component_utils(write_text_mode)
|
`uvm_component_utils(write_text_mode)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase (phase);
|
super.build_phase (phase);
|
seq1 = seq_1p1::type_id::create("seq1");
|
seq1 = seq_1p1::type_id::create("seq1");
|
seq2 = seq_1p2::type_id::create("seq2");
|
seq2 = seq_1p2::type_id::create("seq2");
|
seq3 = seq_1p3::type_id::create("seq3");
|
seq3 = seq_1p3::type_id::create("seq3");
|
seq4 = seq_1p4::type_id::create("seq4");
|
seq4 = seq_1p4::type_id::create("seq4");
|
seq5 = seq_1p5::type_id::create("seq5");
|
seq5 = seq_1p5::type_id::create("seq5");
|
seq6 = seq_1p6::type_id::create("seq6");
|
seq6 = seq_1p6::type_id::create("seq6");
|
seq7 = seq_1p7::type_id::create("seq7");
|
seq7 = seq_1p7::type_id::create("seq7");
|
seq8 = seq_1p8::type_id::create("seq8");
|
seq8 = seq_1p8::type_id::create("seq8");
|
seq9 = seq_1p9::type_id::create("seq9");
|
seq9 = seq_1p9::type_id::create("seq9");
|
seq10 = seq_1p10::type_id::create("seq10");
|
seq10 = seq_1p10::type_id::create("seq10");
|
seq11 = seq_1p11::type_id::create("seq11");
|
seq11 = seq_1p11::type_id::create("seq11");
|
seq12 = seq_1p12::type_id::create("seq12");
|
seq12 = seq_1p12::type_id::create("seq12");
|
seq13 = seq_1p13::type_id::create("seq13");
|
seq13 = seq_1p13::type_id::create("seq13");
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
seq1.start(env.agent._seq,null);
|
seq1.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq11.start(env.agent._seq,null);
|
seq11.start(env.agent._seq,null);
|
seq12.start(env.agent._seq,null);
|
seq12.start(env.agent._seq,null);
|
seq13.start(env.agent._seq,null);
|
seq13.start(env.agent._seq,null);
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
endclass:write_text_mode
|
endclass:write_text_mode
|
|
|
// This test apply thirteen successive tests of UART read request using text communication mode.
|
// This test apply thirteen successive tests of UART read request using text communication mode.
|
// Refer to test plan section in the testbench specifications document for more details.
|
// Refer to test plan section in the testbench specifications document for more details.
|
class read_text_mode extends uart_base_test;
|
class read_text_mode extends uart_base_test;
|
|
|
seq_2p1 seq1;
|
seq_2p1 seq1;
|
seq_2p2 seq2;
|
seq_2p2 seq2;
|
seq_2p3 seq3;
|
seq_2p3 seq3;
|
seq_2p4 seq4;
|
seq_2p4 seq4;
|
seq_2p5 seq5;
|
seq_2p5 seq5;
|
seq_2p6 seq6;
|
seq_2p6 seq6;
|
seq_2p7 seq7;
|
seq_2p7 seq7;
|
seq_2p8 seq8;
|
seq_2p8 seq8;
|
seq_2p9 seq9;
|
seq_2p9 seq9;
|
seq_2p10 seq10;
|
seq_2p10 seq10;
|
seq_2p11 seq11;
|
seq_2p11 seq11;
|
seq_2p12 seq12;
|
seq_2p12 seq12;
|
seq_2p13 seq13;
|
seq_2p13 seq13;
|
|
|
|
|
`uvm_component_utils(read_text_mode)
|
`uvm_component_utils(read_text_mode)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
seq1 = seq_2p1::type_id::create("seq1");
|
seq1 = seq_2p1::type_id::create("seq1");
|
seq2 = seq_2p2::type_id::create("seq2");
|
seq2 = seq_2p2::type_id::create("seq2");
|
seq3 = seq_2p3::type_id::create("seq3");
|
seq3 = seq_2p3::type_id::create("seq3");
|
seq4 = seq_2p4::type_id::create("seq4");
|
seq4 = seq_2p4::type_id::create("seq4");
|
seq5 = seq_2p5::type_id::create("seq5");
|
seq5 = seq_2p5::type_id::create("seq5");
|
seq6 = seq_2p6::type_id::create("seq6");
|
seq6 = seq_2p6::type_id::create("seq6");
|
seq7 = seq_2p7::type_id::create("seq7");
|
seq7 = seq_2p7::type_id::create("seq7");
|
seq8 = seq_2p8::type_id::create("seq8");
|
seq8 = seq_2p8::type_id::create("seq8");
|
seq9 = seq_2p9::type_id::create("seq9");
|
seq9 = seq_2p9::type_id::create("seq9");
|
seq10 = seq_2p10::type_id::create("seq10");
|
seq10 = seq_2p10::type_id::create("seq10");
|
seq11 = seq_2p11::type_id::create("seq11");
|
seq11 = seq_2p11::type_id::create("seq11");
|
seq12 = seq_2p12::type_id::create("seq12");
|
seq12 = seq_2p12::type_id::create("seq12");
|
seq13 = seq_2p13::type_id::create("seq13");
|
seq13 = seq_2p13::type_id::create("seq13");
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
seq1.start(env.agent._seq,null);
|
seq1.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq11.start(env.agent._seq,null);
|
seq11.start(env.agent._seq,null);
|
seq12.start(env.agent._seq,null);
|
seq12.start(env.agent._seq,null);
|
seq13.start(env.agent._seq,null);
|
seq13.start(env.agent._seq,null);
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
endclass:read_text_mode
|
endclass:read_text_mode
|
|
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// PURE BINARY MODE TESTS
|
// PURE BINARY MODE TESTS
|
//
|
//
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// This test apply six successive tests of UART nop request using binary communication mode.
|
// This test apply six successive tests of UART nop request using binary communication mode.
|
// Refer to test plan section in the testbench specifications document for more details.
|
// Refer to test plan section in the testbench specifications document for more details.
|
class nop_command_mode extends uart_base_test;
|
class nop_command_mode extends uart_base_test;
|
|
|
seq_3p1 seq1;
|
seq_3p1 seq1;
|
seq_3p2 seq2;
|
seq_3p2 seq2;
|
seq_3p3 seq3;
|
seq_3p3 seq3;
|
seq_4p1 seq4;
|
seq_4p1 seq4;
|
seq_4p2 seq5;
|
seq_4p2 seq5;
|
seq_4p3 seq6;
|
seq_4p3 seq6;
|
|
|
`uvm_component_utils(nop_command_mode)
|
`uvm_component_utils(nop_command_mode)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
seq1 = seq_3p1::type_id::create("seq1");
|
seq1 = seq_3p1::type_id::create("seq1");
|
seq2 = seq_3p2::type_id::create("seq2");
|
seq2 = seq_3p2::type_id::create("seq2");
|
seq3 = seq_3p3::type_id::create("seq3");
|
seq3 = seq_3p3::type_id::create("seq3");
|
seq4 = seq_4p1::type_id::create("seq4");
|
seq4 = seq_4p1::type_id::create("seq4");
|
seq5 = seq_4p2::type_id::create("seq5");
|
seq5 = seq_4p2::type_id::create("seq5");
|
seq6 = seq_4p3::type_id::create("seq6");
|
seq6 = seq_4p3::type_id::create("seq6");
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
task run_phase(uvm_phase phase);
|
task run_phase(uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
seq1.start(env.agent._seq,null);
|
seq1.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
endclass:nop_command_mode
|
endclass:nop_command_mode
|
|
|
|
|
// This test apply ten successive tests of UART write request using binary communication mode.
|
// This test apply ten successive tests of UART write request using binary communication mode.
|
// Refer to test plan section in the testbench specifications document for more details.
|
// Refer to test plan section in the testbench specifications document for more details.
|
class write_command_mode extends uart_base_test;
|
class write_command_mode extends uart_base_test;
|
|
|
seq_5p1 seq1;
|
seq_5p1 seq1;
|
seq_5p2 seq2;
|
seq_5p2 seq2;
|
seq_5p3 seq3;
|
seq_5p3 seq3;
|
seq_5p4 seq4;
|
seq_5p4 seq4;
|
seq_5p5 seq5;
|
seq_5p5 seq5;
|
seq_5p6 seq6;
|
seq_5p6 seq6;
|
seq_5p7 seq7;
|
seq_5p7 seq7;
|
seq_5p8 seq8;
|
seq_5p8 seq8;
|
seq_5p9 seq9;
|
seq_5p9 seq9;
|
seq_5p10 seq10;
|
seq_5p10 seq10;
|
|
|
`uvm_component_utils(write_command_mode)
|
`uvm_component_utils(write_command_mode)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
seq1 = seq_5p1::type_id::create("seq1");
|
seq1 = seq_5p1::type_id::create("seq1");
|
seq2 = seq_5p2::type_id::create("seq2");
|
seq2 = seq_5p2::type_id::create("seq2");
|
seq3 = seq_5p3::type_id::create("seq3");
|
seq3 = seq_5p3::type_id::create("seq3");
|
seq4 = seq_5p4::type_id::create("seq4");
|
seq4 = seq_5p4::type_id::create("seq4");
|
seq5 = seq_5p5::type_id::create("seq5");
|
seq5 = seq_5p5::type_id::create("seq5");
|
seq6 = seq_5p6::type_id::create("seq6");
|
seq6 = seq_5p6::type_id::create("seq6");
|
seq7 = seq_5p7::type_id::create("seq7");
|
seq7 = seq_5p7::type_id::create("seq7");
|
seq8 = seq_5p8::type_id::create("seq8");
|
seq8 = seq_5p8::type_id::create("seq8");
|
seq9 = seq_5p9::type_id::create("seq9");
|
seq9 = seq_5p9::type_id::create("seq9");
|
seq10 = seq_5p10::type_id::create("seq10");
|
seq10 = seq_5p10::type_id::create("seq10");
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
uvm_test_done.set_drain_time(this,5000);
|
uvm_test_done.set_drain_time(this,5000);
|
//seq1.start(env.agent._seq,null);
|
//seq1.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
endclass: write_command_mode
|
endclass: write_command_mode
|
|
|
|
|
// This test apply ten successive tests of UART read request using binary communication mode.
|
// This test apply ten successive tests of UART read request using binary communication mode.
|
// Refer to test plan section in the testbench specifications document for more details.
|
// Refer to test plan section in the testbench specifications document for more details.
|
class read_command_mode extends uart_base_test;
|
class read_command_mode extends uart_base_test;
|
|
|
seq_6p1 seq1;
|
seq_6p1 seq1;
|
seq_6p2 seq2;
|
seq_6p2 seq2;
|
seq_6p3 seq3;
|
seq_6p3 seq3;
|
seq_6p4 seq4;
|
seq_6p4 seq4;
|
seq_6p5 seq5;
|
seq_6p5 seq5;
|
seq_6p6 seq6;
|
seq_6p6 seq6;
|
seq_6p7 seq7;
|
seq_6p7 seq7;
|
seq_6p8 seq8;
|
seq_6p8 seq8;
|
seq_6p9 seq9;
|
seq_6p9 seq9;
|
seq_6p10 seq10;
|
seq_6p10 seq10;
|
|
|
`uvm_component_utils(read_command_mode)
|
`uvm_component_utils(read_command_mode)
|
|
|
function new (string name,uvm_component parent);
|
function new (string name,uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
seq1 = seq_6p1::type_id::create("seq1");
|
seq1 = seq_6p1::type_id::create("seq1");
|
seq2 = seq_6p2::type_id::create("seq2");
|
seq2 = seq_6p2::type_id::create("seq2");
|
seq3 = seq_6p3::type_id::create("seq3");
|
seq3 = seq_6p3::type_id::create("seq3");
|
seq4 = seq_6p4::type_id::create("seq4");
|
seq4 = seq_6p4::type_id::create("seq4");
|
seq5 = seq_6p5::type_id::create("seq5");
|
seq5 = seq_6p5::type_id::create("seq5");
|
seq6 = seq_6p6::type_id::create("seq6");
|
seq6 = seq_6p6::type_id::create("seq6");
|
seq7 = seq_6p7::type_id::create("seq7");
|
seq7 = seq_6p7::type_id::create("seq7");
|
seq8 = seq_6p8::type_id::create("seq8");
|
seq8 = seq_6p8::type_id::create("seq8");
|
seq9 = seq_6p9::type_id::create("seq9");
|
seq9 = seq_6p9::type_id::create("seq9");
|
seq10 = seq_6p10::type_id::create("seq10");
|
seq10 = seq_6p10::type_id::create("seq10");
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
|
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
//seq1.start(env.agent._seq,null);
|
//seq1.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
endclass:read_command_mode
|
endclass:read_command_mode
|
|
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
//
|
//
|
// COMBINED COMMAND TESTS
|
// COMBINED COMMAND TESTS
|
//
|
//
|
//-------------------------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------------------------
|
|
|
// this test randomly apply series of 100 text mode commands. They would be either read or write
|
// this test randomly apply series of 100 text mode commands. They would be either read or write
|
// sequences described in text mode tests in the testbench specifications document.
|
// sequences described in text mode tests in the testbench specifications document.
|
class text_mode_test extends uart_base_test;
|
class text_mode_test extends uart_base_test;
|
|
|
rand int unsigned command_number;
|
rand int unsigned command_number;
|
|
|
seq_1p1 seq1;
|
seq_1p1 seq1;
|
seq_1p2 seq2;
|
seq_1p2 seq2;
|
seq_1p3 seq3;
|
seq_1p3 seq3;
|
seq_1p4 seq4;
|
seq_1p4 seq4;
|
seq_1p5 seq5;
|
seq_1p5 seq5;
|
seq_1p6 seq6;
|
seq_1p6 seq6;
|
seq_1p7 seq7;
|
seq_1p7 seq7;
|
seq_1p8 seq8;
|
seq_1p8 seq8;
|
seq_1p9 seq9;
|
seq_1p9 seq9;
|
seq_1p10 seq10;
|
seq_1p10 seq10;
|
seq_1p11 seq11;
|
seq_1p11 seq11;
|
seq_1p12 seq12;
|
seq_1p12 seq12;
|
seq_1p13 seq13;
|
seq_1p13 seq13;
|
|
|
|
|
seq_2p1 seq14;
|
seq_2p1 seq14;
|
seq_2p2 seq15;
|
seq_2p2 seq15;
|
seq_2p3 seq16;
|
seq_2p3 seq16;
|
seq_2p4 seq17;
|
seq_2p4 seq17;
|
seq_2p5 seq18;
|
seq_2p5 seq18;
|
seq_2p6 seq19;
|
seq_2p6 seq19;
|
seq_2p7 seq20;
|
seq_2p7 seq20;
|
seq_2p8 seq21;
|
seq_2p8 seq21;
|
seq_2p9 seq22;
|
seq_2p9 seq22;
|
seq_2p10 seq23;
|
seq_2p10 seq23;
|
seq_2p11 seq24;
|
seq_2p11 seq24;
|
seq_2p12 seq25;
|
seq_2p12 seq25;
|
seq_2p13 seq26;
|
seq_2p13 seq26;
|
|
|
`uvm_component_utils(text_mode_test)
|
`uvm_component_utils(text_mode_test)
|
|
|
constraint limit {
|
constraint limit {
|
command_number inside {[1:26]};
|
command_number inside {[1:26]};
|
}
|
}
|
|
|
function new (string name , uvm_component parent);
|
function new (string name , uvm_component parent);
|
super.new(name,parent);
|
super.new(name,parent);
|
endfunction:new
|
endfunction:new
|
|
|
function void build_phase (uvm_phase phase);
|
function void build_phase (uvm_phase phase);
|
super.build_phase(phase);
|
super.build_phase(phase);
|
seq1 = seq_1p1::type_id::create("seq1");
|
seq1 = seq_1p1::type_id::create("seq1");
|
seq2 = seq_1p2::type_id::create("seq2");
|
seq2 = seq_1p2::type_id::create("seq2");
|
seq3 = seq_1p3::type_id::create("seq3");
|
seq3 = seq_1p3::type_id::create("seq3");
|
seq4 = seq_1p4::type_id::create("seq4");
|
seq4 = seq_1p4::type_id::create("seq4");
|
seq5 = seq_1p5::type_id::create("seq5");
|
seq5 = seq_1p5::type_id::create("seq5");
|
seq6 = seq_1p6::type_id::create("seq6");
|
seq6 = seq_1p6::type_id::create("seq6");
|
seq7 = seq_1p7::type_id::create("seq7");
|
seq7 = seq_1p7::type_id::create("seq7");
|
seq8 = seq_1p8::type_id::create("seq8");
|
seq8 = seq_1p8::type_id::create("seq8");
|
seq9 = seq_1p9::type_id::create("seq9");
|
seq9 = seq_1p9::type_id::create("seq9");
|
seq10 = seq_1p10::type_id::create("seq10");
|
seq10 = seq_1p10::type_id::create("seq10");
|
seq11 = seq_1p11::type_id::create("seq11");
|
seq11 = seq_1p11::type_id::create("seq11");
|
seq12 = seq_1p12::type_id::create("seq12");
|
seq12 = seq_1p12::type_id::create("seq12");
|
seq13 = seq_1p13::type_id::create("seq13");
|
seq13 = seq_1p13::type_id::create("seq13");
|
seq14 = seq_2p1::type_id::create("seq14");
|
seq14 = seq_2p1::type_id::create("seq14");
|
seq15 = seq_2p2::type_id::create("seq15");
|
seq15 = seq_2p2::type_id::create("seq15");
|
seq16 = seq_2p3::type_id::create("seq16");
|
seq16 = seq_2p3::type_id::create("seq16");
|
seq17 = seq_2p4::type_id::create("seq17");
|
seq17 = seq_2p4::type_id::create("seq17");
|
seq18 = seq_2p5::type_id::create("seq18");
|
seq18 = seq_2p5::type_id::create("seq18");
|
seq19 = seq_2p6::type_id::create("seq19");
|
seq19 = seq_2p6::type_id::create("seq19");
|
seq20 = seq_2p7::type_id::create("seq20");
|
seq20 = seq_2p7::type_id::create("seq20");
|
seq21 = seq_2p8::type_id::create("seq21");
|
seq21 = seq_2p8::type_id::create("seq21");
|
seq22 = seq_2p9::type_id::create("seq22");
|
seq22 = seq_2p9::type_id::create("seq22");
|
seq23 = seq_2p10::type_id::create("seq23");
|
seq23 = seq_2p10::type_id::create("seq23");
|
seq24 = seq_2p11::type_id::create("seq24");
|
seq24 = seq_2p11::type_id::create("seq24");
|
seq25 = seq_2p12::type_id::create("seq25");
|
seq25 = seq_2p12::type_id::create("seq25");
|
seq26 = seq_2p13::type_id::create("seq26");
|
seq26 = seq_2p13::type_id::create("seq26");
|
endfunction:build_phase
|
endfunction:build_phase
|
|
|
task run_phase (uvm_phase phase);
|
task run_phase (uvm_phase phase);
|
super.run_phase(phase);
|
super.run_phase(phase);
|
phase.raise_objection(this);
|
phase.raise_objection(this);
|
repeat (100)
|
repeat (100)
|
begin
|
begin
|
randomize();
|
randomize();
|
case (command_number)
|
case (command_number)
|
1:
|
1:
|
begin
|
begin
|
seq1.start(env.agent._seq,null);
|
seq1.start(env.agent._seq,null);
|
end
|
end
|
2:
|
2:
|
begin
|
begin
|
seq2.start(env.agent._seq,null);
|
seq2.start(env.agent._seq,null);
|
end
|
end
|
3:
|
3:
|
begin
|
begin
|
seq3.start(env.agent._seq,null);
|
seq3.start(env.agent._seq,null);
|
end
|
end
|
4:
|
4:
|
begin
|
begin
|
seq4.start(env.agent._seq,null);
|
seq4.start(env.agent._seq,null);
|
end
|
end
|
5:
|
5:
|
begin
|
begin
|
seq5.start(env.agent._seq,null);
|
seq5.start(env.agent._seq,null);
|
end
|
end
|
6:
|
6:
|
begin
|
begin
|
seq6.start(env.agent._seq,null);
|
seq6.start(env.agent._seq,null);
|
end
|
end
|
7:
|
7:
|
begin
|
begin
|
seq7.start(env.agent._seq,null);
|
seq7.start(env.agent._seq,null);
|
end
|
end
|
8:
|
8:
|
begin
|
begin
|
seq8.start(env.agent._seq,null);
|
seq8.start(env.agent._seq,null);
|
end
|
end
|
9:
|
9:
|
begin
|
begin
|
seq9.start(env.agent._seq,null);
|
seq9.start(env.agent._seq,null);
|
end
|
end
|
10:
|
10:
|
begin
|
begin
|
seq10.start(env.agent._seq,null);
|
seq10.start(env.agent._seq,null);
|
end
|
end
|
11:
|
11:
|
begin
|
begin
|
seq11.start(env.agent._seq,null);
|
seq11.start(env.agent._seq,null);
|
end
|
end
|
12:
|
12:
|
begin
|
begin
|
seq12.start(env.agent._seq,null);
|
seq12.start(env.agent._seq,null);
|
end
|
end
|
13:
|
13:
|
begin
|
begin
|
seq13.start(env.agent._seq,null);
|
seq13.start(env.agent._seq,null);
|
end
|
end
|
14:
|
14:
|
begin
|
begin
|
seq14.start(env.agent._seq,null);
|
seq14.start(env.agent._seq,null);
|
end
|
end
|
15:
|
15:
|
begin
|
begin
|
seq15.start(env.agent._seq,null);
|
seq15.start(env.agent._seq,null);
|
end
|
end
|
16:
|
16:
|
begin
|
begin
|
seq16.start(env.agent._seq,null);
|
seq16.start(env.agent._seq,null);
|
end
|
end
|
17:
|
17:
|
begin
|
begin
|
seq17.start(env.agent._seq,null);
|
seq17.start(env.agent._seq,null);
|
end
|
end
|
18:
|
18:
|
begin
|
begin
|
seq18.start(env.agent._seq,null);
|
seq18.start(env.agent._seq,null);
|
end
|
end
|
19:
|
19:
|
begin
|
begin
|
seq19.start(env.agent._seq,null);
|
seq19.start(env.agent._seq,null);
|
end
|
end
|
20:
|
20:
|
begin
|
begin
|
seq20.start(env.agent._seq,null);
|
seq20.start(env.agent._seq,null);
|
end
|
end
|
21:
|
21:
|
begin
|
begin
|
seq21.start(env.agent._seq,null);
|
seq21.start(env.agent._seq,null);
|
end
|
end
|
22:
|
22:
|
begin
|
begin
|
seq22.start(env.agent._seq,null);
|
seq22.start(env.agent._seq,null);
|
end
|
end
|
23:
|
23:
|
begin
|
begin
|
seq23.start(env.agent._seq,null);
|
seq23.start(env.agent._seq,null);
|
end
|
end
|
24:
|
24:
|
begin
|
begin
|
seq24.start(env.agent._seq,null);
|
seq24.start(env.agent._seq,null);
|
end
|
end
|
25:
|
25:
|
begin
|
begin
|
seq25.start(env.agent._seq,null);
|
seq25.start(env.agent._seq,null);
|
end
|
end
|
26:
|
26:
|
begin
|
begin
|
seq26.start(env.agent._seq,null);
|
seq26.start(env.agent._seq,null);
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
`uvm_fatal("OUT OF RANGE","Command Number is Out of Range")
|
`uvm_fatal("OUT OF RANGE","Command Number is Out of Range")
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
phase.drop_objection(this);
|
phase.drop_objection(this);
|
endtask:run_phase
|
endtask:run_phase
|
|
|