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[/] [uart8systemc/] [trunk/] [work/] [sc_uart.so] - Diff between revs 4 and 6

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Rev 4 Rev 6 
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terfaceEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE13get_interfaceEv_ZN7sc_core5sc_inIjE5vbindERNS_12sc_interfaceE_ZN7sc_core5sc_inIjE5vbindERNS_12sc_port_baseE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE13add_interfaceEPNS_12sc_interfaceE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE15interface_countEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE11if_typenameEv_ZN7sc_core5sc_inIjE18end_of_elaborationEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE14make_sensitiveEPNS_17sc_thread_processEPNS_15sc_event_finderE_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE14make_sensitiveEPNS_17sc_method_processEPNS_15sc_event_finderE_ZN7sc_core5sc_inIjE4bindERNS_15sc_signal_in_ifIjEE_ZN7sc_core5sc_inIjE4bindERNS_9sc_port_bINS_15sc_signal_in_ifIjEEEE_ZN7sc_core5sc_inIjE4bindERNS_7sc_portINS_15sc_signal_in_ifIjEELi1ELNS_14sc_port_policyE0EEE_ZN7sc_core5sc_inIjE4bindERNS_7sc_portINS_18sc_signal_inout_ifIjEELi1ELNS_14sc_port_policyE0EEE_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIjEELi1ELNS_14sc_port_policyE0EEE_ZNK7sc_core7sc_portINS_15sc_signal_in_ifIjEELi1ELNS_14sc_port_policyE0EE4kindEv_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE5vbindERNS_12sc_interfaceE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE5vbindERNS_12sc_port_baseE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE4bindERS2__ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEE4bindERS3__ZTIN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEEE_ZTIN7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEEE_ZN7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEED1Ev_ZN7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEED0Ev_ZNK7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEE10find_eventEPNS_12sc_interfaceE_ZTIN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEE_ZNK7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EE4kindEv_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE13get_interfaceEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE13get_interfaceEv_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE5vbindERNS_12sc_interfaceE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE5vbindERNS_12sc_port_baseE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE13add_interfaceEPNS_12sc_interfaceE_ZN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE15interface_countEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE11if_typenameEv_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE14make_sensitiveEPNS_17sc_thread_processEPNS_15sc_event_finderE_ZNK7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEE14make_sensitiveEPNS_17sc_method_processEPNS_15sc_event_finderE_ZTIN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEE_ZTIN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEE_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE13register_portERNS_12sc_port_baseEPKc_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE13default_eventEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE19value_changed_eventEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE13posedge_eventEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE13negedge_eventEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4readEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE12get_data_refEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE5eventEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE7posedgeEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE7negedgeEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE8is_resetEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE17get_writer_policyEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE5traceEPNS_13sc_trace_fileE_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE5printERSo_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4dumpERSo_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4kindEv_ZN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE6updateEv_ZNK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE8is_clockEv_ZThn8_NK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE17get_writer_policyEv_ZThn16_NK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE5printERSo_ZThn16_NK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4dumpERSo_ZThn16_NK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE5traceEPNS_13sc_trace_fileE_ZThn16_NK7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE4kindEv_ZThn16_N7sc_core9sc_signalIbLNS_16sc_writer_policyE0EE6updateEv_ZTIN7sc_core18sc_signal_inout_ifIbEE_ZNK7sc_core18sc_signal_write_ifIbE17get_writer_policyEv_ZTIN7sc_core15sc_signal_in_ifIbEE_ZTIN7sc_core18sc_signal_write_ifIbEE_ZTTN7sc_core18sc_signal_write_ifIbEE_ZTTN7sc_core15sc_signal_in_ifIbEE_ZTIN7sc_core18sc_process_monitorE_ZTS11sc_UART_top_ZTVN10__cxxabiv120__si_class_type_infoE_ZTIN7sc_core9sc_moduleE_ZTSN7sc_core9sc_signalIjLNS_16sc_writer_policyE0EEE_ZTVN10__cxxabiv121__vmi_class_type_infoE_ZTIN7sc_core15sc_prim_channelE_ZTIN7sc_core22sc_writer_policy_checkILNS_16sc_writer_policyE0EEE_ZTSN7sc_core18sc_signal_inout_ifIjEE_ZTSN7sc_core18sc_signal_write_ifIjEE_ZTIN7sc_core12sc_interfaceE_ZTSN7sc_core15sc_signal_in_ifIjEE_ZTS7UART_SC_ZTSN5sc_dt7sc_uintILi11EEE_ZTIN5sc_dt12sc_uint_baseE_ZTSN5sc_dt7sc_uintILi4EEE_ZTSN5s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STARTING TX_TRANSMIT()DATA IS NOT EQUAL ON TIME DATA TX :  DATA RX : DATA PARITY IS NOT EQUAL : DATA IS EQUAL ON TIME DATA PARITY IS EQUALRX_RECEIVETX_TRANSMITSHOW_RESULTSclkrxtxresetDUTSC_CTOR(sc_UART_top)sc_UART_topport is not boundvector::_M_insert_aux    @@@@4 $$$$kernel_event$$$$__value_changed_event     name =     value = new value = sc_signalsc_out/home/felipe/Downloads/PROGRAMAS/systemc-2.3.0/include/sysc/communication/sc_port.hiface != 0interface already bound to portiface_p != 0sc_inoutsc_portsc_in_posedge_event_negedge_eventvoid sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_in_if]void sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_inout_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_inout_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_inout_if]void sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_in_if]void sc_core::sc_process_b::reference_increment()PPQ7RR}S TTfU     VVOXX(YYZZ[[\~\^11sc_UART_topN7sc_core9sc_signalIjLNS_16sc_writer_policyE0EEEN7sc_core18sc_signal_inout_ifIjEEN7sc_core18sc_signal_write_ifIjEEN7sc_core15sc_signal_in_ifIjEE7UART_SCN5sc_dt7sc_uintILi11EEEN5sc_dt7sc_uintILi4EEEN5sc_dt7sc_uintILi1EEEN5sc_dt7sc_uintILi8EEEN7sc_core6sc_outIjEEN7sc_core8sc_inoutIjEEN7sc_core7sc_portINS_18sc_signal_inout_ifIjEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_18sc_signal_inout_ifIjEEEEN7sc_core5sc_inIjEEN7sc_core7sc_portINS_15sc_signal_in_ifIjEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEEE10Control_SCN7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEEEN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEEN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEEN7sc_core18sc_signal_inout_ifIbEEN7sc_core18sc_signal_write_ifIbEEN7sc_core15sc_signal_in_ifIbEEN7sc_core18sc_process_monitorEN7sc_core22sc_writer_policy_checkILNS_16sc_writer_policyE0EEEN7sc_core27sc_writer_policy_check_portEN7sc_core28sc_writer_policy_check_writeE;h,t
 
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STARTING TX_TRANSMIT()DATA IS NOT EQUAL ON TIME DATA TX :  DATA RX : DATA PARITY IS NOT EQUAL : DATA IS EQUAL ON TIME DATA PARITY IS EQUALRX_RECEIVETX_TRANSMITSHOW_RESULTSclkrxtxresetDUTSC_CTOR(sc_UART_top)sc_UART_topport is not boundvector::_M_insert_aux    @@@@4 $$$$kernel_event$$$$__value_changed_event     name =     value = new value = sc_signalsc_out/home/felipe/Downloads/PROGRAMAS/systemc-2.3.0/include/sysc/communication/sc_port.hiface != 0interface already bound to portiface_p != 0sc_inoutsc_portsc_in_posedge_event_negedge_eventvoid sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_in_if]void sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_inout_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_inout_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_inout_if]void sc_core::sc_port_b::make_sensitive(sc_core::sc_method_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_method_handle = sc_core::sc_method_process*]void sc_core::sc_port_b::make_sensitive(sc_core::sc_thread_handle, sc_core::sc_event_finder*) const [with IF = sc_core::sc_signal_in_if; sc_core::sc_thread_handle = sc_core::sc_thread_process*]void sc_core::sc_port_b::add_interface(sc_core::sc_interface*) [with IF = sc_core::sc_signal_in_if]void sc_core::sc_process_b::reference_increment()PPQCRRS,TTrUVV[XX4YY(ZZ[[\\*^11sc_UART_topN7sc_core9sc_signalIjLNS_16sc_writer_policyE0EEEN7sc_core18sc_signal_inout_ifIjEEN7sc_core18sc_signal_write_ifIjEEN7sc_core15sc_signal_in_ifIjEE7UART_SCN5sc_dt7sc_uintILi11EEEN5sc_dt7sc_uintILi4EEEN5sc_dt7sc_uintILi1EEEN5sc_dt7sc_uintILi8EEEN7sc_core6sc_outIjEEN7sc_core8sc_inoutIjEEN7sc_core7sc_portINS_18sc_signal_inout_ifIjEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_18sc_signal_inout_ifIjEEEEN7sc_core5sc_inIjEEN7sc_core7sc_portINS_15sc_signal_in_ifIjEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_15sc_signal_in_ifIjEEEE10Control_SCN7sc_core17sc_event_finder_tINS_15sc_signal_in_ifIbEEEEN7sc_core7sc_portINS_15sc_signal_in_ifIbEELi1ELNS_14sc_port_policyE0EEEN7sc_core9sc_port_bINS_15sc_signal_in_ifIbEEEEN7sc_core9sc_signalIbLNS_16sc_writer_policyE0EEEN7sc_core18sc_signal_inout_ifIbEEN7sc_core18sc_signal_write_ifIbEEN7sc_core15sc_signal_in_ifIbEEN7sc_core18sc_process_monitorEN7sc_core22sc_writer_policy_checkILNS_16sc_writer_policyE0EEEN7sc_core27sc_writer_policy_check_portEN7sc_core28sc_writer_policy_check_writeE;h,7|V7p7&8X88,8L8l899999\=P:We:w::::,:L:l;";,;R;h;;,;L;l<D<<6=u==,=lH>^>~>>>?4"?T^?t???0@B@l@4@T@tAAA
 
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