--! Top wishbone Master to test the uart_wishbone_slave
|
--! Top wishbone Master to test the uart_wishbone_slave
|
library ieee;
|
library ieee;
|
USE ieee.std_logic_1164.ALL;
|
USE ieee.std_logic_1164.ALL;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
--! Use CPU Definitions package
|
--! Use CPU Definitions package
|
use work.pkgDefinitions.all;
|
use work.pkgDefinitions.all;
|
|
|
entity SERIALMASTER is
|
entity SERIALMASTER is
|
port(
|
port(
|
-- WISHBONE Signals
|
-- WISHBONE Signals
|
ACK_I: in std_logic;
|
ACK_I: in std_logic;
|
ADR_O: out std_logic_vector( 1 downto 0 );
|
ADR_O: out std_logic_vector( 1 downto 0 );
|
CLK_I: in std_logic;
|
CLK_I: in std_logic;
|
CYC_O: out std_logic;
|
CYC_O: out std_logic;
|
DAT_I: in std_logic_vector( 31 downto 0 );
|
DAT_I: in std_logic_vector( 31 downto 0 );
|
DAT_O: out std_logic_vector( 31 downto 0 );
|
DAT_O: out std_logic_vector( 31 downto 0 );
|
RST_I: in std_logic;
|
RST_I: in std_logic;
|
SEL_O: out std_logic;
|
SEL_O: out std_logic;
|
STB_O: out std_logic;
|
STB_O: out std_logic;
|
WE_O: out std_logic;
|
WE_O: out std_logic;
|
|
|
-- NON-WISHBONE Signals
|
-- NON-WISHBONE Signals
|
byte_rec : out std_logic_vector(7 downto 0)
|
byte_rec : out std_logic_vector(7 downto 0)
|
);
|
);
|
|
|
end SERIALMASTER;
|
end SERIALMASTER;
|
|
|
architecture Behavioral of SERIALMASTER is
|
architecture Behavioral of SERIALMASTER is
|
signal masterSerialStates : testMaster;
|
signal masterSerialStates : testMaster;
|
signal byteIncome : std_logic_vector(7 downto 0);
|
signal byteIncome : std_logic_vector(7 downto 0);
|
begin
|
begin
|
|
|
process (CLK_I)
|
process (CLK_I)
|
variable contWait : integer range 0 to 50000000;
|
variable contWait : integer range 0 to 50000000;
|
|
variable cycles2Wait : integer range 0 to 50000000;
|
variable nextState: testMaster;
|
variable nextState: testMaster;
|
begin
|
begin
|
if rising_edge(CLK_I) then
|
if rising_edge(CLK_I) then
|
if RST_I = '1' then
|
if RST_I = '1' then
|
masterSerialStates <= idle;
|
masterSerialStates <= idle;
|
nextState := idle;
|
nextState := idle;
|
contWait := 0;
|
contWait := 0;
|
byteIncome <= (others => '0');
|
cycles2Wait := 25000000;
|
|
byteIncome <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@';
|
else
|
else
|
case masterSerialStates is
|
case masterSerialStates is
|
when idle =>
|
when idle =>
|
masterSerialStates <= config_clock;
|
masterSerialStates <= config_clock;
|
nextState := idle;
|
nextState := idle;
|
|
|
when config_clock =>
|
when config_clock =>
|
nextState := config_baud;
|
nextState := config_baud;
|
ADR_O <= "00";
|
ADR_O <= "00";
|
WE_O <= '1';
|
WE_O <= '1';
|
STB_O <= '1';
|
STB_O <= '1';
|
DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz
|
DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz
|
if ACK_I = '1' then
|
if ACK_I = '1' then
|
-- Byte received wait some cycles to continue
|
-- Byte received wait some cycles to continue
|
masterSerialStates <= wait_cycles;
|
masterSerialStates <= wait_cycles;
|
byte_rec <= "00000001";
|
byte_rec <= "00000001";
|
end if;
|
end if;
|
|
|
when config_baud =>
|
when config_baud =>
|
nextState := send_byte;
|
nextState := send_byte;
|
ADR_O <= "01";
|
ADR_O <= "01";
|
WE_O <= '1';
|
WE_O <= '1';
|
STB_O <= '1';
|
STB_O <= '1';
|
DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps
|
DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps
|
if ACK_I = '1' then
|
if ACK_I = '1' then
|
-- Byte received wait some cycles to continue
|
-- Byte received wait some cycles to continue
|
masterSerialStates <= wait_cycles;
|
masterSerialStates <= wait_cycles;
|
byte_rec <= "00000010";
|
byte_rec <= "00000010";
|
end if;
|
end if;
|
|
|
when send_byte =>
|
when send_byte =>
|
nextState := receive_byte;
|
nextState := receive_byte;
|
ADR_O <= "10";
|
ADR_O <= "10";
|
WE_O <= '1';
|
WE_O <= '1';
|
STB_O <= '1';
|
STB_O <= '1';
|
--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
|
--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
|
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
|
DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
|
if ACK_I = '1' then
|
if ACK_I = '1' then
|
-- Byte received wait some cycles to continue
|
-- Byte received wait some cycles to continue
|
masterSerialStates <= wait_cycles;
|
masterSerialStates <= wait_cycles;
|
byte_rec <= "00000100";
|
cycles2Wait := 7000000;
|
end if;
|
end if;
|
|
|
when receive_byte =>
|
when receive_byte =>
|
nextState := send_byte;
|
nextState := send_byte;
|
ADR_O <= "11";
|
ADR_O <= "11";
|
WE_O <= '0';
|
WE_O <= '0';
|
STB_O <= '1';
|
STB_O <= '1';
|
if ACK_I = '1' then
|
if ACK_I = '1' then
|
-- Byte received wait some cycles to continue
|
-- Byte received wait some cycles to continue
|
masterSerialStates <= wait_cycles;
|
masterSerialStates <= wait_cycles;
|
byte_rec <= DAT_I(7 downto 0);
|
byte_rec <= DAT_I(7 downto 0);
|
byteIncome <= DAT_I(7 downto 0);
|
byteIncome <= DAT_I(7 downto 0);
|
--byte_rec <= "00001000";
|
cycles2Wait := 7000000;
|
end if;
|
end if;
|
|
|
when wait_cycles =>
|
when wait_cycles =>
|
-- wait some cycles (90)
|
-- wait some cycles (90)
|
if contWait < 25000000 then
|
if contWait < cycles2Wait then
|
contWait := contWait + 1;
|
contWait := contWait + 1;
|
STB_O <= '0';
|
STB_O <= '0';
|
else
|
else
|
contWait := 0;
|
contWait := 0;
|
masterSerialStates <= nextState;
|
masterSerialStates <= nextState;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
