--! Top wishbone Master to test the uart_wishbone_slave
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--! @file
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--! @brief Top wishbone Master to test the uart_wishbone_slave
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library ieee;
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library ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity SERIALMASTER is
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entity SERIALMASTER is
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port(
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port(
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-- WISHBONE Signals
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-- WISHBONE Signals
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ACK_I: in std_logic;
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ACK_I: in std_logic; --! Ack input
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ADR_O: out std_logic_vector( 1 downto 0 );
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ADR_O: out std_logic_vector( 1 downto 0 ); --! Address output
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CLK_I: in std_logic;
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CLK_I: in std_logic; --! Clock input
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CYC_O: out std_logic;
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CYC_O: out std_logic; --! Cycle output
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DAT_I: in std_logic_vector( 31 downto 0 );
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DAT_I: in std_logic_vector( 31 downto 0 ); --! Data input
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DAT_O: out std_logic_vector( 31 downto 0 );
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DAT_O: out std_logic_vector( 31 downto 0 ); --! Data output
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RST_I: in std_logic;
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RST_I: in std_logic; --! Reset input
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SEL_O: out std_logic;
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SEL_O: out std_logic; --! Select output
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STB_O: out std_logic;
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STB_O: out std_logic; --! Strobe output (Works like a chip select)
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WE_O: out std_logic;
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WE_O: out std_logic; --! Write enable
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-- NON-WISHBONE Signals
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-- NON-WISHBONE Signals
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byte_rec : out std_logic_vector(7 downto 0)
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byte_rec : out std_logic_vector(7 downto 0) --! Signal byte received (Used to debug on the out leds)
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);
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);
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end SERIALMASTER;
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end SERIALMASTER;
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--! @brief Test the uart_wishbone_slave
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--! @details Configure the core then, send the received data back to the PC
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architecture Behavioral of SERIALMASTER is
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architecture Behavioral of SERIALMASTER is
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signal masterSerialStates : testMaster;
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signal masterSerialStates : testMaster;
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signal byteIncome : std_logic_vector(7 downto 0);
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signal byteIncome : std_logic_vector(7 downto 0);
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begin
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begin
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process (CLK_I)
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process (CLK_I)
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variable contWait : integer range 0 to 50000000;
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variable contWait : integer range 0 to 50000000;
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variable cycles2Wait : integer range 0 to 50000000;
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variable cycles2Wait : integer range 0 to 50000000;
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variable nextState: testMaster;
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variable nextState: testMaster;
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begin
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begin
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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if RST_I = '1' then
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masterSerialStates <= idle;
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masterSerialStates <= idle;
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nextState := idle;
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nextState := idle;
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contWait := 0;
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contWait := 0;
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cycles2Wait := 25000000;
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cycles2Wait := 25000000;
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byteIncome <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@';
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byteIncome <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@';
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else
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else
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case masterSerialStates is
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case masterSerialStates is
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when idle =>
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when idle =>
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masterSerialStates <= config_clock;
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masterSerialStates <= config_clock;
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nextState := idle;
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nextState := idle;
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when config_clock =>
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when config_clock =>
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nextState := config_baud;
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nextState := config_baud;
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ADR_O <= "00";
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ADR_O <= "00";
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WE_O <= '1';
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WE_O <= '1';
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STB_O <= '1';
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STB_O <= '1';
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DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz
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DAT_O <= conv_std_logic_vector(50000000, (nBitsLarge)); -- 50Mhz
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if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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byte_rec <= "00000001";
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byte_rec <= "00000001";
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end if;
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end if;
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when config_baud =>
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when config_baud =>
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nextState := send_byte;
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nextState := send_byte;
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ADR_O <= "01";
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ADR_O <= "01";
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WE_O <= '1';
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WE_O <= '1';
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STB_O <= '1';
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STB_O <= '1';
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DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps
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DAT_O <= conv_std_logic_vector(115200, (nBitsLarge)); --115200 bps
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if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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byte_rec <= "00000010";
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byte_rec <= "00000010";
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end if;
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end if;
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when send_byte =>
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when send_byte =>
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nextState := receive_byte;
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nextState := receive_byte;
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ADR_O <= "10";
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ADR_O <= "10";
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WE_O <= '1';
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WE_O <= '1';
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STB_O <= '1';
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STB_O <= '1';
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--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
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--DAT_O <= conv_std_logic_vector(64, (nBitsLarge)); --Send the '@'
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
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DAT_O <= conv_std_logic_vector(0, (nBitsLarge-8)) & byteIncome; --Send the '@'
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if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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cycles2Wait := 7000000;
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cycles2Wait := 7000000;
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end if;
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end if;
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when receive_byte =>
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when receive_byte =>
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nextState := send_byte;
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nextState := send_byte;
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ADR_O <= "11";
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ADR_O <= "11";
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WE_O <= '0';
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WE_O <= '0';
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STB_O <= '1';
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STB_O <= '1';
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if ACK_I = '1' then
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if ACK_I = '1' then
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-- Byte received wait some cycles to continue
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-- Byte received wait some cycles to continue
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masterSerialStates <= wait_cycles;
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masterSerialStates <= wait_cycles;
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byte_rec <= DAT_I(7 downto 0);
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byte_rec <= DAT_I(7 downto 0);
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byteIncome <= DAT_I(7 downto 0);
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byteIncome <= DAT_I(7 downto 0);
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cycles2Wait := 7000000;
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cycles2Wait := 7000000;
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end if;
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end if;
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when wait_cycles =>
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when wait_cycles =>
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-- wait some cycles (90)
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-- wait some cycles
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if contWait < cycles2Wait then
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if contWait < cycles2Wait then
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contWait := contWait + 1;
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contWait := contWait + 1;
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STB_O <= '0';
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STB_O <= '0';
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else
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else
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contWait := 0;
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contWait := 0;
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masterSerialStates <= nextState;
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masterSerialStates <= nextState;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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