--! Unsigned division circuit, based on slow division algorithm (Restoring division)
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--! Unsigned division circuit, based on slow division algorithm (Restoring division)
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--! http://en.wikipedia.org/wiki/Division_%28digital%29
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--! http://en.wikipedia.org/wiki/Division_%28digital%29
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity divisor is
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entity divisor is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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quotient : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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reminder : out STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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numerator : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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divident : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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done : out STD_LOGIC);
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done : out STD_LOGIC);
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end divisor;
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end divisor;
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architecture Behavioral of divisor is
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architecture Behavioral of divisor is
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begin
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begin
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-- Division algorithm Q=N/D
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-- Division algorithm Q=N/D
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process (rst, clk, numerator, divident)
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process (rst, clk, numerator, divident)
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variable Q : unsigned(quotient'length-1 downto 0);
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variable Q : unsigned(quotient'length-1 downto 0);
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variable R : unsigned(reminder'length-1 downto 0);
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variable R : unsigned(reminder'length-1 downto 0);
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variable D : unsigned(reminder'length-1 downto 0);
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variable D : unsigned(reminder'length-1 downto 0);
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variable N : unsigned(reminder'length-1 downto 0);
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variable N : unsigned(reminder'length-1 downto 0);
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variable iteractions : integer;
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variable iteractions : integer;
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begin
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begin
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if (rst = '1') then
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if (rst = '1') then
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quotient <= (others => '0');
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quotient <= (others => '0');
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reminder <= (others => '0');
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reminder <= (others => '0');
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done <= '0';
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done <= '0';
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-- Initialize variables
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-- Initialize variables
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iteractions := quotient'length;
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iteractions := quotient'length;
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D := unsigned(divident);
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D := unsigned(divident);
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N := unsigned(numerator);
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N := unsigned(numerator);
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-- initialize quotient and remainder to zero
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-- initialize quotient and remainder to zero
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Q := (others => '0');
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Q := (others => '0');
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R := (others => '0');
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R := (others => '0');
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if iteractions > 0 then
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if iteractions > 0 then
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iteractions := iteractions - 1;
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iteractions := iteractions - 1;
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-- left-shift R by 1 bit
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-- left-shift R by 1 bit
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R := (R((R'HIGH - 1) downto 0) & '0');
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R := (R((R'HIGH - 1) downto 0) & '0');
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--set the least-significant bit of R equal to bit i of the numerator(dividend)
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--set the least-significant bit of R equal to bit i of the numerator(dividend)
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R(0) := N(iteractions);
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R(0) := N(iteractions);
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if (R >= D) then
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if (R >= D) then
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R := R - D;
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R := R - D;
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Q(iteractions) := '1';
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Q(iteractions) := '1';
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end if;
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end if;
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else
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else
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done <= '1';
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done <= '1';
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quotient <= CONV_STD_LOGIC_VECTOR(Q,32);
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quotient <= CONV_STD_LOGIC_VECTOR(Q,32);
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reminder <= CONV_STD_LOGIC_VECTOR(R,32);
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reminder <= CONV_STD_LOGIC_VECTOR(R,32);
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-- Used to avoid transparent latch (Good practise)
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D := unsigned(divident);
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N := unsigned(numerator);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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