--! Data receiver
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--! Data receiver
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--! http://www.fpga4fun.com/SerialInterface.html
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--! http://www.fpga4fun.com/SerialInterface.html
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity serial_receiver is
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entity serial_receiver is
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Port (
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Port (
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rst : in STD_LOGIC;
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rst : in STD_LOGIC;
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baudClk : in STD_LOGIC;
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baudClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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baudOverSampleClk : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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serial_in : in STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_ready : out STD_LOGIC;
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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data_byte : out STD_LOGIC_VECTOR ((nBits-1) downto 0));
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end serial_receiver;
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end serial_receiver;
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architecture Behavioral of serial_receiver is
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architecture Behavioral of serial_receiver is
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signal current_s,next_s: rxStates;
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signal current_s,next_s: rxStates;
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signal filterRx : rxFilterStates;
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signal filterRx : rxFilterStates;
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signal syncDetected : std_logic;
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signal syncDetected : std_logic;
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begin
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begin
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-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC
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-- First we need to oversample(8x baud rate) out serial channel to syncronize with the PC
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process (rst, baudOverSampleClk, serial_in, current_s)
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process (rst, baudOverSampleClk, serial_in, current_s)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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filterRx <= s0;
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filterRx <= s0;
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syncDetected <= '0';
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syncDetected <= '0';
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elsif rising_edge(baudOverSampleClk) then
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elsif rising_edge(baudOverSampleClk) then
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case filterRx is
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case filterRx is
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when s0 =>
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when s0 =>
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syncDetected <= '0';
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syncDetected <= '0';
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-- Spike down detected, verify if it's valid for at least 3 cycles
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-- Spike down detected, verify if it's valid for at least 3 cycles
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s1;
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filterRx <= s1;
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else
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else
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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when s1 =>
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when s1 =>
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syncDetected <= '0';
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syncDetected <= '0';
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s2;
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filterRx <= s2;
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syncDetected <= '0';
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syncDetected <= '0';
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else
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else
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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when s2 =>
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when s2 =>
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syncDetected <= '0';
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syncDetected <= '0';
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s3;
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filterRx <= s3;
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syncDetected <= '0';
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syncDetected <= '0';
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else
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else
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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when s3 =>
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when s3 =>
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-- Real Beginning of start bit detected
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-- Real Beginning of start bit detected
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if serial_in = '0' then
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if serial_in = '0' then
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filterRx <= s3;
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filterRx <= s3;
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syncDetected <= '1';
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syncDetected <= '1';
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end if;
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end if;
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-- Reset out sync detector when finished to receive a byte
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-- Reset out sync detector when finished to receive a byte
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if current_s = rx_stop then
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if current_s = rx_stop then
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filterRx <= s0;
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filterRx <= s0;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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-- Next state logic for rx Receiver (On this case our reset is the syncDetected signal
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-- Next state logic for rx Receiver (On this case our reset is the syncDetected signal
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process (syncDetected, baudClk, serial_in)
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process (syncDetected, baudClk, serial_in)
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begin
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begin
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if syncDetected = '0' then
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if syncDetected = '0' then
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current_s <= rx_idle;
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current_s <= rx_idle;
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elsif rising_edge(baudClk) then
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elsif rising_edge(baudClk) then
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current_s <= next_s;
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current_s <= next_s;
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end if;
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end if;
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end process;
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end process;
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-- Process to handle the serial receive
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-- Process to handle the serial receive
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process (current_s)
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process (current_s)
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variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
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variable byteReceived : STD_LOGIC_VECTOR ((nBits-1) downto 0);
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begin
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begin
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case current_s is
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case current_s is
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when rx_idle =>
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when rx_idle =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived := (others => 'Z');
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byteReceived := (others => 'Z');
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next_s <= bit0;
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next_s <= bit0;
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when bit0 =>
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when bit0 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(0) := serial_in;
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byteReceived(0) := serial_in;
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next_s <= bit1;
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next_s <= bit1;
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when bit1 =>
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when bit1 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(1) := serial_in;
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byteReceived(1) := serial_in;
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next_s <= bit2;
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next_s <= bit2;
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when bit2 =>
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when bit2 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(2) := serial_in;
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byteReceived(2) := serial_in;
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next_s <= bit3;
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next_s <= bit3;
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when bit3 =>
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when bit3 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(3) := serial_in;
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byteReceived(3) := serial_in;
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next_s <= bit4;
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next_s <= bit4;
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when bit4 =>
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when bit4 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(4) := serial_in;
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byteReceived(4) := serial_in;
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next_s <= bit5;
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next_s <= bit5;
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when bit5 =>
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when bit5 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(5) := serial_in;
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byteReceived(5) := serial_in;
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next_s <= bit6;
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next_s <= bit6;
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when bit6 =>
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when bit6 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(6) := serial_in;
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byteReceived(6) := serial_in;
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next_s <= bit7;
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next_s <= bit7;
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when bit7 =>
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when bit7 =>
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data_ready <= '0';
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data_ready <= '0';
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byteReceived(7) := serial_in;
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byteReceived(7) := serial_in;
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data_byte <= byteReceived;
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next_s <= rx_stop;
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next_s <= rx_stop;
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when rx_stop =>
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when rx_stop =>
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data_ready <= '1';
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data_ready <= '1';
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data_byte <= byteReceived;
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next_s <= rx_stop;
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next_s <= rx_stop;
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end case;
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end case;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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