--! Data transmitter
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--! @file
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--! http://www.fpga4fun.com/SerialInterface.html
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--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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--! Use CPU Definitions package
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--! Use CPU Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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entity serial_transmitter is
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entity serial_transmitter is
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Port ( rst : in STD_LOGIC;
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Port ( rst : in STD_LOGIC; --! Reset input
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baudClk : in STD_LOGIC;
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baudClk : in STD_LOGIC; --! Baud rate clock input
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0);
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data_byte : in STD_LOGIC_VECTOR ((nBits-1) downto 0); --! Byte to be sent
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data_sent : out STD_LOGIC;
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data_sent : out STD_LOGIC; --! Indicate that byte has been sent
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serial_out : out STD_LOGIC);
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serial_out : out STD_LOGIC); --! Uart serial output
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end serial_transmitter;
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end serial_transmitter;
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--! @brief Serial transmitter http://www.fpga4fun.com/SerialInterface.html
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--! @details Implement block that serialize the "data_byte" signal on a stream of bits clocked out by "baudClk"
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architecture Behavioral of serial_transmitter is
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architecture Behavioral of serial_transmitter is
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signal current_s,next_s: txStates;
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signal current_s,next_s: txStates;
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begin
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begin
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-- Next state process
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-- Next state process
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process (rst, baudClk)
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process (rst, baudClk)
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begin
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begin
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if rst = '1' then
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if rst = '1' then
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current_s <= tx_idle;
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current_s <= tx_idle;
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elsif rising_edge(baudClk) then
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elsif rising_edge(baudClk) then
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current_s <= next_s;
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current_s <= next_s;
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end if;
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end if;
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end process;
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end process;
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process (current_s, data_byte)
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process (current_s, data_byte)
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begin
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begin
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case current_s is
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case current_s is
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when tx_idle =>
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when tx_idle =>
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serial_out <= '1';
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serial_out <= '1';
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data_sent <= '0';
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data_sent <= '0';
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next_s <= tx_start;
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next_s <= tx_start;
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-- Start bit
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-- Start bit
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when tx_start =>
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when tx_start =>
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serial_out <= '0';
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serial_out <= '0';
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit0;
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next_s <= bit0;
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when bit0 => -- Send the least significat bit
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when bit0 => -- Send the least significat bit
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serial_out <= data_byte(0);
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serial_out <= data_byte(0);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit1;
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next_s <= bit1;
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when bit1 =>
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when bit1 =>
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serial_out <= data_byte(1);
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serial_out <= data_byte(1);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit2;
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next_s <= bit2;
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when bit2 =>
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when bit2 =>
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serial_out <= data_byte(2);
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serial_out <= data_byte(2);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit3;
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next_s <= bit3;
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when bit3 =>
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when bit3 =>
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serial_out <= data_byte(3);
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serial_out <= data_byte(3);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit4;
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next_s <= bit4;
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when bit4 =>
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when bit4 =>
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serial_out <= data_byte(4);
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serial_out <= data_byte(4);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit5;
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next_s <= bit5;
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when bit5 =>
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when bit5 =>
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serial_out <= data_byte(5);
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serial_out <= data_byte(5);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit6;
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next_s <= bit6;
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when bit6 =>
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when bit6 =>
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serial_out <= data_byte(6);
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serial_out <= data_byte(6);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= bit7;
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next_s <= bit7;
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when bit7 => -- Send the most significat bit
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when bit7 => -- Send the most significat bit
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serial_out <= data_byte(7);
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serial_out <= data_byte(7);
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data_sent <= '0';
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data_sent <= '0';
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next_s <= tx_stop1;
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next_s <= tx_stop1;
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when tx_stop1 =>
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when tx_stop1 =>
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serial_out <= '1';
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serial_out <= '1';
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data_sent <= '1';
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data_sent <= '1';
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next_s <= tx_stop2;
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next_s <= tx_stop2;
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when tx_stop2 => -- Stop here and wait for other reset
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when tx_stop2 => -- Stop here and wait for other reset
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serial_out <= '1';
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serial_out <= '1';
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data_sent <= '1';
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data_sent <= '1';
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next_s <= tx_stop2;
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next_s <= tx_stop2;
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end case;
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end case;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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