--! Test baud_generator module
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--! Test baud_generator module
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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--! Use Global Definitions package
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--! Use Global Definitions package
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use work.pkgDefinitions.all;
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use work.pkgDefinitions.all;
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ENTITY testBaud_generator IS
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ENTITY testBaud_generator IS
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END testBaud_generator;
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END testBaud_generator;
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ARCHITECTURE behavior OF testBaud_generator IS
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ARCHITECTURE behavior OF testBaud_generator IS
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COMPONENT baud_generator
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COMPONENT baud_generator
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PORT(
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PORT(
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rst : IN std_logic;
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rst : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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cycle_wait : in STD_LOGIC_VECTOR ((nBitsLarge-1) downto 0);
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baud_oversample : out std_logic;
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baud_oversample : out std_logic;
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baud : OUT std_logic
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baud : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal cycle_wait : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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--Outputs
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--Outputs
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signal baud : std_logic;
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signal baud : std_logic;
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signal baud_oversample : std_logic;
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signal baud_oversample : std_logic;
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-- Clock period definitions (1.8432MHz)
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-- Clock period definitions (1.8432MHz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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--! Instantiate the Unit Under Test (UUT)
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uut: baud_generator PORT MAP (
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uut: baud_generator PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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cycle_wait => cycle_wait,
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cycle_wait => cycle_wait,
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baud_oversample => baud_oversample,
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baud_oversample => baud_oversample,
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baud => baud
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baud => baud
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- Test the baud generator waiting for 16 clock cycles for 1.8432MHz clock
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-- Test the baud generator waiting for 16 clock cycles for 1.8432MHz clock
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rst <= '1';
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rst <= '1';
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cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
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cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
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wait for 2 ns;
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wait for 2 ns;
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rst <= '0';
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rst <= '0';
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wait for clk_period*300;
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wait for clk_period*300;
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-- Stop Simulation
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-- Stop Simulation
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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wait;
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wait;
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end process;
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end process;
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END;
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END;
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