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--! Test divisor module
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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:35:04 04/20/2012
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-- Design Name:
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-- Module Name: /home/laraujo/work/uartVHDLWishBone/testDivisor.vhd
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-- Project Name: uartVHDLWishBone
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: divisor
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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--! Use Global Definitions package
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-- arithmetic functions with Signed or Unsigned values
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use work.pkgDefinitions.all;
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--USE ieee.numeric_std.ALL;
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ENTITY testDivisor IS
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ENTITY testDivisor IS
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END testDivisor;
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END testDivisor;
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ARCHITECTURE behavior OF testDivisor IS
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ARCHITECTURE behavior OF testDivisor IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT divisor
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COMPONENT divisor
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PORT(
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PORT(
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rst : IN std_logic;
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rst : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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quotient : OUT std_logic_vector(31 downto 0);
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quotient : OUT std_logic_vector((nBitsLarge-1) downto 0);
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reminder : OUT std_logic_vector(31 downto 0);
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reminder : OUT std_logic_vector((nBitsLarge-1) downto 0);
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numerator : IN std_logic_vector(31 downto 0);
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numerator : IN std_logic_vector((nBitsLarge-1) downto 0);
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divident : IN std_logic_vector(31 downto 0);
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divident : IN std_logic_vector((nBitsLarge-1) downto 0);
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done : OUT std_logic
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done : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal rst : std_logic := '0';
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signal rst : std_logic := '0';
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal numerator : std_logic_vector(31 downto 0) := (others => '0');
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signal numerator : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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signal divident : std_logic_vector(31 downto 0) := (others => '0');
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signal divident : std_logic_vector((nBitsLarge-1) downto 0) := (others => '0');
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--Outputs
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--Outputs
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signal quotient : std_logic_vector(31 downto 0);
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signal quotient : std_logic_vector((nBitsLarge-1) downto 0);
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signal reminder : std_logic_vector(31 downto 0);
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signal reminder : std_logic_vector((nBitsLarge-1) downto 0);
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signal done : std_logic;
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signal done : std_logic;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant clk_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: divisor PORT MAP (
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uut: divisor PORT MAP (
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rst => rst,
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rst => rst,
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clk => clk,
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clk => clk,
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quotient => quotient,
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quotient => quotient,
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reminder => reminder,
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reminder => reminder,
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numerator => numerator,
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numerator => numerator,
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divident => divident,
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divident => divident,
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done => done
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done => done
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- hold reset state for 100 ns.
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-- hold reset state for 100 ns.
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rst <= '1';
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rst <= '1';
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numerator <= conv_std_logic_vector(50000000, 32);
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numerator <= conv_std_logic_vector(50000000, 32);
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divident <= conv_std_logic_vector(115200, 32);
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divident <= conv_std_logic_vector(115200, 32);
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wait for 20 ns;
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wait for 20 ns;
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rst <= '0';
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rst <= '0';
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wait until done = '1';
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wait until done = '1';
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wait for clk_period;
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wait for clk_period;
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rst <= '1';
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rst <= '1';
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numerator <= conv_std_logic_vector(40, 32);
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numerator <= conv_std_logic_vector(40, 32);
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divident <= conv_std_logic_vector(5, 32);
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divident <= conv_std_logic_vector(5, 32);
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wait for 20 ns;
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wait for 20 ns;
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rst <= '0';
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rst <= '0';
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wait until done = '1';
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wait until done = '1';
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wait for clk_period;
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wait for clk_period;
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-- insert stimulus here
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-- insert stimulus here
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assert false report "NONE. End of simulation." severity failure;
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assert false report "NONE. End of simulation." severity failure;
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end process;
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end process;
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END;
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END;
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